FULCRU COMPUTER PRODUCTS

Size: px

Start display at page:

Download "FULCRU COMPUTER PRODUCTS"

Joanna Morris
5 years ago
Views:

1 ,re,e,., 488 FULCRU COMPUTER PRODUCTS TM 1 82 FULCRUM (EUROPE) VAllEY HOUSE PURlEIGH ESSEX, ENGLAND CM3 6QH TelEPHONE: (0621) Exclusively distributed by:

3 I-EEE 488/3P BYTE INTERFACE DESCRIPTION The is designed to be plugged into one slot of a standard S-100. ~, (IEEE-696 cardcage. The central processor unit (CPU) supplies the instructions to be performed by the The consists of two major functional blocks: leee-488 Interface Three parallel ports The leee-488 portion of the board is designed to perform the interface function between an IEEE /78 General Purpose Interface Bus (GPIB) and the CPU. It communicates with the CPU via an input/output-mapped 8-bit data bus and provides a 16-bit bus to interface with the GPIB via buffer devices. IEEE /78 standard protocol is hand.led automatical1y in Talker, Listener, and Bus or System Controller operational modes. The three parallel input/output (I/O) ports portion of the board is designed to perform as a general purpose programmable I/O device. It has 24 I/O pins which may be individually programmed in two groups of twelve and used in three major modes of operation. In Mode 0 each group. of twelve I/O pins may be programmed in sets of 4 to be input or output. In Mode 1 each g~oup lllaybe programmed. to have 8 lines of input or output. Of the remaining four pins three are used for hand.shaking and interrupt control signals. fuode 2 is a Bi-directional Bus mode which uses 8 lines for a ~i-directional Bus, and five lines, borrowing one from the other group, ~for handshaking. The 488+3's flexibility is enhanced by switches/jumpers which allow the user to select input/output port ac.dresses, interrupt priorities, my address, sy.stem or not system controller, ana. system clock ( ) or 2 lviliz clock. The software I/O driver routines supplied with the facilitate its use. These programs are callable subroutines for performing message handling. The manner in which they have been written allows them to be easily incorporated into a software program. IEEE 488 Functions Handles all IEEE /78 functions Talker and listener functions (T~TE,L,LE) Automatic source and acceptor handshakes (SH,AH) Controller with pass control capabilities (C) Device clear and trigger functions (DC,DT) Service request functions (SR) ~ Parallel and. serial poll facilities (PP,SP) L

4 Remote/local with local lockout (RL) ~k Single or dual addressing modes Secondary addressing capabilities INTRODUCTION TO THE IEEE /78 INTERFACE BUS The G.PIB is designed to allow up to 15 instruments within a localized area to coullilunicateyd.th each other over a common bus. Each device has a unique address, read from external switches at power-on, to which it responds. Information is transmitted in byte-serial bit-parallel format and may consist of ei.ther data or interface control inform.ation. Device data may be sent by anyone device (TAlhER) and received by a number or other devices (LISTENElill). Instructions stich as select range, select function, or measurement data for processing or printout may be sent in this way. One of the devices on the bus, designated the Controller in charge (ContI'oller), may send interface control messages. Devices can be assigned to the bus as listeners or talkers by sending"their unique talk or listen addresses, and may be switched between remote and local control. One device on the bus must be the system controller and be the only device which controls the lllterface clear mld remote enable lines. The can be the system controller, just a device on the bus, or a controller in charge. The bus itself consists of a 24 wire shielded cable. 8 lines carry data; 8 are control lines; 8 are signal system grounds. Three of the bus management lines operate as a three line handsh~~e between talker (or controller) a.nd listeners. No new data is sent until each device addressed to listen has received the last byte and is ready for the next byte 0 This method of asynchronous corrununication ensures that the data rate is suited to the slowest active listener, as well as ensuring compatibility over a wide range of devices.

5 SPECIFI l)hysical GNU GNS Ch2xacte:ri.sti.cs The occupies one cm:'d position in an SIOO cardcage. I< k-. ---~(;~37D--- 10,00-- {-.~,I9,S-7r! or it) ~J..ERflrvC Outline Derninsion:: oj' the 488+). XX XX>< -..!

6 ~ ~._._-~-_._-----_ ~-_._ Envionmental Cb2Tacteristics Temperature: Oper.ating Non-operating note: OCto +50 C -50 c to +85 C The dissipates 5 watts. Adequate circula,tion of air muf3t be pl'ovided to :prevent a temper'ai.\it8 rise above +50 c. Humidity: Operating Non-operating up tc. 90% relative humidity vii thout condensation. all condition,'iithout condensation or frost. DC Power Requirements +8 volts +3/-1 O. 8 amp maxinrrnil

7 HAIIDWARE The 488+3's architecture can be broken down into five functional areas: \"---..-/ 488 Bus Interface 488 Controller Parallel Ports Controller IEEE 696 Interface Miscellaneous Logic Figure 4.1 shows the manner in which these functional blocks are interconnected. IEEE Bus Interface. The IEEE 488 interface consists of two buffers. The 488 bus is physically connected to the through a 26 - pin connector. The interface to the IEEE 488 data bus is handled by 75160A. This is an octal bus transceiver designed to provide communication on the IEEE 488 data bus. An active turn-off feature has been incorporated into the busterminating resistors so that the device exhibits a high impedance to the bus when VCC=OV. ~ The interface to the IEEE 488 data transfer and bus management signals on the IEEE 488 bus is han6led by a 75162A. This is an octal bus transceiver designed to provide con@unication on the IEEE 488 control bus. The 75162A is designed to perform in a single or two controller system. Direction of bus management signals BEN and IFC are determined by the SC input, while SRQ, ATN, and EOI are determined by the DC input. Data transfer signals DAV, NDAC, and Nfu"'Ddirection are determined by the 'fe input. 'llhelevel of SC is controlled by a socket. When SC is high, the is the system conti.'oller md may transmit REi.'T and IFC and if required. 'fhe IEEE 488 bus controller is Tl~lS99'14. It performs the interface function between the CPU and IEEE 488 bus and it relieves the CPU of the task of maintaining the IEEE protocol. By utilizing the interrupt capabilities of the device the bus does not have to be continually polled, and fast responses to changes in the interface configuration can be achieved. The TN~ 9914 input/output lines are connected to the IEEE 488 bus via bus transceivers as previously described. The direction of data flow is controlled by the TE and CONTROLl~~ outputs generated by TN The TE and CCNTROLLER signals are routed within the 75160A and 75162A so that the buffers on particular lines are controlled by the Tk 9914 as required. Communication between the CPU and the TN~ 9914 is carried out via input/output mapped registers. There are 13 registers within TRS 9914 six of which are read and seven of which are write. They are used both to pass control data and get status information from the TlviS9914. The three least significant address lines from the CPU are connected to the register select lines RSO, RS1, and Iill2;they determine the particular register selected. The high order address lines (A7-A3) are decoded on the to Gause the CE input to the TlVlS9914 to be pulled low when 8J:J..Y one of 8 consecutive addresses are selected. ThQS the internal registers appear to be situated at 8 consecutive locations within the CPU input/output address space. Input or '.tput instructions to these locations transfer information betweer! the TlvlS9914 ~.d the CPU. Note that input or output instructions to the same location will not access the same register within the TI\.S9914 since they are read only or write only registers. s

For example, an.input operation with HS2 - Il~30 == 011 gives the current status of the IEEE 488 bus interface control lines, whereas an outp11t to this location loads the auxilary command register.

8 For example, an.input operation with HS2 - Il~30 == 011 gives the current status of the IEEE 488 bus interface control lines, whereas an outp11t to this location loads the auxilary command register. Eac~ device on the bus interface is given a 5-bit address enabling it to be addressed as a talker or listener. This adciress is set on SVi3 before poweron and is read by the CPU and then written into the address register as part of the initialization px ocedure. rrhe Ti,.S99"\ 4 responds by causing a ma (hiy Address) interrupt and enteri.ng the required addressed state when this address is o.etected on the IEEE 488 data lines. Par~llel Ports Controller The 8255 is prograuwlable Peripheral Interface device designed for use in microp:r:ocessor systems. Its function is that of a general purpose r/o component to interface periphexal equipment to the microcomputer system bus. rrhe funct.ional configuration of the 8255A is progxammed by the systelligoftware so that normally no external logic is necessary to i.nterface peripheral devices or structures. IEEE 696 Interface All Address lines and data buses in and out are fully buffered and jwuper pads are provided to route interrupt signe.ls. Software The softwa~e supplied with the consists of Input/output drivers written in ~illasic. The ffiainfunctions of the drivers are to initialize the ~~S at power-on ~nd to simplify the issuing of commands to the IEEE 488 Bus Controller. The I/O drivers allow illirreciateuse of the as experience and understanding are gained. They may be restructured OI.' completely rewritten to better suit tde particular application. / (<, / :> )... ) /

5 The GP Interface Bus

5 The GP Interface Bus In this chapter... Introduction to the System Interface Buses, 5-2 The GPIB Statements, 5-3 Addressing the Bus And Bus Devices, 5-5 A Reference Description of the GPIB, 5-8 Objectives