CS 251, Winter 2019, Assignment % of course mark

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1 CS 25, Winter 29, Assignment.. 3% of corse mark De Wednesday, arch 3th, 5:3P Lates accepted ntil Thrsday arch th, pm with a 5% penalty. (7 points) In the diagram below, the mlticycle compter from the corse notes is eecting the instrction 96 beq $,$2,2 in the EX state. The EX/E register bank will be written to at the end of the clock cycle. In the figre below, there are seven nmbered dark lines, each above one of the lines or control lines in the path. Above each dark line write the vale on the line jst before the end of the clock cycle; if the vale on the line can not be determined from the information given, write?. 2 IF/ID ID/EX EX/E E/ Shift left 2 reslt 3 PC ress Instrction Instrction register register 2 Registers 2 register Zero reslt ress Data 6 Sign etend CONTROL

2 2. ( points) Describe 3 differences between the lticycle path and the Single Cycle path. In addition to the 3 differences, discss how the individal instrction eection time has changed in the lticycle path. 3. ( points) Consider the following IPS code seqence: 2 lw $3, ($2) 2 add $3, $, $5 28 add $, $3, $ 22 add $, $3, $ (a) (5 pts) In the diagram below, each row is labeled with an eected instrction. ark all dependencies by drawing straight lines (similar to Figre.52 of the tet) between when the reslt is stored in the register file and when it needs to be taken from the register file. Assme that the code is to rn on the pipelined path of Fig..5 of the 5th edition; this path implements neither stalling nor forwarding. For each dependency, label it either as a hazard or as a non-hazard. CC CC2 CC3 CC CC5 CC6 CC7 CC8 2 lw $3, ($2) I Reg D Reg 2 add $3,$,$5 I Reg D Reg 28 add $,$3,$ I Reg D Reg 22 add $,$3,$ I Reg D Reg 2

3 (b) (5 pts) odify the code to remove the hazards by inserting a minimm nmber of NOPs. Line # Code 3

4 . (6 points) odify the pipelined path provided on the net page to incorporate the jmp register instrction. The instrction will set PC to the address provided in the $rs sorce register. PC <= $rs a) ( points) the jr $rs (jmp register) instrction to the pipeline stage where it is most efficient. Yo may add new control lines, mltipleors or additional components as needed. arks will be dedcted for inefficiency. Note: the jr $rs instrction will work similarly to the jmp instrction stdied in the Single Cycle path. Yo do not need to modify the address in $rs; we assme is it a mltiple of for. The following eection shows eamples of instrctions seqences that are possible with jr $rs. We want to implement the instrction and modify PC with the vale in $rs as soon as possible to avoid errant instrctions beginning eection. Yo do not need to implement any flshing. Yo may assme that nwanted instrctions following the jr or branch instrctions are flshed. Yo may also assme that the necessary forwarding hardware will be added in order to ensre the vale in $rs is correct in any stage of the pipelined path. jr $ beq $2, $, -5 beq $2, $, -5 add $, $3, $2 add $, $3, $2 add $, $3, $2 8 sb $6, $7, $8 8 jr $ 8 addi $,$, - 2 addi $, $, - 2 addi $, $, - 2 jr $ 6 lw $3, ($2) 6 lw $3, ($2) 6 lw $3, ($2) Yo do not need to consider the case where branch is immediately followed by jr. Yo do need to consider the cases listed above in order to implement jr correctly in the appropriate pipeline stage. b) (2 points) State the vale of any new control bits as needed for the jr instrction added in part(a). Also, state the vale of the new control bits for all other instrctions sing the path.

5 PC Instrction Instrction Instrction [2 6] emtoreg Op Branch RegDst Src 6 32 Instrction [5 ] reslt Registers register 2 register register 2 Sign etend reslt Zero control Shift left 2 Reg em Control Instrction [5 ] 6 EX IF/ID PCSrc ID/EX EX/E E/ em ress Data 5ress

6 5. (7 points) This qestion refers to the pipelined path withot forwarding, shown below and in Figre.5 in the tetbook. Consider the instrctions add $2, $3, $ beq $, $2, 6 8 lw $, 8($6) 2 add $2, $2, $ Consider the pipeline when the add instrction is in the stage, the beq instrction is in the E stage, the 8 lw instrction is in the EX stage, and the 2 add instrction is in the ID stage. In the figre below, state the decimal vales on the nmbered blank lines -7. In this figre, the instrctions have been drawn above the appropriate set of pipeline stages. Note: The blank lines do not refer to control bits. Line #2 refers to read register, line #6 refers to the address going into. All other line nmbers refer to the decimal vale on the line immediately below or beside it. Before these instrctions begin eection, register i contains the vale 22 + i. PCSrc add $2,$2,$ lw $, 8($6) beq $,$2,6 add $2,$3,$ Control ID/EX EX/E E/ PC ress Instrction IF/ID Instrction. 2. register register 2 Registers 2 register Reg EX Shift left 2 reslt 3. Src Zero reslt Branch ress em Data emtoreg Instrction 6 32 [5 ] Sign etend 6 control em Instrction [2 6] Instrction [5 ] RegDst Op 7. 6

7 6. (3 points) This qestion refers to the pipelined path from the previos qestion on this assignment. State how many bits wide the Intermediate Register EX/E mst be in order to store all the reqired and control bits. Yo mst show yor work. 7

8 7. ( points) This qestion refers to the pipelined path withot forwarding, shown below and in Figre.5 in the tetbook. Consider the instrctions add $2, $3, $ beq $, $2, 6 8 lw $, 8($6) 2 add $2, $2, $ Consider the pipeline when the add instrction is in the stage, the beq instrction is in the E stage, the 8 lw instrction is in the EX stage, and the 2 add instrction is in the ID stage. In the figre below, label all of the control signals (inclding both those coming directly ot of the control nit and those coming ot of the pipeline registers) with their appropriate vales, sing don t cares where appropriate. In this figre, the instrctions have been drawn above the appropriate set of pipeline registers. We have also filled in the soltion for the stage, and given the names of the control signals whose vales yo need to determine for the other three stages. PCSrc add $2,$2,$ lw $, 8($6) beq $,$2,6 add $2,$3,$ Control ID/EX EX/E E/ IF/ID EX PC ress Instrction Instrction register register 2 Registers 2 register Reg Shift left 2 reslt Src Zero reslt Branch ress em Data emtoreg Instrction 6 32 [5 ] Sign etend 6 control em Instrction [2 6] Instrction [5 ] RegDst Op emtoreg= Branch= em= RegDst= Op= Src= Reg= em= emtoreg= Branch= em= RegDst= Op= Src= Reg= em= emtoreg= Reg= Branch= em= em= Reg= emtoreg= 8

9 8. (5 points) This qestion refers to the pipelined path with forwarding in Figre.56 of the tetbook and also given in the corse notes. Consider the instrctions 2 addi $, $, 2 add $3, $, $ 28 add $3, $, $3 Consider the sitation when the addi instrction is in the stage, the add instrction is in the E stage, and the 8 add instrction is in the EX stage. In the figre below, trace back each of the two inpts to the throgh the UXes back to the appropriate set of pipeline registers (i.e., trace a path from the back to the pipeline registers where the vales are stored). Yo may se bold dark or zigzag lines to clearly indicate yor work. IF/ID Control add $3,$,$3 add $3,$,$ addi $,$, ID/EX EX EX/E E/ PC Instrction Instrction Registers Data IF/ID.RegisterRs IF/ID.RegisterRt IF/ID.RegisterRt IF/ID.RegisterRd Rs Rt Rt Rd Forwarding nit EX/E.RegisterRd E/.RegisterRd 9

10 itional eercises for pipeline architectre: Eercise -9, -, -3, -.