CSSE232 Computer Architecture I. Mul5cycle Datapath

Transcription

1 CSSE232 Compter Architectre I Ml5cycle Datapath

2 Class Stats Next 3 days : Ml5cycle datapath ing Ml5cycle datapath is not in the book!

3 How long do instrc5ons take? ALU 2ns Mem 2ns Reg File 1ns Everything else is free!

4 How long do instrc5ons take? ALU 2ns Mem 2ns Reg File 1ns Everything else is free! R- type? Branch? Store? Load?

5 Otline Problems with single- cycle Steps IF, ID, EXEC, MEM, WB RTL (Register Transfer Langage) Describe processor ac5ons

6 Single Cycle Design Problems What are they?

7 Single Cycle Design Problems Fixed period clock Every instrc5on takes one clock cycle All cycles same length Cycle 5me set by longest instrc5on path (lw) Some instrc5ons cold rn faster What if we have very long instrc5ons? (floa5ng point) Many adders Dplicate hardware is a waste?

8 Improving Single Cycle Redce hardware se? Redce 5me se?

9 Improving Single Cycle Redce hardware se? Very hard, all parts are needed Redce 5me se? Variable length clock Longer for lw, shorter for branch Has been done, hard to do in prac5ce Shorter clock cycles Break work into small steps Con5ne instrc5on if not finished azer step

10 Ml5cycle Break instrc5ons into steps Each step takes one cycle Each step needs approximately the same 5me Each step ses one piece of hardware Save instrc5on data between steps Save par5al work at end of cycle Next cycle, con5ne instrc5on

11 PCSrc 4 Add Shift left 2 Add ALU reslt M x PC address memory register 1 register 2 Write register Write data RegWrite Registers data 1 data 2 16 Sign 32 extend ALUSrc M x 3 ALU operation Zero ALU ALU reslt Address Write data Mem MemWrite data Data memory MemtoReg M x ALU 2ns Mem 2ns Reg 1ns

12 Breaking instrc5ons into steps Or goal is to break p the instrc5ons into steps so that each step takes one clock cycle the amont of work to be done in each step/cycle is abot eqal each cycle ses at most once each major fnc5onal nit so that sch nits do not have to be replicated fnc5onal nits can be shared between different cycles within one instrc5on Data at end of one cycle to be sed in next mst be stored!!

13 Breaking instrc5ons into steps We break instrc5ons into the following poten/al exec5on steps not all instrc5ons reqire all the steps each step takes one clock cycle 1. Instrc5on fetch and PC increment (IF) 2. Instrc5on decode and register fetch (ID) 3. Exec5on, memory address compta5on, or branch comple5on (EX) 4. Memory access or R- type instrc5on comple5on (MEM) 5. Memory read comple5on (WB) Each MIPS instrc5on takes from 3 5 cycles (steps)

14 Step 1: Instrc5on Fetch & PC Increment (IF) Use PC to get instrc5on and pt it in the instrc5on register. Increment the PC by 4 and pt the reslt back in the PC. Can be described sccinctly sing RTL (Register- Transfer Langage): IR = Memory[PC]; PC = PC + 4;

15 Step 2: Instrc5on Decode and Register Fetch (ID) registers rs and rt in case we need them. Compte the branch address in case the instrc5on is a branch. RTL: A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOt = PC + (sign-extend(ir[15-0]) << 2);

16 Step 3: Exec5on, Address Compta5on or Branch Comple5on (EX) ALU performs one of for fnc5ons depending on instrc5on type memory reference: ALUOt = A + sign-extend(ir[15-0]); R- type: ALUOt = A op B; branch (instrc5on completes): if (A==B) PC = ALUOt; jmp (instrc5on completes): PC = PC[31-28] (IR(25-0) << 2) Note that the PC is wriden twice!!

17 Step 4: Memory access or R- type Instrc5on Comple5on (MEM) Again depending on instrc5on type: Loads and stores access memory load MDR = Memory[ALUOt]; store (instrc5on completes) Memory[ALUOt] = B; R- type (instrc5ons completes) Reg[IR[15-11]] = ALUOt;

18 Step 5: Memory Comple5on (WB) Again depending on instrc5on type: Load writes back (instrc5on completes) Reg[IR[20-16]]= MDR; Important: There is no reason from a datapath (or control) point of view that Step 5 cannot be eliminated by performing Reg[IR[20-16]]= Memory[ALUOt]; for loads in Step 4. This wold eliminate the MDR as well. The reason this is not done is that, to keep steps balanced in length, the design restric5on is to allow each step to contain at most one ALU opera5on, or one register access, or one memory access.

19 Smmary of Instrc5on Exec5on Step 1: IF 2: ID 3: EX 4: MEM 5: WB Step name fetch decode/register fetch Action for R-type instrctions Action for memory-reference Action for instrctions branches IR = Memory[PC] PC = PC + 4 A = Reg [IR[25-21]] B = Reg [IR[20-16]] ALUOt = PC + (sign-extend (IR[15-0]) << 2) Action for jmps Exection, address ALUOt = A op B ALUOt = A + sign-extend if (A ==B) then PC = PC [31-28] II comptation, branch/ (IR[15-0]) PC = ALUOt (IR[25-0]<<2) jmp completion Memory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOt] completion ALUOt or Store: Memory [ALUOt] = B Memory read completion Load: Reg[IR[20-16]] = MDR

20 Ml5cycle Approach PCSrc 4 Add Shift left 2 Add ALU reslt M x PC address memory register 1 register 2 Write register Write data Registers data 1 data 2 RegWrite 16 Sign 32 extend ALUSrc M x 3 ALU operation Zero ALU ALU reslt Address Write data Mem MemWrite data Data memory MemtoReg M x Single-cycle datapath

21 Ml5cycle Approach Note par5clari5es of PC ml5cyle vs. single- diagrams single memory for data and instrc5ons single ALU, no extra adders extra registers to hold data between clock cycles 4 address Add memory register 1 register 2 Write register Write data Registers data 1 data 2 RegWrite 16 Sign 32 extend Shift left 2 ALUSrc M x Add ALU reslt 3 ALU operation Zero ALU ALU reslt Single-cycle datapath PCSrc M x Address Write data Mem MemWrite data Data memory MemtoReg M x PC Address Memory Data or data register Memory data register Data Register # Registers Register # Register # A B ALU ALUOt Mlticycle datapath (high-level view)

22 Ml5cycle Datapath PC 0 M x 1 Address Write data Memory MemData [25 21] [20 16] [15 0] register [15 0] Memory data register [15 11] 0 M x 1 0 M x 1 16 register 1 register 2 Registers Write register Write data Sign extend data 1 data 2 32 Shift left 2 A B 4 0 M x M 2 x 3 Zero ALU ALU reslt ALUOt Basic mlticycle MIPS datapath handles R-type instrctions and load/stores: new internal registers and new mltiplexors in ovals.

23 Ml5cycle Datapath PC 0 M x 1 Address Write data Memory MemData [25 21] [20 16] [15 0] register [15 0] Memory data register [15 11] 0 M x 1 0 M x 1 16 register 1 register 2 Registers Write register Write data Sign extend data 1 data 2 32 Shift left 2 A B 4 0 M x M 2 x 3 Zero ALU ALU reslt ALUOt Basic mlticycle MIPS datapath handles R-type instrctions and load/stores: new internal registers and new mltiplexors in ovals.

24 Ml5cycle Exec5on Step (1): Instrc5on Fetch IR = Memory[PC]; PC = PC + 4; PC + 4 4!

25 Ml5cycle Exec5on Step (2): Instrc5on Decode & Register Fetch A = Reg[IR[25-21]]; (A = Reg[rs]) B = Reg[IR[20-15]]; (B = Reg[rt]) ALUOt = (PC + sign-extend(ir[15-0]) << 2) Reg[rs] Branch Target Address PC + 4 Reg[rt]

26 Ml5cycle Exec5on Step (3): Memory Reference Instrc5ons ALUOt = A + sign-extend(ir[15-0]); Reg[rs] Mem. Address PC + 4 Reg[rt]

27 Ml5cycle Exec5on Step (3): ALUOt = A op B ALU Instrc5on (R- Type) Reg[rs] R- Type Reslt PC + 4 Reg[rt]

28 Ml5cycle Exec5on Step (3): Branch Instrc5ons if (A == B) PC = ALUOt; Reg[rs] Branch Target Address Branch Target Address Reg[rt]

29 Ml5cycle Exec5on Step (3): Jmp Instrc5on PC = PC[31-28] concat (IR[25-0] << 2) Reg[rs] Branch Target Address Jmp Address Reg[rt]

30 Ml5cycle Exec5on Step (4): Memory Access - (lw) MDR = Memory[ALUOt]; Reg[rs] Mem. Address PC + 4 Mem. Data Reg[rt]

31 Ml5cycle Exec5on Step (4): Memory Access - Write (sw) Memory[ALUOt] = B; Reg[rs] PC + 4 Reg[rt]

32 Ml5cycle Exec5on Step (4): ALU Instrc5on (R- Type) Reg[IR[15:11]] = ALUOUT Reg[rs] R- Type Reslt PC + 4 Reg[rt]

33 Ml5cycle Exec5on Step (5): Memory Comple5on (lw) Reg[IR[20-16]] = MDR; Reg[rs] Mem. Address PC + 4 Mem. Data Reg[rt]

34 Review and Qes5ons Problems with single- cycle Steps RTL