ECE 313 Computer Organization Name SOLUTION EXAM 2 November 3, Floating Point 20 Points

Transcription

1 ECE Computer Organization Name SOLTION EA November, This exam is open book and open notes. Credit for problems requiring calculation will be given only if you show your work.. Floating Point Points Translate the IEEE single-precision floating point numbers shown below to their decimal equivalent and write them in the space provided below. Value of number: -. two (-7) = = -46 Value of number:. two (7-7) = = Value of number: NaN (Not a Number) Zero exponent => Denormalized number! Value of number:.two -6 =.97-6 =.86-9 Page of

2 ECE Computer Organization Name SOLTION EA November,. Verilog / Logic & Arithmetic Points We would like to design a shifter module in Verilog with the inputs, outputs, and function described below. When =, it shifts the input left by the number of bits specified by AT. When =, it shifts the input right by the number of bits specified by AT. All shifts are logical shifts, i.e., the values that are shifted in are all zero. AT SHIN SHOT SHOT SHIN << AT SHIN >> AT Fill in the Verilog module declaration below to show all input and output ports and the behavioral code necessary to perform the desired function (you may use either an assign statement or an always block). module (, AT, SHIN, SHOT); input ; input [4:] AT; input [:] SHIN; output [:] SHOT; reg [:] SHOT; or AT or SHIN) if () SHOT = SHIN >> AT; else SHOT = SHIN << AT; endmodule Alternative solution using assign module (, AT, SHIN, SHOT); input ; input [4:] AT; input [:] SHIN; output [:] SHOT; assign SHOT = (? SHIN >> AT : SHIN << AT ); endmodule Page of

3 ECE Computer Organization Name SOLTION EA November,. Single-Cycle Processor Design Points odify the single-cycle processor design in the book to implement the shifting instruction srl (shift-right-logical) using the shifter designed in problem. The srl instruction is used in assembly language like this: srl rd, rt, shamt The register transfer for this instruction is as follows: Reg[rd] <- Reg[rt] >> shamt; The srl instruction is encoded as an R-Type instruction, with opcode= and funct=.. Show all changes to the datapath along with any changes to the nit or AL modules in the space provided below. ADD PC pc 4 ADDR RD Instruction emory instr nit 6 RN RN WN RD Register File RegWrite AL 6 opcode funct 6 immed ALOp RD E 6 T N shamt D instr[-6] RegDst ALSrc Reg[rt] << Operation AL AT SHIN SHOT ADD Zero PCSrc Branch emwrite ADDR Data emory RD emread ShOrAL emtoreg ShDir There are two ways to approach the control for this problem: ) Add a row to the truth table of the control unit (requires that nit looks at both opcode and funct) in this case, modify only the nit table AL stays the same. ) odify the AL but not the control unit (se existing control unit signals for R-Type instructions) odified tables are shown on the next page Page of

4 ECE Computer Organization Name SOLTION EA November, Approach nit (ust add funct input) No Change to AL emto- Reg Reg Write em Read em Write Branch ALOp ALp ShDir ShOrAL Instruction RegDst ALSrc R-format lw sw beq srl Approach AL No Change to nit ALOp Funct field Operation ALOp ALOp F F4 F F F F ShDir ShOrAL. Single-Cycle Processor Timing Points Assume that the shifter module has a delay of ns. (a) Calculate delay of the longest path in your modified circuit when performing the srl instruction. em Fetch Reg. Read Shift Reg. Write Total ns ns ns 7 ns (b) Calculate the longest path for all instructions in your modified circuit. The longest path is still for the load word instruction em Fetch Reg. Read AL Operation em Read Reg. Write Total ns ns 8 ns Page 4 of

5 ECE Computer Organization Name SOLTION EA November, 4. ulticycle Processor Design (Datapath) Points We wish to modify the multicycle processor design to implement the srl instruction described in Problem. Show all changes on the diagram on the next page. Zero PCWriteEnable PCWriteCond PCWrite nit ALOp AL IRWrite pc_next PC pc IorD mem_addr emwrite ADDR emory RD emread mem_rd I R DR op 6 I[:6] funct 6I[:] 6 immed mdr rfile_wd emtoreg rs rt RN RN WN Registers RD RegWrite j_offset rd RegDst rfile_wn RD rfile_rd A B rfile_rd a b 4 8 j_addr << CONCAT ALSrcA aluout_in Operation alu_a AL Zero ShOrAL j_sh alu_b AL OT PCSource aluout 6 E T << shamt N D extend_immed instr[-6] ALSrcB b_offset AT SHIN SHOT ShDIr Page of