Real-Time Graphics Architecture

Transcription

1 Real-Time Graphics Architecture Lecture 4: Parallelism and Communication Kurt Akeley Pat Hanrahan Topics 1. Frame buffers 2. Types of parallelism 3. Communication patterns and requirements 4. Sorting classification for parallel rendering (with examples) 1

2 Frame Buffers er vs. calligraphic er (image order) dominant choice Calligraphic (object order) Earliest choice (Sketchpad) E&S terminals in the 70s and 80s Works with light pens Scene complexity affects frame rate Monitors are expensive Still required for FAA simulation Increases absolute brightness of light points 2

3 Frame buffer definitions What is a frame buffer? What can we learn by considering different definitions? Frame buffer definition #1 Storage for commands that are executed to refresh the display Allows for raster or calligraphic display (e.g. Megatech) Frame buffer for calligraphic display is a display list OpenGL render list? Key point: frame buffer contents are interpreted Color mapping Image scaling, warping Window system (overlay, separate windows, ) Address Recalculation Pipeline 3

4 Frame buffer definition #2 Image memory used to decouple the render frame rate from the display frame rate Meets common understanding of frame buffer as image Leads naturally to double buffering One render buffer, one display buffer, swap n-buffering also possible, can control latency Key idea: decoupling enables general-purpose GPU Visual simulation has high render frame rate MCAD has low render frame rate Window manager has no frame rate Frame buffer definition #3 All pixel-assigned memory used to assemble and display the images being rendered Key point: frame buffer is active participant in rendering Leads to non-color buffers: depth, stencil, window control OpenGL treats these buffers as part of frame buffer Some reserve frame buffer for color images Should be n-buffered in some cases (sort last) RealityEngine frame buffer can be deeper than wide or high History cycles through this definition 2-D manipulation 3-D painters algorithm 3-D depth, stencil, accumulation, multi-pass Programmable shading 4

5 Frame buffer is optional Calligraphic display If we don t define display list as frame buffer Follow-the-beam rendering Minimizes latency Saves cost if frames are never dropped Talisman-like image assembly (3-D sprites) Old idea (visual simulation, window systems) GigaPixel render tile Frame buffer stores color images only Depth, stencil, etc. in small tile Dominant architecture is consistent SGI architectures look like ATI architectures, which look like NVIDIA architectures Details are evolving, but big picture remains the same Why is this? Simplicity of design Simplicity of algorithms Simplicity of immediate-mode approach 5

6 Simplicity of design Frame buffer operations Blending: merge fragment and pixel color Depth Buffering: save nearest fragment Stencil Buffering: simple pixel state machine Accumulation Buffering: high-resolution color arithmetic Antialiasing: (to be covered later). All frame buffer operations: Combine fragment and pixel data (not just a replace) But replace operation is optimized, e.g., no parity/ecc Are local (no intra-pixel dependencies) Why aren t fragment operations programmable? Simplicity of algorithms Frame buffer employs brute-force simplicity Hidden surface elimination: Depth-buffer vs. sort/painter Capping: Stencil-based vs. object calculations Image-space algorithm is efficient Just samples, never object information, locality Just-in-time calculation, steady cost function Accumulation Buffer (high-resolution color arithmetic) The Accumulation Buffer, Haeberli and Akeley, Proceedings of SIGGRAPH 90 Volume rendering using 3D textures Multi-pass rendering Interactive Multi-pass Programmable Shading, Peercy, Olano, Airey, and Ungar, Proceedings of SIGGRAPH 00 6

7 Simplicity of immediate-mode Frame buffer contents are context Matches 2D/window-rendering model Rendering System Little graphics state here Frame buffer: most graphics state here Decreasing display bandwidth burden Historically display bandwidth was a limiting factor Hence Sproull s Rule : fill rate >= display rate Now display bandwidth is almost inconsequential Year System FB (GB) Disp (GB) Disp / FB 1984 SGI 2000-series / SGI GTX 1.8 * / SGI InfiniteReality / NVIDIA 7900 GTX /70 * VRAM provided separate video bandwidth 7

8 Parallelism and Communication Parallelism and communication Parallelism using multiple computational units to processes work in parallel Communication connecting the computational units to allow work to be distributed and aggregated Issues Dependencies Ordering Sorting Scalability Computation Bandwidth Load balancing 8

9 Parallelism taxonomy Hardware parallelism (simultaneous execution on multiple processors) Virtual parallelism (time sharing a single processor, usually with hardware support) Data parallelism [aka parallelism ] (same task on similar data sets) Task parallelism (different tasks on similar OR differing data sets) Parallelism taxonomy Hardware parallelism (simultaneous execution on multiple processors) Virtual parallelism (time sharing a single processor, usually with hardware support) Data parallelism [aka parallelism ] (same task on similar data sets) Frame-parallelism (batch, SGI N-clops) Object-parallelism (geometry) Image-parallelism (fragment/pixel) Task parallelism (different tasks on similar OR differing data sets) 9

10 Parallelism taxonomy Hardware parallelism (simultaneous execution on multiple processors) Virtual parallelism (time sharing a single processor, usually with hardware support) Data parallelism [aka parallelism ] (same task on similar data sets) Task parallelism (different tasks on similar OR differing data sets) Frame-parallelism (batch, SGI N-clops) Object-parallelism (geometry) Image-parallelism (fragment/pixel) Multi-processing (on multiple CPUs) Pipelining (the graphics pipeline) Parallelism taxonomy Data parallelism [aka parallelism ] (same task on similar data sets) Hardware parallelism (simultaneous execution on multiple processors) Frame-parallelism (batch, SGI N-clops) Object-parallelism (geometry) Image-parallelism (fragment/pixel) Virtual parallelism (time sharing a single processor, usually with hardware support) Multi-processing (graphics context switching) Multi-threading (almost defines a GPU-like processor) Task parallelism (different tasks on similar OR differing data sets) Multi-processing (on multiple CPUs) Pipelining (the graphics pipeline) 10

11 Parallelism taxonomy Data parallelism [aka parallelism ] (same task on similar data sets) Task parallelism (different tasks on similar OR differing data sets) Hardware parallelism (simultaneous execution on multiple processors) Frame-parallelism (batch, SGI N-clops) Object-parallelism (geometry) Image-parallelism (fragment/pixel) Multi-processing (on multiple CPUs) Pipelining (the graphics pipeline) Virtual parallelism (time sharing a single processor, usually with hardware support) Multi-processing (graphics context switching) Multi-threading (almost defines a GPU-like processor) Multi-processing (time sharing a single CPU) Multi-threading (Direct3D-10 commoncore ) Graphics is embarrassingly parallel Ample self-similar data sets Frames, vertexes, fragments, texels, pixels With minimal dependencies Few intra-set dependencies Pixels (in the frame buffer) are the significant exception Inter-set dependencies are purely sequential Graphics pipeline is designed to minimize dependencies Other graphics architectures have more dependencies E.g., for global lighting effects But graphics pipeline has huge redundancies Hence many opportunities for optimization How hard should we work to do things wrong? 11

12 etry parallelism trend (SGI) Model Transform Length Transform Width G GTX VGX RE IR Image parallelism trend (SGI) erization G GTX VGX RE IR 12

13 The clear trend Shorter and wider Why? Communication taxonomy Sorting Distribution Object Image Routing (Introduced by parallelism) (Introduced by parallelism) Texturing Fundamental 13

14 Sorting is fundamental Sorting Distribution Object Image Routing Texturing I. E. Sutherland, R. F. Sproull, and R. A. Schumacher, A characterization of ten hidden surface algorithms Classified by order of x, y, z radix sorts Pipelining vs. parallelism Issue Ordering dependencies Sorting dependencies Computation scalability Bandwidth scalability Load balancing scalability Task Parallelism (pipelining) Easy Easy Data Parallelism Challenging Challenging 14

15 Pipelining vs. parallelism Issue Ordering dependencies Sorting dependencies Computation scalability Bandwidth scalability Load balancing scalability Task Parallelism (pipelining) Easy Easy Poor Poor (Nearly) impossible Data Parallelism Challenging Challenging Challenging Challenging Challenging Ordering challenges Fundamental: Frame buffer operations Painter s algorithm Memory hazards Texture writes Render Copy to texture Render Readback From pipelining: Changes to graphics state 15

16 Sorting taxonomy Application Command etry erization Texture Fragment Display Sort-First Sort-Middle Sort-Last Fragment Sort-Last Image Composition Sort-First 16

17 Sort-first App App Pre-transformation Cmd SORT Cmd Point-to-point communication scales Tex Tex Coarse tiling incurs load imbalance Frag Frag Disp Disp Princeton Display Wall, Stanford WireGL Sort-first Order Automatic (conceptually) Sort Pre-stage (cheat ) Compute scalability Good Bandwidth scalability Good Load balance scalability Poor 17

18 Sort-first App Cmd Tex Frag SORT ROUTE Disp App Cmd Tex Frag Ring parallelism App Cmd Tex Frag DIST Cmd DIST Cmd DIST DIST Cmd Tex Tex Tex Frag Frag Frag ROUTE Disp 3DLABs 18

19 Sort-Middle Image-space work distribution Parke - Tiled Fuchs - Interleaved 19

20 Sort-middle interleaved App DISTRIBUTE Cmd Cmd etry work load-balanced, Tex Frag SORT ROUTE Disp Tex Frag except clipping and tesselation Broadcast communication does not scale, but supports ordering Finely interleaved screen tiling ensures es excellent load balance SGI Graphics Workstations: RealityEngine, InfiniteReality Sort-middle interleaved Order Force sequence at triangle sort Sort Broadcast Compute scalability Good Bandwidth scalability Limited by sort broadcast Load balance scalability Good 20

21 SGI RealityEngine 240 MB/s 1600 MB/s 3200 MB/s Sort-middle tiled App Cmd Tex Frag Disp SORT ROUTE App Cmd Tex Frag Disp UNC PixelPlanes, Stanford Argus Point-to-point communication scales Coarse tiling incurs load imbalance 21

22 Sort-middle tiled (immediate mode) Order Force sequence at triangle sort Sort Can approach point-to-point Compute scalability Good Bandwidth scalability Good Load balance scalability Poor for rasterization (due to large triangles) Sort-middle tiled (chunked) Order Sort Force sequence at triangle sort Full-frame delay, render to texture difficulties Can approach point-to-point Compute scalability Good Bandwidth scalability Good Load balance scalability Good 22

23 UNC Pixel-Planes5 (1990) Sort-Last 23

24 Sort-last fragment App Cmd Tex Frag SORT ROUTE App Cmd Tex Frag Improved texture locality No redundant work in FG Exposes rasterization load imbalance to application Point-to-point communication scales, but requires more bw Finely interleaved screen tiling insures excellent load balance Disp Disp Possible, but difficult, to maintain ordering Kubota Denali, E&S Freedom 3000 Sort-last fragment Order Force sequence at fragment sort Sort Point-to-point, high bandwidth Compute scalability Good Bandwidth scalability OK (sorting is the bottleneck) Load balance scalability OK (exposed to application) 24

25 Kubota Denali (1993) TEM 48 5 X6 24 X10 FBM Denali Technical Overview 1.0 Kubota Pacific Computer, 1993 Image composition Z comp Other combiners possible 25

26 Sort-last image composition App Cmd App Cmd Exposes rasterization load imbalance to application Point-to-point ring interconnect scales Tex Tex Frag Frag Disp SORT Disp Two-stage image composition loses ordering UNC/HP PixelFlow, Aizu VC-1, Stanford Lightning-2 Sort-last image composition Order Not fully supported! Sort One to many for each pipeline Compute scalability Excellent Bandwidth scalability Excellent Load balance scalability OK (exposed to application) 26

27 UNC Pixel Flow From J. Poulton, J. Eyles, S. Molnar, H. Fuchs, Pixel Flow: The Realization 27

28 Sort-Everywhere Sort-everywhere: Pomegranate App Cmd Mem Tex Mem Frag Disp DISTRIBUTE SORT ROUTE App Cmd Tex Mem Frag Mem Disp 28

29 Architecture comparison X indicates an issue Sort-first interleaved Sort-middle i Sort-middle tiled (immd) Sort-middle tiled (chunk) Sort-last frag gment Sort-last ima age comp. Sort-everywh here Ordered (X) X Compute scalability Bandwidth scalability X X Load balance scalability X X X X Summary GPU architecture trend Pipeline hardware-parallel virtual-parallel 29

30 Readings Required 1. S. Molnar, M. Cox, D. Ellsworth, H. Fuchs, A sorting classification of parallel rendering 2. Fuchs et al., A heterogenous multiprocessor graphics system using processor-enhanced memories (PP5). 3. Eyles et al., PixelFlow: The Realization Recommended 1. F. I. Parke, Simulation and expected performance analysis of multiple processor z-buffer systems 2. H. Fuchs, Distributing a visible surface algorithm over multiple processors Real-Time Graphics Architecture Lecture 4: Parallelism and Communication Kurt Akeley Pat Hanrahan 30