M32: A Constructive Multilevel Logic Synthesis System*

Transcription

1 M32: A Construtive Multilevel Logi Synthesis System* Vitor N. Kravets Karem A. Sakallah Department of Eletrial Engineering and Computer Siene University of Mihigan, Ann Arbor, MI {vkravets, karem}@ees.umih.edu Abstrat We desribe a new onstrutive multilevel logi synthesis system that integrates the traditionally separate tehnology-independent and tehnology-dependent stages of modern synthesis tools. Dubbed M32, this system is apable of generating iruits inrementally based on both funtional as well as strutural onsiderations. This is ahieved by maintaining a dynami strutural representation of the evolving implementation and by refining it through progressive introdution of gates from a target tehnology library. Ciruit onstrution proeeds from the primary inputs towards the primary outputs. Preliminary experimental results show that iruits generated using this approah are generally superior to those produed by multi-stage synthesis. I. Introdution and Motivation In this paper we desribe a new multilevel logi synthesis system, M32, that departs in several important respets from urrent pratie in logi synthesis tehnology. The development of M32 was motivated by the oft-ited refrain that wires are starting to dominate ative logi in determining the area and speed of deep submiron ICs, and that urrent synthesis flows are biased primarily towards optimizing gates. M32 was designed to address this bias by intertwining the traditionally separate stages of tehnologyindependent Boolean optimization and tehnology-dependent mapping in a onstrutive synthesis strategy that is ognizant of the strutural impliations of optimization deisions. Suh generation of the tehnology speifi iruit from the initial steps makes the task of assessing final design quality more aurate from the initial steps of synthesis, and allows exploration of degrees of freedom whih are lost in the split between tehnology-independent and tehnology-dependent stages of synthesis. The remainder of this paper is organized as follows. Setion II gives a brief desription of prior work. A synthesis algorithm based on the onstrutive synthesis methodology is then presented in Setion III. It overomes the limitations of previous onstrutive approahes and benefits from reent advanes in synthesis tehnology, allowing it to handle muh larger iruits. Its prototype implementation in the M32 synthesis system has been demonstrated for ombinational iruits ontaining several thousand gates. An example illustrating exeution of the algorithm is given in Setion IV. Experimental results are disussed in Setion V. II. Prior Work Combinational multilevel logi synthesis is the proess of implementing a set of logi expressions using ells from a tehnology library, eah with a presribed funtion and physial harateristis *This researh was supported by DARPA under ontrat DAAH04-94-G Permission to make digital or hard opies of all or part of this work for personal or lassroom use is granted without fee provided that opies are not made or distributed for profit or ommerial advantage and that opies bear this notie and the full itation on the first page. To opy otherwise, to republish, to post on servers or to redistribute to lists, requires prior speifi permission and/or a fee. DAC 98, June 15-19, 1998, San Franiso, CA USA ISBN x/98/06 $ [26]. Most of the urrent logi synthesis systems divide the logi synthesis proess into tehnology-independent [4] and tehnologydependent stages [16, 10]. The tehnology-independent stage fouses on partitioning the logi, whereas the tehnology-dependent stage hooses appropriate gates from the library to implement the partitioned logi. Suh multi-stage approahes to omplex optimization problems are ommon in eletroni design automation (e.g. plaement followed by routing) and are usually neessitated by the diffiulty of solving these problems simultaneously. This serialization of the optimization proess implies that deisions made in earlier stages must neessarily be based on loose estimates of what later stages an aomplish. At the same time, the solutions produed by early stages plae limitations on the degrees of freedom to improve final implementation of a design. For two-stage logi synthesis, deisions made during the tehnology-independent stage [5, 7, 6] signifiantly determine the struture of a iruit. They are made with no regard for the downstream tehnology. When the tehnology harateristis beome available in the mapping stage it is often too late to augment the effets of these deisions to improve iruit quality. The bak-annotated approahes, whih perform resynthesis after tehnology speifi information is extrated from the mapped iruit, ompensate partially for this problem. This is typially done by re-synthesizing ritial setions identified during the sign-off proess [14, 31, 2, 20, 13, 27]. While this yields improvement in iruit quality, tehnology-independent and tehnology-dependent transformations still remain disonneted. In [19], the authors address this problem by dynamially modifying the set of AND2/ INV deompositions while deleting others based on the atual ost funtion used in tehnology mapping. It allows tehnology-independent transformations to be part of the tehnology mapping. However, these transformations do not exhibit global knowledge about iruit struture and funtionality. Reently, De Miheli [21] disussed onurrent tehnology mapping and optimization by utilizing the don t-are sets of the bound portion of the network. The potentially detrimental effets of serializing logi synthesis beome more pronouned in fine-feature CMOS ICs where interonnetions tend to dominate both area and delay [17]. For example, hanges in the average topologial wire length of a iruit, an signifiantly ontribute to the post-layout delay and routing area [18]. It is therefore ritial for a synthesis tool to have aurate estimation of wiring from the initial stages of synthesis. In [29], the authors pursued this problem by relying on the traditional synthesis methods, aounting for routing area during logi deomposition using heuristis for minimizing the fanout ranges of a deomposed network. Another method of minimizing routing ost by deriving and maintaining an order among the primary inputs of the iruit was proposed in [24, 1]. These approahes operate during the early phase of synthesis, and remain removed from the final implementation iruit. In [23] an attempt is made to aount for the interonnetions during the tehnology mapping phase of synthesis. The idea is to generate a ompanion plaement solution for the iruit before it is mapped. This plaement is then dynamially updated as the mapping proess tries to evaluate the ost of a mathing gate. The algorithm estimates the interonnetion ontribution to the area and delay by referring to the dynamially updated plaement of the network. Using this tehnique, the authors were able to generate iruits with shorter wire lengths and

2 Initial speifiation network F1 F3 Partial implementation network F1 Final implementation network F2 -- Unimplemented -- Implemented F2 F3 F1 F2 F3 smaller area. Several attempts to synthesize networks inrementally are reported in the literature. Davidson presented a branh-and-bound algorithm for NAND network synthesis [9]. The algorithm onstruts a network realization inrementally starting from the primary outputs. In eah iteration, the algorithm extends a partial solution by introduing a new NAND gate together with its fanin onnetions. Another inremental synthesis proedure for arbitrary gates was presented by Shneider and Dietmeyer [25]. In eah step, their algorithm finds the iruit pakage (i.e. gate type in a tehnology library) that satisfies some goal, suh as area and delay, while meeting fanin, loading and power onstraints. Suh approahes, however, did not yield pratial synthesis tools: their exponential run time omplexity rendered them useless exept for very small iruits. III. The M32 Logi Synthesis System M32 is a multilevel tehnology-dependent onstrutive logi synthesis system. It relies on extended algebrai deomposition tehniques whih define a feasible spae of transformations whih an be applied to sum-of-produts expressions. The M32 algorithm performs iruit transformations that aount for the topologial harateristis of the evolving network struture in the ontext of a speifi gate library. The system is urrently geared towards performane-oriented synthesis whih also minimizes average topologial wire length. In this setion we first give an overview of the system, and then desribe its main features in detail. A. System Overview Fig. 1. Illustration of the onstrutive tehnology-dependent synthesis The overall synthesis proess in M32 is depited in Fig. 1. The state of the synthesis proess is modeled by a Boolean network η [3] that aptures an evolving strutural representation of the funtions being synthesized. Eah vertex v in suh a network has an assoiated Boolean funtion f v that omputes the logi value at the vertex s output in terms of the logi values on its inputs. A vertex is onsidered to be implemented if its funtion is equivalent to one of the funtions in a given gate library L, and unimplemented otherwise. To insure an onto mapping from L to the verties in η, the library must, at a minimum, have inverter and pass-through wire gates as well as any 2-input gate that makes it funtionally omplete. Reading its funtional speifiation F as a set of multi-output ubes, M32 onstruts an initial speifiation network onsisting of implemented verties orresponding to the primary inputs and unimplemented verties orresponding to the speified output funtions f 1, f 2,, f n. As the synthesis proess evolves, the funtions of unimplemented verties are suessively deomposed in terms of those of already implemented verties, resulting in a series of partial implementation networks. The deomposition is losely tied with the given gate library, and leads to the reation of new implemented verties, i.e. verties that orrespond to library gates. Eah implemented vertex v introdues a new variable y v whih an now be used to simplify the funtions of unimplemented verties. The effet of these suessive deompositions is an expansion of η from the PIs towards the POs as more implemented verties are reated and as the funtional omplexity of unimplemented verties is redued. This onstrutive reation proess makes it possible to ontrol the strutural omplexity of the evolving implementation. The synthesis proess terminates when all verties beome implemented yielding a final implementation network. The main loop in the M32 synthesis algorithm is shown in the pseudo-ode of Fig. 2. The algorithm treats F and η as globally aessible strutures. In eah iteration, the funtions of unimplemented verties are examined and one of them, f k, is seleted for a deomposition step. An atomi divisor P is extrated from f k by an appropriate division proedure. The divisor is subsequently implemented by a small set of verties orresponding to gates from L leading to the expansion of the implemented part of η. The deomposition step is ompleted by substituting the variables y v of the newly reated verties into the funtions of the unimplemented verties. An unimplemented vertex beomes implemented when its funtion redues to a single literal. Thus, the iteration stops, signalling ompletion of the synthesis proess, when all the funtions in F have been redued to single literals. This algorithm has several features that distinguish it from ommonly-used synthesis methods: It interleaves funtional deomposition and tehnology mapping throughout the synthesis proess It onsiders the strutural impliations of andidate deompositions It seletively applies Boolean transformations to improve synthesis quality without adversely affeting run time effiieny The remainder of this setion is devoted to detailed desriptions of the four main routines of the algorithm. B. SeletFuntion The order in whih the funtions of F are deomposed learly affets the final synthesized implementation. In eah iteration of the algorithm, the set of verties that are andidates for deomposition is the subset of unimplemented verties whose fanins are already implemented. The SeletFuntion routine identifies the next funtion to deompose by greedily hoosing the andidate vertex whose funtion has the largest number of literals in its ube representation. This hoie is motivated by the expetation that larger, riher, funtions yield better divisors. In this ontext, divisor P 1 is onsidered better than divisor P 2 if the verties in its implementation subiruit represent better opportunities for sharing among the unimplemented verties. More sophistiated seletion strategies an be easily envisioned, espeially when the initial speifiation is a multi-level network. C. GenerateDivisor Like most modern synthesis algorithms, M32 relies on an effiient division proedure to deompose a funtion f into the form pq + r. The most ommonly used division proedure is weak division [7] whih is applied to an SOP expression for f and is equivalent to exluding all Boolean transformations exept for the distributive law. While primarily motivated by the need for a fast division operation, weak division has been empirially shown to yield aeptable deompositions in pratie. Still, the quality of the divisors, as measured by the total number of literals in the resulting fatored form, an be improved by the judiious appliation of 337

3 while exists f i F suh that f i is not a single literal do { k SeletFuntion( ); P GeneratateDivisor( f k ); ẏ v IntrodueGates( P) ; Substitute( P, ẏ v ); } Fig. 2. Synthesis loop in the M32 system additional Boolean transformations. The division operation in M32 augments the distributive law with the annihilation ( a a = 0) and idempoteny ( aa = a ) properties to generate better deompositions. This additional flexibility omes at a modest omputational ost. It is interesting to note that limiting allowable transformations of Boolean expressions to the above three properties (distributivity, annihilation, and idempoteny) guarantees that any generated fatored form will reprodue the original SOP over under flattening [15]. This, in turn, implies that different initial SOP representations of a funtion an lead to different deompositions. Removal of this bias requires the deployment of the entire arsenal of Boolean transformations, i.e. operating in the unrestrited funtional domain. In general, the attendant improvement in the quality of suh unrestrited deomposition omes at a steep omputational ost to be pratial. M32 partially ompensates for this bias by intertwining deomposition with mapping to a speifi gate library while managing the strutural attributes of the evolving implementation. Divisor seletion in M32 is aomplished through suessive fatorization, using the distributive law, of repeated literals from an SOP expression f. The annihilation and idempoteny transformations are subsequently invoked to modify the resulting quotient and redue the literal ost of the deomposition. This proess is iterated until eah literal appears only one in the fatored form. To aount for the strutural impliations of partiular deompositions, literals are hosen based on a strutural ost metri that is omputed aording to: [ depth( f ẋ) depth( ẏ v )] ost() ẋ = (1) ourrene( ẏ v, f ẋ) size ( f ẋ ) ẏ v support( f ẋ) where ẋ is a andidate literal in expression f and f/ẋ is the quotient resulting from algebrai division of f by ẋ. The term support( f ẋ) in the formula denotes the set of literals appearing in f ẋ. The depth of a literal, depth( ẏ v ), is the topologial depth of its orresponding vertex v in η; the depth of a primary input is defined to be 0. Similarly, the depth of expression f ẋ, or a set of literals, is the maximum depth of any of its literals plus 1. Given f ẋ, ourrene( ) denotes the number of times a literal ẏ v ours in the expression, and size( ) is the total number of literal ourrenes in it. GenerateDivisor reates a divisor by suessively seleting the next andidate literal with least ost aording to (1). D. IntrodueGates Unlike onventional tehnology mappers that operate on an intermediate optimized Boolean network obtained in a prior tehnology-independent phase, M32 losely ties its reation of gates with funtional deomposition. As soon as a divisor P is found by GenerateDivisor, IntrodueGates proeeds to map it to the given gate library. The mapping proess is also different from those used in onventional synthesis tools: no intermediate subjet graph is onstruted. Similar to GenerateDivisor, this proedure is aware of the strutural impliations of its hoies, and involves iterating the following steps until P is fully implemented by library gates: 1. A gate from the tehnology library with its suitable variable support in P is seleted for instantiation as vertex v 2. The vertex v, along with possible fanin inverters, is instantiated and added to η; variable y v is assoiated with the new vertex v 3. The divisor P is re-expressed in terms of y v The implementation of IntrodueGates is urrently limited to a small tehnology library defined by L = { wire, INV, NAND2}. Thus, the gate type seletion step in the above proedure is unneessary. Enhanements to IntrodueGates that are urrently underway extend its apabilities to riher gate libraries. The seletion of a suitable variable support in step 1 is also simplified by this library hoie. Candidate variable subsets are determined by examining all assoiative groupings of literal pairs in P for boolean mathing [22] to NAND2, and seleting the best pair. Again, quality in this ontext is estimated by a strutural metri: a pair of literals whih instantiate a vertex v of least depth is greedily seleted. (The depth of v in η is determined from the depth of verties in its support, while aounting for the possible presene of an inverter on v s fanin lines.) To break ties between the andidate supports we have used estimated signal arrival times based on the SIS-1.2 library model. In our experiments we have used nominal delay and apaitane was taken from the MCNC library. After a gate support and its phases are determined, it is introdued into the iruit by establishing its fanin onnetions and plaing an inverter (either a new one or reusing a previously introdued one) on eah onnetion whih has negative input phase. No inverter is plaed on the gate output regardless of the output phase. Finally, divisor P is re-expressed in terms of this newly introdued gate, leading to a redution in its size. The proess ontinues until P is redued to a single literal. This literal is then returned by the IntrodueGates routine, and is later used to substitute it for P in F. E. Substitute At eah iteration of the algorithm routine Substitute re-expresses funtions f 1,, f n of the unimplemented verties in network η in terms of the newly introdued verties. The substitutions applied to the funtions are based on the division operation. If pq + r is the result of dividing f by p then substitution re-expresses f as ẏ v q + r, where ẏ v is a new literal. As in the GenerateDivisor step, the division operation utilizes the distributive, idempotent and annihilation laws. In addition, ube redution using the sharp produt A#B AB' [11] is used to maximize the sharing of potential divisors. Substitute re-expresses f 1,, f n in two steps: (1) substituting literal ẏ v ( y' v ) for the P ( P' ) funtion; and (2) substituting variables of newly introdued verties for their gate funtions, modulo the phase assignment on its inputs determined in IntrodueGates. These steps are applied to eah of the funtions f 1,, f n individually. The routine performs substitution seletively to minimize topologial ost. In the first step Substitute uses the literal returned by the IntrodueGates routine, whih orresponds to the output vertex of a subiruit implementing P. The seond step of the routine implements substitutions of finer granularity. Substitution of gate funtions in this step is performed for eah of the verties in their topologial order. Note that substitution using the distributive law only does not require step (1), sine it is subsumed by step (2). We should also point out that the division under the used properties may not be unique. This is illustrated in the example below, where annihilation gives rise to two distint deompositions: Example 3.1 Suppose f = ab'e' + a'bd + a'de' + a'de, and let P = a'e' + a'd be a divisor of f. We then an have two different quotients q 1 = b + 'd + e and q 2 = b+ ad + a'e. Thus either substitution f = y v ( b + 'd + e) or f = y v ( b+ ad + a'e) is feasible. IV. An M32 Synthesis Example Synthesis of a full adder will be used as an example of the M32 system. M32 first reads the funtional speifiation z = a b = a'b' + a'b' + ab'' + ab (2) = ab + a + b (3) 338

4 a b ( a b) y1 z = ( y 1 ' + ab' ) y2 = ab + y 3 z = y 3 = y 4 ' + y 5 ' y4 y5 = y 4 ' + y 3 y3 y6 = y 6 = y 6... z = y 3... TABLE I: Pre-layout synthesis results Ciruit SIS-1.2 M32 Norm. Name Inp.Outp. Cubes Gates Lev.Compl. Delay GatesLev.Compl. Delay Delay z4ml vda in ount ldd b ex ordi ps duke vg apex sqrt bw lip ( ab + a + b) Fig. 3. M32 synthesis steps of the full adder of the iruit to be synthesized. Thus, F = { z, } is the set of unimplemented verties to be synthesized. The algorithm then selets funtion z sine it has more literals then. A subexpression P seleted from z by the GenerateDivisor routine is a'b + ab'. GenerateDivisor selets this divisor sine it has the least ost, with the assumption that signal arrives later than the two other input signals a and b. This expression is then implemented using IntrodueGates by introduing gates y 1, y 2, and y 3 through the following sequene of transformations of P: P a'b + ab' y' 1 + ab' y' 1 + y' 2 y 3. (4) The Substitute funtion would then substitute y 3 for ab' + a'b (omplement substitution is also tried) in both z and, giving: z = y 3 ' + 'y 3 (5) = ab + y 3. (6) Note that ab' + a'b is not an algebrai divisor of ab + a + b. Therefore substitution based on weak division alone would not bring any hanges to. The Substitute routine makes substitution in possible due to the ube redution based on the sharp produt operation. The M32 system detets that the division beomes possible if ubes a and b are redued to a'b and ab respetively. This is a valid transformation sine the result of a#ab' and b#a'b, whih is in both ases ube ab, is overed by the ube ab. It is now easy to see that a'b + ab' divides expression ab + ab' + a'b, representing the same arry-out funtion : ab + ( ab' + a'b). The next step in the Substitute routine is to see if any of the loal funtions of verties y 1, y 2 or y 3 an be used to re-express either z or. No further substitutions are possible in this ase. This ompletes the first iteration of the algorithm in Fig. 2. On the next iteration of the loop either the unimplemented vertex for out or z an be seleted, sine both of their funtions have same number of literals. Fig. 3 depits exeution of the algorithm with the assumption that is seleted. is ompletely implemented on this iteration of the algorithm through the following sequene of transformations: ab + y 3 y' 4 + y 3 y' 4 + y' 5 y 6. (7) The final implementation of the iruit has 9 NAND2 gates and 4 inverters. V. Experimental results Ciruit Name TABLE II: Post-layout synthesis results SIS-1.2 Total area Routing Delay (mil 2 ) length (µm) (ns) M32 Total area Routing (mil 2 ) length (µm) Improvement M32 / SIS-1.2 Delay Total (ns) area Routing length Delay z4ml vda in ount ldd b ex ordi ps duke vg apex sqrt bw lip Average Improvement: We evaluated the performane of M32 by synthesizing a set of iruits seleted from the MCNC benhmarks [30] and omparing the results against SIS-1.2 [12]. The benhmarks were first minimized using ESPRESSO [4] prior to multilevel synthesis in M32 or SIS We used the delay sript in SIS-1.2 whih is based on the lustering sript proposed in [28] and is targeted towards tehnology-independent minimization of iruit delay. Both systems used the minimal gate library L = { wire, INV, NAND2}, and delay of the implementations obtained by both systems was estimated using the library delay model of SIS-1.2 and parameters from the mn.genlib library. Table I ompares the generated iruits in terms of the number of gates, levels of logi, topologial omplexity (i.e. average topologial wire length) [18] and estimated pre-layout delay. The results in this table suggest the following observations: Even though minimization of gate ount is not a primary objetive in the M32 system, it generates implementations with fewer gates in all but two ases. In some ases the redution in gate ount is almost 50%. M32-generated iruits have onsistently fewer logi levels, in several ases being almost half as deep as SIS-generated iruits. The topologial omplexity of M32-generated iruits is onsistently lower than that of SIS-generated iruits. The metri is similar to the fanout range suggested by Vaishnav and Pedram [29] for ontrolling routing omplexity during tehnology-independent logi synthesis. The topologial omplexity however, should not be interpreted as a lone judge of iruit quality. This beomes apparent from the post-layout results in Table II. The pre-layout iruit delays of M32-generated iruits are onsistently lower than those of SIS-generated iruits, the average improvement in delay being about 30%. The run times of M32 were omparable to or better than those of SIS-1.2 for all benhmarks suggesting that the use of more powerful deompositions and substitutions is omputationally feasible. To get a better indiation of synthesis quality, the netlists produed 339

5 TABLE III: Results from mapping to a riher tehnology library SIS M32 Ciruit NAND2/INV mn.genlib * NAND2/INV mn.genlib * Name Area Delay Area Delay Area Delay Area Delay z4ml vda in ount ldd b ex ordi ps duke vg apex sqrt bw lip * Tehnology mapping was done using the SIS-1.2 ommand map -s -n 1 -AFG -p from M32 and SIS-1.2 were laid out using the Epoh standard ell plae and route tools [8] from Casade Design Automation. The layouts were generated using ells in a 0.5µm CMOS proess with two layers of metal, and allowing over-ell routing. I/O pins were distributed around the perimeter of the standard ell blok. Delays were omputed using the Epoh stati timing analyzer TACTIC. These results, shown in Table II, indiate a 23% average improvement in total area, routing length and post-layout delay for M32-generated iruits. The layouts generated for a representative iruit, the ordi benhmark, are shown in Fig. 4. It is important to note that for some of the M32-generated iruits, suh as b9 and lip, smaller average topologial wire length does not imply redued wiring when ompared to SIS-1.2. We onjeture that this is due to the larger degree of reonvergent fanout in these iruits, sine gates in the M32 algorithm beome available aross the entire logi. The ordi benhmark is also used in Fig. 5 to highlight the onstrutive nature of M32 s synthesis algorithm and to illustrate its ability to dynamially adjust the implementation topology. The two variants shown in the figure were fored to diverge after the 28th iteration of the synthesis loop (1/3 of total iterations for the Figure 5 (a) solution). The gates marked with in both variants orrespond to the ommon portion of the implemented shematis. The implementation in part (a) of the figure orresponds to the results shown in Table I and Table II, and reflets the inorporation of topologial omplexity onstraints. The implementation in part (b) was generated by relaxing these onstraints after the 28th iteration. This inremental synthesis apability an prove invaluable when the generated netlists marginally fail to meet speifiations and must be fine tuned in the neighborhood of a given solution. Table III shows a final experiment designed to assess the effet of using a riher gate library on the quality of the generated iruits. Sine the only library that is urrently supported by our prototype implementation of M32 is the simple NAND2/INV library, we had to resort to a less-than-ideal work-around to generate iruits based on other libraries. Using the SIS-1.2 map ommand, the NAND2/ INV iruits produed by M32 were tehnology-mapped to the mn.genlib library. The same mapping proess was also applied to the NAND2/INV iruits generated by SIS-1.2. The olumns labeled Area and Delay reord, respetively, the ative areas and iruit delays of eah implementation as reported by the mapper. An examination of these results indiates that, overall, the iruits produed from M32 are still faster and smaller than those produed from SIS-1.2. However, the improvement is not as pronouned as it was for the NAND2/INV library. This outome is hardly surprising sine the above mapping proess is deidedly antithetial to the onstrutive synthesis philosophy of M32 and undoes many of its gains. Speifially, mapping by tree overing is ill-suited to a b) M32 Fig. 4. Cordi relative layout areas (shown to the same sale) highly optimized DAG and we onjeture that exat DAG overing may have produed better results. It must be noted, however, that DAG overing is notoriously diffiult and no published algorithms that an effetively handle large iruits have been demonstrated. We believe that a more natural approah for solving this problem is the extension of the M32 algorithm to handle arbitrary gate libraries diretly. This effort is urrently underway. VI. Conlusions and Future Work The M32 synthesis approah outlined in this paper is a promising alternative to onventional multi-stage logi synthesis algorithms. Initial results from a prototype implementation are enouraging and suggest that further exploration of this method is worthwhile. We are urrently examining a number of extensions and variants inluding: Experimentation with other strutural omplexity metris Support of arbitrary gate libraries Synthesis of partially-speified funtions Exploration of other funtional representations, suh as BDDs, to enable more powerful Boolean transformations Ultimately, we would like to integrate physial optimization (plaement and routing) with logi synthesis for better management of interonnet effets on both area and delay. Referenes a) SIS-1.2 (sript.delay) [1] P. Abouzeid, K. Sakouti, G. Sauier, and F. Poirot. Multilevel synthesis minimizing the routing fator. In Pro. 27th DAC, pp , June [2] K. Bartlett, W. Cohenand A. de Geus, and G. Hahtel. Synthesis and optimization of multilevel logi under timing 340

6 o b d m n k l i j g h w t e a p q u v r s b a d o e w ft u r f v s p q m n k l i j g h a) Synthesis with topologial onstraints: 133 gates, 11 levels b) Synthesis with relaxed strutural onstraints:116 gates,13 levels Fig. 5. Two inrementally-different implementations of the ordi iruit onstraints. IEEE Trans. CAD IC, CAD-5, [3] R. Brayton, E. Detjens, S. Krishna et al. Multiple-level optimization system. In Pro. ICCAD, Nov [4] R. K. Brayton, G. D. Hahtel, L. A. Hemahandra et al. A omparison of logi minimization strategies using ESPRESS0. In Pro. IEEE Intern Symp. Cir. Systems, pp , May [5] R. K. Brayton and C. MMullen. Synthesis and optimization of multistage logi. In Pro. ICCD, pp , f1 f2 f2 f1 [6] R. K. Brayton, C. MMullen, G. D. Hahtel, and A. Sangiovanni-Vinentelli. Logi Minimization Algorithms for VLSI Synthesis. Kluwer Aademi Publishers for VLSI Synthesis, [7] R. K. Brayton, R. Rudell, A. Sangiovanni-Vinentelli, and A. Wang. MIS: A multiple-level logi optimization system. IEEE TCAD IC, 6: , Nov [8] Casade Design Automation, Bellevue, WA EP- OCH User s Manual, ver. 3.2, [9] E. Davidson. An algorithm for NAND deomposition under network onstraints. IEEE TC, C-18(12): , De [10] E. Detjens, G. Gannot, R. Rudell, et al. Tehnology mapping in MIS. In Pro. ICCAD, pp , Nov [11] D. L. Dietmeyer. Logi design of digital Systems. Allyn and Baon, Boston, MA, [12] E. M. Sentovih et. al. SIS: A system for sequential iruit synthesis. Tehnial Report UCB/ERL M92/41, UC Berkeley, Eletronis Researh Laboratory, May [13] J. P. Fishburn. LATTIS: An iterative speedup heuristi for mapped logi. In Pro. 29th DAC, pp , June [14] D. Gregory, K. Bartlett, A. de Geus, and G. Hahtel. Sorates: A system for automatially synthesizing and optimizing ombinational logi. In Pro. 23rd DAC, pp , [15] G. Hahtel, R. M. Jaoby, K. Keutzer et al. On properties of algebrai transformations and the synthesis of multifault-irredundant iruits. IEEE TCAD IC, 11(3): , Marh [16] K. Keutzer. DAGON: tehnology binding and loal optimization by DAG mathing. In Pro. 24th DAC, pp , June [17] K. Keutzer, A. R. Newton, and N. Shenoy. The future of logi synthesis and physial design in deep-submiron proess geometries. In Pro. ISPD, pp , [18] V. N. Kravets and K. A. Sakallah. Construtive multilevel logi synthesis under properties of boolean algebra. Tehnial Report CSE-TR , Marh [19] E. Lehman, Y. Watanabe, J. Grodstein and H. Harkness. Logi deomposition during tehnology mapping. In Pro. ICCD, pp , [20] P. MGeer, R. Brayton, and A. Sangiovanni-Vinentelli. Performane enhanement through the generalized bypass transform. In Pro. ICCAD, pp , Nov [21] G. De Miheli. Synthesis and Optimization of Digital Ciruits. MGraw-Hill, In., [22] L. Benini G. De Miheli. A survey of boolean mathing tehniques for library binding. ACM TODAES, 2(3), [23] M. Pedram and N. Bhat. Layout driven tehnology mapping. In Pro. 28th DAC, pp , June [24] G. Sauier, J. Fron, and P. Abouzied. Lexiographial expressions of boolean funtions with appliations to multilevel synthesis. IEEE TCAD IC, 12: , Nov [25] P. R. Shneider and D. L. Dietmeyer. An algorithm for synthesis of multiple-output ombinational logi. IEEE TC, C- 17(2): , Feb [26] K. Sott and K. Keutzer. Improving ell libraries for synthesis. In Pro. IEEE Custom Integrated Ciruits Conf., pp , [27] K. J. Singh and A. Sangiovanni-Vinentelli. A heuristi algorithm for the fanout problem. In Pro. 27th DAC, pp , June1990. [28] H. J. Touati, H. Savoj, and R. K. Brayton. Delay optimization of ombinational logi iruits and partial ollapsing. In Pro. 28th DAC., pp , June [29] H. Vaishnav and M. Pedram. Minimizing the routing ost during logi extration. In Pro. 32nd DAC, pp , June [30] S. Yang. Logi synthesis and optimization benhmarks user guide version 3.0. MCNC, Researh Triangle Park, NC, January [31] K. Yoshikawa, H. Ihiryu, H. Tanishita et al. A depth-dereasing heuristi for ombinational logi; or how to onvert a ripple-arry adder into a arry-lookahead adder or anything in-between. In Pro. 28th DAC, pp , June