Department of Electrical and Computer Engineering University of Wisconsin Madison. Fall

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1 Department of Eletrial and Computer Engineering University of Wisonsin Madison ECE 553: Testing and Testable Design of Digital Systems Fall Assignment #2 Date Tuesday, September 25, 2014 Due date Thursday, Otober 2, 2014 SOLUTION OUTLINE 1. (10 points) Compute the total number of stuk-at (single and multiple) faults for a logi in figure 1. For the iruit of Figure 1, we have Therefore, Number of fault sites = PIs+gates+fanout branhes = 15 Number of single faults = 15 2 = 30 Number of single and multiple faults = 3 number of fault sites 1 = = The iruit has single and multiple stuk-at faults. Total number of transistors = = (15 poiints) (Bushnell and Agrawal) Problem 4.5 (a) A two-input NAND gate is shown in the above figure. The following table gives tests for transistor stuk-open (sop) faults: Test No. Fault Test: Vetor 1, Vetor 2 1 P1 sop 11, 01 2 P2 sop 11, 10 3 N1 sop 01, 11 or 10, 11 or 00, 11 4 N2 sop 01, 11 or 10, 11 or 00, 11 1 Fall 2014 (Le: Saluja)

2 V DD A P1 P2 B N1 C A B C N2 Logi NAND gate. Ground CMOS NAND gate. Ciruit for Problem 4.5. Notie that the sop faults of N1 and N2 have exatly the same tests. These two faults are equivalent. Equivalene of transistor faults is disussed in the following paper: M.-L Flottes, C. Landrault and S. Provossoudovith, Fault Modeling and Fault Equivalene in CMOS Tehnology, J. Eletroni Testing: Theory and Appliations, vol. 2, pp , August (b) The following sequene of four vetors ontains one vetor pair for eah fault in the above table: 11, 01, 11, 10 Notie that this sequene also detets all single stuk-at faults in the logi model of the NAND gate. () A stuk-at fault in a signal affets two transistors in the two-input NAND gate. For example, the fault A s-a-1 will mean that N1 remains permanently shorted (N1-ssh) and P1 remains permanently open (P1-sop). The following table gives all equivalenes: Stuk-at fault Equivalent transistor faults A s-a-1 N1-ssh and P1-sop B s-a-1 N1-ssh and P2-sop C s-a-1 (P1-ssh or P2-ssh) and (N1-sop or N2-sop) A s-a-0 N1-sop and P1-ssh B s-a-0 N2-sop and P2-ssh C s-a-0 N1-ssh, N2-ssh, P1-sop and P2-sop Notie that the three equivalent faults, A s-a-0, B s-a-0 and C s-a-0, are atually aused by different faulty transistors. They are deteted by the same test (11). 2 Fall 2014 (Le: Saluja)

3 3. (15 points) Show that the two faults a s-a-0 and s-a-1 are equivalent in the iruit of figure 2. Faulty funtions for the iruit of Figure 4.6 orresponding to the two faults after logial simplifiation are: m(a s a 0) = b+d n(a s a 0) = b d (1) m( s a 1) = b+d n( s a 1) = b d The two faulty funtions are indistinguishable and hene the two faults are equivalent. Alternatively, you need to show that the signal u = 1 for either of these two faults and these faults reonverge only at line u. 4. (30 points) For this problem you will use the iruit given in Figure 3. (a) (10 points) The Table 1 gives a fault list forthe iruit of Figure3, after strutural fault ollapsing. Fill in the blanks with equvalent fault sets for eah listed fault. (Validity hek: the total number of faults in table should be 40) (b) (10 points) Assume that you are applying exhaustive test set for the iruit in Figure 3. In the Table 2, mark all the faults that are deteted by eah vetor. Note that only the ollapsed faults are listed in Table 2. For this problem you are allowed to use fault simulator (SFSP) of TESTCAD toolset () (10 points) From the over table of (b), i. find minimum number of vetors that detet all detetable faults. At least 4 vetor is required to detet all detetable faults. ii. list a minimum test set. There are 4 essential vetors, that are 0111, 1001, 1010, 1111 to detet all detetable faults. There are however a few faults 6/1, 7/1, 15/1 and 12/0 and their equivalent faults that are undetetable. 5. (15 points) (Bushnell and Agrawal) Problem 4.11 (2) (3) 3 Fall 2014 (Le: Saluja)

4 Fault List all equivalent Faults 1/1 Ø 9/0 1/0, 5/0 9/1 Ø 5/1 Ø 2/0 Ø 2/1 Ø 10/0 6/0, 7/0 6/1 Ø 7/1 Ø 3/0 Ø 3/1 Ø 11/0 Ø 11/1 4/0, 8/0 8/1 Ø 4/1 Ø 17/1 14/0, 15/0 14/1 Ø 15/1 10/1, 12/1 12/0 Ø 18/1 16/0 19/0 13/1 19/1 13/0 20/0 Ø 20/1 16/1, 17/0, 18/0 Table 1: Table for problem 4(a) 4 Fall 2014 (Le: Saluja)

5 /1 x x x x 9/0 x x x x 9/1 x x x x x x x x x x x x 5/1 x x x x 2/0 x x x x 2/1 x x x x 10/0 x 6/1 7/1 3/0 x x x 3/1 x x x 11/0 x x x x x x x x x x x 11/1 x x x 8/1 x x x x 4/1 x x x 17/1 x 14/1 x 15/1 12/0 18/1 x x x x x x x x x 19/0 x x x x x x x x x x x x 19/1 x x x x 20/0 x x x x x x x x x x x x x 20/1 x x x Table 2: Table for problem 4(b) 5 Fall 2014 (Le: Saluja)

6 Deleted due to equivalene 18 Ciruit for Problem (a) The given iruit is shown below with fault sites marked with numbers. The number of potential fault sites is 18. (b) The figure shows deletion of equivalent faults using an output to input pass. Of the 36 faults, 20 remain, giving a ollapse ratio 20/36 = () Chekpoint lines are shown in boldfae numbers. These are three PIs and six fanout branhes. Notie that a single input gate (inverter) is treated as ontinuation of its inputline. Thus, line2isassumedtofanoutto5,12and13. Thereareninehekpoints and 18 hekpoint faults. Further, s-a-0 faults on lines 6 and 12 are equivalent and any one of them an be hosen. Similarly, s-a-0 faults on 7 and 13 are equivalent, and so are s-a-0 on 5 and s-a-1 on 8. Thus, the set of fault set is redued to 15, giving a ollapse ratio 15/36 = (15 points) (Bushnell and Agrawal) Problem Please use the definition given in the text (Definition 4.7 on page 78) for hekpoints in a iruit. Note : For those who have older version of text, the definision of hek point is slightly modified as follows. Chekpoints : Primary inputs and fanout branhes of a ombinational iruit onsisting only of BOOLEAN gates are alled the hekpoints. Thus, expend XOR gate as in Figure 4.9 in the text. (Bushnell and Agrawal) Problem Please use the orreted version of the Definition 4.7 (page 78) in the text for hekpoints in a iruit. The orreted version (also disussed in lass) an be found via the link shown for the orretions in the ourse web page. One, you see the orreted version of the definition, you will need to know the gate level realization of the Exlusive OR iruit. Use the gate level realization of the 6 Fall 2014 (Le: Saluja)

7 Exlusive OR shown in Figure 4.9 of the text. Thus, in the new iruit, with Exlusive OR replaed with its gate equivalent realization, the lines d and e will have fanouts. Label these fanout signals as d1, d2, e1,e2. The signals d1 and e2 will feed the AND gates and d2 and e1 will be inputs to the NOT gates. (a) Chekpoints are defined for the signals in a ombinational iruit. These signals are the interonnets between Boolean gates, a fat not always expliitly stated. To avoid ambiguity, the definition on page 78 of the book should read as: Definition 4.7 Chekpoints. Primary inputs and fanout branhes of a ombinational iruit onsisting only of Boolean gates are alled the hekpoints. To find hekpoints of the iruit of Figure 4.12, we must replae the exlusive-or (XOR) funtion by a primitive Boolean gate implementation. AND, OR, NAND, NOR and NOT are alled the primitive Boolean gates. Funtions suh as XOR are sometimes referred to as omplex gates. In the following figure, we have assumed one suh implementation. Our result is, therefore, based on this assumption. Other implementations of the XOR funtion are possible and an give a different set of hekpoints. a d d1 XOR b e e1 d2 e2 i k f g h There are nine hekpoints in this iruit. These inlude three primary inputs, a, b and, and six fanout branhes, d1, d2, f, e1, e2 and g. The hekpoint fault set onsists of eighteen faults s-a-0 and s-a-1 faults on the nine lines. Notie that lines d and e of the original iruit are not hekpoints. If we did not model the XOR blok with Boolean gates, then those lines will appear to be hekpoints, whose number will be fourteen. However, detetion of those faults will not guarantee detetion of faults on the fanouts that are internal to the XOR blok. Considering the Boolean gate struture, a fault on d orresponds to a simultaneous (multiple) fault on d1 and d2 and, in general, the detetion of a multiple fault is not equivalent to detetion of the omponent faults. 7 Fall 2014 (Le: Saluja)

8 (b) We evaluate the output funtion k orresponding to the two faults: k(d s a 0) = +b+a+b = +b+ab k(g s a 1) = +ab+ab+a = +ab+a The two faulty funtions are shown by Karnaugh maps below. In both ases, the funtions have exatly one false minterm, ab. Sine the two faulty funtions are idential the orresponding faults are equivalent. false minterm b false minterm b b a ab a k with d s-a-0 ab a k with g s-a-1 Note: this type of fault equivalene is funtional and is often diffiult to find by typial fault analysis tools, whih rely on struturally identifiable equivalenes. 8 Fall 2014 (Le: Saluja)