DETECTING timing-related defects has become vital for

Transcription

1 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 6, JUNE Crosstalk- and Process Variations-Aware High-Quality Tests for Small-Delay Defects Ke Peng, Member, IEEE, Mahmut Yilmaz, Member, IEEE, Krishnendu Chakrabarty, Fellow, IEEE, and Mohammad Tehranipoor, Senior Member, IEEE Abstract The population of small-delay defects (SDDs) in integrated circuits increases significantly as technology scales to 65 nm and below. Therefore, testing for SDDs is necessary to ensure the quality and reliability of high-performance integrated circuits fabricated with the latest technologies. Commercial timing-aware automatic test pattern generation (ATPG) tools have been developed for SDD detection. However, they only use static timing analysis reports in the form of standard delay format for path-length calculation and neglect important underlying causes, such as process variations, crosstalk, and power-supply noise, which can also induce small delays into the circuit and impact the timing of targeted paths. In this paper, we present an efficient pattern evaluation and selection procedure for screening SDDs that are caused by physical defects and by delays added to paths by process variations and crosstalk. In this procedure, the best patterns for SDDs are selected from a large repository test set. Experimental results demonstrate that our method sensitizes more LPs, detects more SDDs with a much smaller pattern count, and needs less CPU runtime compared with a commercial timingaware ATPG tool. Index Terms Crosstalk, delay test, pattern selection, process variations, small-delay defects (SDDs). I. INTRODUCTION DETECTING timing-related defects has become vital for ensuring product quality in the very deep-submicrometer regime. Such defects are introduced by imperfect manufacturing processes that lead to resistive opens, resistive shorts, and process variations, as well as some nonphysical effects, such as crosstalk and power supply noise, which cause chip failures by introducing extra delay to the design. Small-delay defect (SDD) is one type of such timing defects. SDDs were not a major concern at higher technology nodes because of Manuscript received June 30, 2011; revised February 8, 2012; accepted May 18, Date of publication August 7, 2012; date of current version May 20, The work of K. Peng and M. Tehranipoor was supported in part by SRC under Contract 1587 and by the National Science Foundation (NSF) under Grant ECCS and Grant ECF The work of M. Yilmaz and K. Chakrabarty was supported in part by the SRC under Contract 1588 and by the NSF under Grant ECCS K. Peng is with Freescale Semiconductor, Austin, TX USA ( ke.peng@freescale.com). M. Yilmaz is with NVIDIA, Santa Clara, CA USA ( mahmut.yilmaz@gmail.com). K. Chakrabarty is with the Department of Electrical and Computer Engineering, Duke University, Durham, NC USA ( krish@ee.duke.edu). M. Tehranipoor is with the Department of Electrical and Computer Engineering, University of Connecticut, Storrs, CT USA ( tehrani@engr.uconn.edu). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TVLSI /$ IEEE their small size relative to the timing margins allowed by the maximum operating frequency of a design. Although the delay introduced by each SDD is small, the overall impact can be significant if the sensitized path is a long/critical path, especially when the technology scales to 65 nm and below [1] [3]. Furthermore, it is very difficult or impossible to avoid SDDs at the design stage, even with accurate models. Therefore, SDDs require serious consideration as we strive to increase test quality and reduce test escape (i.e., increase infield reliability), denoted by defective parts per million. Transition-delay fault (TDF) and path-delay fault are two prevalent fault models widely used in industry. The TDF model assumes that there is a slow-to-rise or slow-to-fall fault at each gate output in the design [4], [5]. A delay fault at a gate output, when it is sufficiently large (gross-delay defect), can cause a logic failure when the signal is propagated through the fault site to the test observation points. The pathdelay fault model assumes a cumulative delay through all the gates and interconnects on a pre-defined path. The pathdelay fault is superior to TDF in modeling capacity since it addresses distributed defects that affect the entire path. The major drawback of the path-delay fault model is that it requires a large test pattern set, and it may also be impossible to excite all the paths in the design due to the fact that the number of paths in the design increases exponentially with the circuit size. Thus, path-delay fault models are only used for selected long/critical paths in the design [6]. In practice, most timing defects are targeted by the TDF model, which has been shown to be effective in improving overall test quality. However, traditional TDF automatic test pattern generation (ATPG) tools are not useful for detecting SDDs since they tend to detect faults via short paths (SPs). Note that a SDD only introduces a small extra delay to the fault site, and it may only fail the design when sensitized via the long or critical paths. Thus, it is necessary to detect SDDs via long paths (LPs). Methods, such as n-detect ATPG are capable of sensitizing LPs, i.e., detecting SDDs, since they detect faults via different paths [7], therefore, if there is a sensitizable long path running through the target fault site, the ATPG tool may sensitize it for fault detection. Therefore, with a large value of n for n-detect ATPG, we will have a good chance to detect faults via their possible LPs. However, the significantly large pattern count for large n limits the usage of n-detect ATPG in real applications. Commercial timing-aware ATPG tools, e.g., latest versions of Synopsys TetraMAX [8] and Mentor Graphics FastScan [9], have been developed to deal with the deficiencies

2 1130 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 6, JUNE 2013 of traditional timing-unaware ATPGs in detecting SDDs. However, timing-aware ATPGs do not take into account important underlying causes, such as process variations, crosstalk, and power-supply noise [10], [11]. Furthermore, these tools result in a significantly larger pattern count and CPU runtime compared to 1-detect timing-unaware TDF ATPG [10]. In conclusion, there are no available tools that can simultaneously satisfy the requirements of high SDD detection quality and low pattern count. The complexity of today s ICs and shrinking process technologies have made design features more probabilistic [12]. Thus, it is necessary to perform statistical timing analysis when evaluating the path length considering process variations. Statistical static timing analysis (SSTA) methods were proposed, and SSTA tools were developed to deal with these issues [12] [14]. However, these methods are patternindependent, i.e., they estimate path length using the delay of components on the path without considering the patterndependent parameters. Note that power supply noise and crosstalk are pattern-dependent effects and they can significantly impact the delay of the components on a path. In this paper, we propose the use of pattern-dependent statistical timing analysis considering process variations and crosstalk for path-delay evaluation. The impact of power supply noise will be added to the proposed flow in future work. A. Related Prior Work Several techniques have been presented in the past few years for screening SDDs and increasing test quality. The as late as possible transition fault (ALAPTF) model was proposed to launch one or more transition faults as late as possible to detect the faults through the least slack path [16], this approach requires high CPU runtime compared to traditional ATPGs. In [17], the authors proposed a delay fault coverage metric to sensitize the longest paths affecting a TDF fault site. It is based on robust path-delay test and attempts to find the longest sensitizable paths passing through the target fault site and generating a slow-to-rise or slow-to-fall transition. However, this may become impossible due to further scaling of technology and increasing functionality since the number of paths in the design increases exponentially with the circuit size. The authors in [2] proposed a hybrid method using one-detect and timing-aware ATPGs to detect SDDs based on SDF with a reduced pattern count. This method counts the inefficient patterns generated by timing-aware ATPG and, therefore, cannot produce a minimized pattern set. In [3], a static-timing-analysis (STA)-based method was proposed to generate and select patterns that sensitize LP. It finds LP, intermediate paths (IPs), and SP to each observation point using static-timing analysis tools. Then IP and SP observation points are masked in the pattern generation procedure to force the ATPG tool to generate patterns for LPs. Next, a pattern selection procedure is applied to ensure the pattern quality. The authors in [18] proposed a procedure to estimate the maximum path delay with coupling noise considering both logic and timing constrains in delay testing. However, not all the patterns can reach this worst-case scenario in real applications. In [19], the authors presented ATPG techniques to traverse the longest testable path passing through a gate or wire based on a graph traversal algorithm. However, its computation complexity may prohibit this method to be applied to large industry circuits. Several SSTA algorithms have been proposed, which can be classified to be path-based or block-based. In [20], the authors provided a simple method to perform statistical timing analysis using a path-based scheme. This procedure is based on a deterministic STA to identify critical paths. A parameterized blockbased SSTA method is proposed in [21]. It assumes Gaussian distribution parameters for efficient statistical analysis. In [22], a statistical quality model reflecting fabrication process quality, design delay margin, and test timing accuracy was proposed for delay testing, based on which effective test vectors were generated. A statistical fault coverage metric combining local and global delay faults was proposed in [23], which can only be used to evaluate the coverage of an existing test set. A false-path-aware statistical timing analysis framework was proposed in [24]. It selects all logically sensitizable LPs using worst-case statistical timing information, and obtains the true timing information of the selected paths. The authors in [25] proposed path-based and cone-based metrics for estimating path delay under test. This method is not accurate due to its dependence on gate delay models; unit gate delay and differential gate delay models, which were determined by the gate type, number of fanins and fanouts, and the transition type at the output. In [26], the authors proposed a dynamic pattern compaction method for path-delay patterns. The 2K longest paths, K paths having the rising transition and K paths having the falling transition, through each fault site was reported for path delay pattern generation. However, with the increase in circuit size, it becomes infeasible to generate 2K longest paths for each fault. Furthermore, to meet the robust test generation condition, it is infeasible to generate patterns for all the LPs in the design. The authors in [27] proposed a statistical delay fault coverage model based on the propagation delay of a path and the delay defect size. They assumed independent delay distribution for each gate, and derived a Gaussian distribution for path delay according to the central limit theorem (CLT). However, the analysis of test effectiveness in this paper requires information on the delay distribution of the path under test, the delay defect size, as well as the delay distribution of the longest path passing through the fault site. Obtaining the delay defect size needs considerable analysis using circuit testability or silicon data. Since the path length is a random variable in statistical timing analysis, it is extremely difficult to find the longest path passing through the target fault site. Crosstalk effects can be reduced using redesign in circuit layout as presented in [28]. However, it may not be possible to eliminate the crosstalk effects, especially for the high-density designs fabricated with the latest technologies. The authors in [29] showed that the simultaneous switching-induced crosstalk effects can cause up to 40% stage delay error on coupled nets, and should be taken into account during test generation and validation. Furthermore, [30] shows that process variations can also aggravate crosstalk and ground bounce effects. Therefore, techniques were proposed to

3 PENG et al.: CROSSTALK- AND PROCESS VARIATIONS-AWARE HIGH-QUALITY TESTS 1131 generate test patterns considering crosstalk, e.g., [31] and [32], which mainly focused on single-aggressor scenarios. The approach proposed in [33] uses a genetic algorithm to induce crosstalk into delay test patterns. An academic ATPG method was proposed in [34] and [35] that can generate test patterns taking into account crosstalk and transition arrival time. However, this approach is computationally intensive. Moreover, prior work on crosstalk test generation did not consider process variations explicitly process variations were not deemed as serious problem as they are today at the time when crosstalk modeling and test generation were studied. In recent work [10], an output-deviation-based method was developed to detect SDDs. This method defined gate-delay defect probabilities (DDPs) to model delay variations in a design. Based on the delay defect probability matrix (DDPM) of each gate, output deviations are calculated, which are used for pattern evaluation and selection. However, the main drawback here is that in case of a design with a large number of gates on a path, the output deviation metric saturates and equal output deviations (close to 1) are obtained for both long and IPs. A similar method was developed in [11] to take into account the interconnect contribution to the total delay of sensitized paths. However, it also has the saturation problem associated with output deviations. B. Contributions and Paper Organization In this paper, we present a novel pattern evaluation and selection procedure to address the above problems. Due to the complexity of ATPG algorithms, it would be extremely difficult to develop an ATPG to take into account all the important design features, such as process variations, as well as the pattern-dependent noise effects, such as crosstalk and power supply noise. It is also difficult to ensure that all the generated patterns are high-quality SDD patterns. In this paper, we focus on developing a novel pattern selection procedure for screening SDDs. This approach is compatible with existing ATPG flows and it does not require new ATPG techniques, making the proposed approach easily adopted in practice. Our main contributions include the following. 1) We use a probability density function (PDF)-based method rather than DDPM-based method [10] for pattern evaluation; this solves the saturation problem associated with output deviations. 2) We consider process variations and crosstalk effect as sources of SDD in nanometer technology designs. The impact of these two design features is taken into account dynamically during the pattern evaluation process using PDF-based analysis. 3) The PDF propagation and crosstalk calculation procedures are validated by comparisons with SPICE simulation. 4) The proposed procedure can check the overlap between sensitized paths by various patterns; this helps in selecting the most effective patterns with a minimum pattern count. Therefore, it can detect more SDDs with a reduced test cost. The CPU runtime is also less than the commercial timing-aware ATPG tool. The n-detect pattern set is used as our original pattern repository in this paper. The remainder of this paper is organized as follows. Section II analyzes the effectiveness of SDD detection of different pattern sets. Section III presents the variation sources that induce SDDs. The pattern evaluation and selection procedure are presented in Section IV. The experimental results are presented in Section V. Finally, we conclude this paper in Section VI. II. SDD DETECTION ANALYSIS Due to imperfect manufacturing processes, SDDs can be found in many fabricated designs. Studies have demonstrated that a large portion of failures in delay-defective parts are due to SDDs, especially when technologies scale down to 65 nm and below [1]. Although, a SDDs contribution to delay increase is small, it may fail the chip if sited on a critical/long path, or it may pose a reliability risk in the field. If there are several SDDs along a critical/long path, the accumulation will be significant, and may fail the chip. Due to these concerns, it is important to take into account SDDs during manufacturing test to increase product quality and in-field reliability. The effectiveness of traditional TDF ATPGs for detecting SDDs is questioned since: 1) a timing defect can only be detected if the introduced delay is larger than the slack of the affected path; 2) traditional ATPG tools tend to detect the TDFs through; and 3) it is more efficient to detect SDDs through the LPs running through the fault sites. With the delay information obtained from STA tools, timing-aware ATPGs [8], [9] can calculate the length of all paths running through the target fault site, and therefore select the possible LPs for SDD detection. However, the timingaware ATPGs have been proven to result in a much larger pattern count compared to traditional timing-unaware TDF pattern sets, and require a significant CPU runtime, especially for large industry designs. Due to its underlying algorithms, n-detect ATPG can also be an effective method for SDD detection, even without timing information of the design. For each target fault, n-detect ATPG will generate patterns trying to detect it n times, through different paths. In this way, with the increase in n, wemay have a greater possibility to detect delay defects via the long path running through the fault site. Therefore, n-detect ATPG can result in high-quality patterns for screening SDDs. In this paper, we only count LPs based on our long path threshold definition. It is not necessarily the longest path running through the fault site. The reason behind this is that a SDD can be detected if the sensitized path is long enough, not necessarily the absolute longest path. It is also possible to have pathological circuits where a fault site has many SPs and one hard-to-sensitize long path for which the timing-aware ATPG can detect it and n-detect ATPG may not. However, in all of our experiments, this situation seldom occurs and we only compare the total number of sensitized LPs of each pattern set, rather than the single pathological case. Moreover, in all our experiments, n-detect ATPG can sensitize a comparable number of LPs or even more LPs

4 1132 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 6, JUNE 2013 (a) (b) Fig. 1. (a) Normalized CPU runtime and (b) pattern count of different pattern sets for usb_funct benchmark. than the timing-aware ATPG. Furthermore, the n-detect ATPG requires much less CPU runtime when compared with timingaware ATPG, when n is not too large (n < 20). The major drawback of n-detect ATPG, however, is the very large pattern count, limiting its usage in practice. Fig. 1 presents the normalized CPU runtime and pattern count for one-detect, n-detect (n = 3, 5, 8, 10), and timingaware TDF ATPGs for the IWLS benchmark usb_funct [36]. The CPU runtime and pattern count are normalized with respect to one-detect ATPG. It can be seen from the figure that as n increases, the CPU runtime of n-detect timing-unaware ATPG increases. Timing-aware ATPG consumes a much larger CPU runtime compared with timing-unaware ATPGs (over 80X of one-detect ATPG). The pattern count of n-detect ATPG increases almost linearly with n for this benchmark. The timing-aware ATPG results in a pattern count similar to tendetect ATPG for this benchmark. Similar results are obtained for many other benchmarks. In general, comparing with one-detect timing-unaware ATPG, timing-aware ATPG can generate high-quality SDD patterns with the penalty of a large pattern count and significant CPU runtime, and n-detect ATPG will result in highquality SDD patterns with a large pattern count and a small amount of CPU runtime increase. Our work is based on the n-detect pattern set and is striving to reduce SDD pattern count by only selecting the high-quality patterns. However, our procedure can be applied to any kind of pattern repository (e.g., random pattern set). We also run our procedure on timing-aware pattern sets to show the effectiveness of the pattern selection algorithm. III. ANALYZING VARIATION-INDUCED SDDS As mentioned earlier, SDDs can be introduced by both physical defects and variations. The physical defects include resistive opens and shorts. The variation-induced SDDs in a circuit are from process variations, crosstalk, power supply noise, etc. In this paper, our procedure targets physical SDDs, as well as SDDs introduced by process variations and crosstalk. The impact of process variations and crosstalk effects will be different at different technology nodes. For example, our analysis shows that on average the crosstalk effect can add approximately 15% delay to paths at a 90-nm technology, and only around 10% for the 180-nm Cadence Generic Standard Cell Library. However, our flow and the conclusion will not be greatly impacted by the technology nodes, since crosstalk only acts as shift to the path PDF (Section III-B for details). In this paper, our experiments are based on the public 180-nm Cadence Generic Standard Cell Library. A. Impact of Process Variations on Path Delay In reality, the parameters of fabricated transistors are not exactly the same as design specifications due to process variations. In fact, the parameters are different from die-todie, wafer-to-wafer, and lot-to-lot. These variations include impurity concentration densities, oxide thicknesses, and diffusion depths, caused by nonuniform conditions during the deposition and/or the diffusion of the impurities. They directly result in deviations in transistor parameters, such as threshold voltage, oxide thickness, W/L ratios, as well as variation in the widths of interconnect wires [37], and impact the performance (increase or decrease delays) to a large extent in the latest technologies. Due to the impact of process variations, the delay of each path segment (gate and interconnect) is assumed to be a random variable X with mean value μ and standard deviation σ, rather than a fixed value. We ran HSPICE-based Monte Carlo simulations [8] using a 180-nm Cadence Generic Standard Cell Library to obtain the delay distributions for all gates in the library. For each gate, Monte Carlo simulations were run with: 1) different input switching combinations; 2) different output load capacitances; and 3) process-variation parameters. The process-variation parameters are: 1) transistor gate length L: 3σ = 10%; 2) transistor gate width W: 3σ = 10%; 3) threshold voltage V th :3σ = 20%; 4) gate-oxide thickness t ox :3σ = 3%. The slew rate is an important parameter for measuring propagation delay on standard cells. Different slew rate of the input signal may result in different propagation delays on the cell [38]. The 180-nm cadence generic standard cell library only includes a small number of simple gates with similar driving strength. Therefore, the slew rate s impact on delay is minor. To obtain a simple model for our experiments, a fixed input slew rate was applied on all the standard cells, when driving by a mediate size cell in the library. Furthermore, this assumption will not affect the validation of our pattern selection procedure.

5 PENG et al.: CROSSTALK- AND PROCESS VARIATIONS-AWARE HIGH-QUALITY TESTS 1133 For interconnects, we use SPICE simulation [8] to obtain their delay distributions. Different variations between metal layers and vias are taken into consideration when calculating these delay distributions. We first run SPICE simulation for the delay of each metal layer with unit length and each single via according to their RC parameters from the library database. Then the metal length and vias between metal layers of each interconnect are extracted from layout, with which we can calculate the nominal delay of each interconnect. There are six available metal layers in the library. We use 3σ variations 30%, 30%, 20%, 15%, 10%, and 5% for Metals 1 6, respectively. The 3σ variations for vias in Metal layers 1 5 are 50% [39]. In this way, we obtain the nominal delay and 3σ variation for each interconnect in the design. In this paper, the delay distribution of metal layers and vias are assumed to be independent from each other. It is obvious that the mean and variance of the delay of each interconnect segment are bounded. Since this assumption will only slightly impact the variance of the path delay, it will have a minor impact on the calculated path weight results, introduced in Section IV-A. Since the mean and variance of the delay of each interconnect segment are bounded, the Lindeberg s Condition is satisfied and the CLT holds (the detailed proof is given in Appendix) [40]. Assume that the delay for Metal layers 1 6 with unit length L are μ M1, μ M2, μ M3, μ M4, μ M5,andμ M6, respectively, and the delay for single vias in Metal layers 1 5 are μ V 1, μ V 2, μ V 3, μ V 4,andμ V 5, respectively. If an interconnect contains Metal 1 (length l 1 ) and 2 (length l 2 ), and a single via 1 connecting the two layers, the mean μ i and 3σ deviation 3σ i of its delay distribution can be calculated using (1) and (2), respectively μ i = μ M1 L l 1 + μ V 1 + μ M2 L l 2 (1) ( 3σ i = 0.3 μ ) M1 2 ( L l 1 + (0.5μV 1 ) μ ) M2 2. L l 2 (2) Note that the delay of each interconnect segment (metal segment or via) can be of any kind of distribution. As the number of segments increases, the delay distribution of the interconnect approaches to a normal distribution. We also assume that delay variations on path segments (gates or interconnects) are independent from each other. Similar to the interconnect distribution calculation, the path delay distribution can be calculated using (3) and (4), respectively μ p = N μ si (3) i=1 σ p = N σsi 2 (4) where μ p and σ p are the mean and standard deviation for the target path, respectively. μ si and σ si are the mean delay and standard deviation for segment i, respectively. We evaluate and validate the calculation accuracy in Section V-A. i=1 Fig. 2. Impact of aggressor arrival time on victim propagation delay when victim and aggressor nets have (a) same transition direction and (b) opposite transition direction. Coupling capacitance: 0.1pF. d coupling_arrival (ps) load capacitance=0.20 load capacitance=0.15 load capacitance=0.10 load capacitance= Coupling capacitance C a v (pf) Fig. 3. Impact of coupling capacitance on victim propagation delay with same arrival times, opposite transition direction, and different load capacitances. Load capacitance unit is pf. B. Impact of Crosstalk on Path Delay There are millions of interconnect segments running in parallel in a design, with parasitic coupling capacitances between them, introducing crosstalk effects and impacting the circuit delay characteristics and performance. The crosstalk effects introduced by parasitic coupling capacitance between a target net (victim) and its neighboring nets (aggressors) may either speed up or slow down the delays on both victim and aggressor nets, according to the transition direction, transition arrival time, as well as coupling capacitance between the victim and aggressor nets [41]. To take crosstalk effects into account during path length analysis and pattern selection, we perform various analysis to obtain a realistic model of crosstalk. Since transitions on aggressors and victim have different direction and arrival time, we perform a set of SPICE simulations and analyze their impact on each other. Fig. 2 demonstrates the simulation results on crosstalk effects between two neighboring interconnects (one victim and one aggressor) with a fixed coupling capacitance. The times t1, t2, and t3 in the figure represent the break-points of the curve-fitting. The parameter t a v denotes the arrival time difference between transitions on aggressor and victim nets, and d arrival represents the victim net delay considering the impact of arrival time difference. It is seen that when the aggressor and victim nets have the same transition direction [see Fig. 2(a)], the victim net will be sped up. Otherwise, the victim net will be slowed down [see Fig. 2(b)]. Furthermore, the crosstalk effect on the victim net is maximized when the transition arrival time of aggressor and victim nets are almost the same (t a v 0).

6 1134 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 6, JUNE 2013 We perform another set of simulations and analysis to take into account the impact of coupling capacitance size given a fixed arrival time between transitions on aggressor and victim nets. The simulations were done considering one aggressor for the victim net. In Fig. 3, it is shown that for different load capacitances, the propagation delay of the victim net increases linearly with the coupling capacitance. d coupling_arrival denotes the victim net delay considering the impact of coupling capacitance size, and C a v is the coupling capacitance between the aggressor and victim nets. For the same transition direction case, the crosstalk delay decreases linearly. Least squares technique can be used for fitting data to a curve [42]. Instead of solving the equations exactly, the least squares technique tries to minimize the sum of the squares of the residuals. Similar to [14], we apply the least squares curve-fitting to the simulation results shown in Fig. 2, and approximate a piecewise function relationship between the interconnect delay and the aggressor-victim arrival time difference as shown in (5) d orig, 0 t a v < t 1 a 0 t a v + a 1, t 1 t a v < t 2 d arrival = (5) b 0 t a v + b 1, t 2 t a v < t 3 d orig, t 3 t a v where d orig is the original interconnect delay without considering crosstalk effects. t a v is the arrival time difference between aggressor and victim nets. a 0 and b 0 are the curve slopes between timing windows [t 1, t 2 ] and [t 2, t 3 ] (see Fig. 2), respectively. a 1 is the arrival time delay of the victim net with the conditions t a v = 0andt 2 > 0. Similarly, b 1 is the arrival time delay when t a v = 0andt 2 < 0. After considering the impact of the transition direction and arrival time, we take the impact of coupling capacitance into account, approximated in (6), which is also obtained from least squares curve fitting d coupling_arrival = a d arrival C a v (6) where d coupling_arrival is the propagation delay considering the impact of the transition direction, arrival time, and coupling capacitance between the aggressor net and the target victim net. The factor a is negative for the same transition direction and positive for the opposite transition direction case. Furthermore, these parameters are highly dependent on technology nodes. For different technologies, these parameters are different. For a target victim net, the aggressors as well as the coupling capacitances between the victim net and these aggressors are extracted using Synopsys PrimeTime SI [8]. After aggressor extraction, a coupling capacitance threshold can be set to minimize the number of aggressors. Only aggressors with coupling capacitance larger than this threshold are considered as effective aggressors. Then, we developed a first come first impact (FCFI) procedure for the calculation of multipleaggressor cases. In the FCFI procedure, we list all the sensitized aggressors of the target victim net for each test pattern, and sort them according to their arrival time. Then we apply the impact of the first-coming aggressor using (5) and (6) and update the arrival time of the victim net. The secondcoming aggressor is applied next. This procedure iterates until the impact of all the sensitized aggressors are applied. For simplicity, we assume that there is no crosstalk effects between the aggressors. The validation of our crosstalk calculation procedure is presented in Section V-B. In this paper, we assume that for each victim net, crosstalk effects will only impact its mean delay value, rather than its standard deviation. In this way, only the mean delay value of the victim net will be updated when measuring the path delay. The similar procedure can be followed for the other sources of delay, such as power supply noise. IV. PATTERN EVALUATION AND SELECTION Since it is desirable to detect SDDs via LPs running through the fault sites, a technique is needed to target SDDs via LPs and gross delay defects via paths of any length. An SDD is defined as a TDF on a long path. Therefore, a TDF pattern would be considered more efficient in detecting SDDs when it sensitizes a large number of LPs. Thus, we need to identify all the paths sensitized by each pattern for pattern evaluation and selection. We developed an in-house tool to list all the sensitized paths of a TDF pattern. Based on the TDF fault list of each TDF pattern, the tool will search the topology of the design, and report the path as sensitized if all the segments of the path are sensitized. Note that without timing information during the sensitized paths identification, the tool may report some nonrobust paths as the sensitized paths of the target pattern. With the sensitized-path report, we can evaluate and weight the sensitized paths delay, and ensure that if a TDF pattern sensitizes a large number of LPs in the design, it would be considered an effective pattern and will have a large weight. Whether a path is long or short is determined by comparing its length to the functional clock period. The path length is calculated in the presence of process variations and crosstalk. A. Path PDF Analysis In general, when the length of a path is close to the clock period, which means it has a small slack, we consider it as a long path. Otherwise, when the path length is short compared with clock period, we consider it as a short path with large slack. Thus, it is necessary to define a threshold [named long path threshold (LP thr ) in this paper] according to the clock period T to differentiate the paths to be long or short. However, in the presence of process variations, our path length is a random variable with mean μ si and standard deviation σ si, rather than a fixed value. We evaluate a path by the probability that it is longer than LP thr obtained from the clock period T. Fig. 4 shows an example of path weight definition. As mentioned in Section III, the PDF of a sensitized path is calculated by (3) and (4) considering process variations, and is updated with crosstalk effects. The LP thr can be defined according to the application requirements. For instance, if LP thr = 0, every sensitized path will have a weight 1 and contribute equally to the pattern evaluation, while if LP thr is very close to the clock period T, only critical

7 PENG et al.: CROSSTALK- AND PROCESS VARIATIONS-AWARE HIGH-QUALITY TESTS 1135 Fig. 4. Fig. 5. Path PDF and path weight definition. Example of path and pattern evaluation. paths have the nonzero weights and are used for the pattern evaluation. After path weight calculation, the SPs with 0 or close-to-0 weight will be removed. In this way, only the LPs or IPs (close to LPs) will be considered in the following pattern selection procedure. The reason for keeping IPs in the calculation is that they could present as LPs with the impact of some other factors, such as power supply noise. Also for this reason, a pattern would be considered as high-quality if it sensitizes a large number of IPs. In this paper, the weight of pattern i (W patterni ) is calculated using (7), where M i is the total number of sensitized long or IPs by pattern i. This definition ensures that a pattern with large weight can sensitize more LPs or a lot more IPs, and therefore is effective for the SDD detection. In our work, we consider a path long if the mean value of its delay distribution is larger than the LP thr, which means that the path weight is larger than 0.5 M i W patterni = W pathi. (7) Fig. 5 shows an example of path weight and pattern weight calculation. In this example, assume that pattern i sensitizes four different paths. The PDF of each path is shown in Fig. 5 as PDF1, PDF2, PDF3, and PDF4, respectively. Assume that LP thr is 0.7T. We calculate the weight of these four paths, as W path1 = 1, W path2 = 0.65, W path3 = 0.3, and W path4 = 0. Then the weight of this pattern can be calculated using (7) i=1 W patterni = = (8) B. Pattern Selection From our analysis and calculation of pattern/path weights in the previous section, we conclude that if a pattern has large weight, it is more effective in sensitizing long or intermediate paths and detecting SDDs. Therefore, we select the patterns with largest weights. However, some of the paths may be sensitized by multiple patterns. In our procedure, if a long path has already been detected by the selected patterns, it will not be considered during evaluation of the remaining patterns. The detected IPs will not be excluded since they could be sensitized as LPs by some other remaining patterns. In our pattern selection procedure, the pattern with the largest weight will be the first to be selected. After selecting the pattern, we re-evaluate all the remaining patterns by excluding LPs that have been sensitized by the selected pattern. Then, the pattern with largest weight in the remaining pattern set is selected. This procedure is repeated until some termination criteria are met, for instance, when the pattern weight is smaller than a specific threshold. This pattern selection procedure will ensure that the best patterns can be selected from the initial pattern repository. It can also ensure that there is as little overlap as possible between patterns in terms of sensitized paths. Therefore, it can reduce the pattern count. The pattern-sorting algorithm is shown in Fig. 1. In this algorithm, each pattern is evaluated by LPs that are not sensitized by the previously selected patterns. This algorithm will return a pattern list with decreasing order according to the test efficiency of patterns with which we can select the best patterns in the initial pattern repository. Assume that N patterns are used by the above algorithm. Also assume that a maximum of M paths are sensitized by a pattern, and a maximum of K segments exist on a sensitized path in the target circuit. The worst-case time complexity of the pattern sorting algorithm is O(N 2 MK) where N >> M and N >> K for large designs. In fact, this is the worstcase scenario which may never be met in real applications, since several new techniques are added to the procedure to speed it up: 1) the inefficient patterns are removed before performing pattern selection; 2) once a pattern is selected, all its sensitized LPs will be removed from the long path lists of the remaining patterns. This will reduce the LPs list of each pattern significantly after several patterns are selected; 3) after re-evaluation, the new inefficient patterns in the remaining pattern set will be removed since they will never be selected; and 4) the pattern selection will be terminated if the largest weight in the remaining patterns is smaller than the pattern weight threshold, which is used to terminate the pattern selection iteration. The CPU runtime can also be tradeoff by the pattern selection efficiency. For instance, assuming that we have test patterns, we can divide these patterns into 1000 groups according to pattern ID; each group includes ten patterns. The pattern groups can also be evaluated by their sensitized paths. After evaluating the pattern groups, we can run our pattern evaluation and selection procedure on them. In this way, we can reduce the time complexity by 100X. Furthermore, we can also bypass the procedure used for checking the sensitized path overlap, so that the time complexity of this algorithm would be O(NMK). This will significantly reduce the CPU runtime. In this case, some faults may be detected multiple times and therefore, the test quality of the selected pattern set may also increase. However, the penalty is that the pattern count will also increase.

8 1136 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 6, JUNE 2013 Algorithm 1 Pattern Sorting Algorithm TABLE I DETAILS OF EXPERIMENTAL BENCHMARKS Benchmark No. of gates No. of No. of total FFs standard cells ethernet wb_conmax tv ac97_ctrl mem_ctrl systemcaes wb_dma s s of logic gates is shown in Column 2, and the number of flipflops is shown in Column 3. The total number of standard cells is presented in Column 4. Note that the data in Table I are obtained from synthesized circuits, and they may be slightly different after placement and routing, since the physical design tool may add some buffers for routing optimization. Fig. 6. Flow diagram of the pattern generation, evaluation, and selection. V. EXPERIMENTAL RESULTS The complete flow of our proposed method is shown in Fig. 6. In our experiments, synopsys design compiler [8] was used for circuit synthesis, and Astro [8] was used to perform the placement and routing of standard cells. After physical synthesis of the design, n-detect ATPG with TetraMAX [8] is run to generate source patterns (n-detect patterns in Fig. 6) for our pattern evaluation and selection procedure. All patterns are generated using launch-of-capture method. Although the flow is run on n-detect pattern set, it can be run on any kind of pattern repository, e.g., random pattern set. PrimeTime SI [8] is used for crosstalk analysis. Monte Carlo simulation is run to obtain the PDFs of the standard cells, with consideration of the different input combinations, and different output load capacitances. After pattern selection, top-off ATPG, which is one-detect timing-unaware ATPG, is run to meet the fault coverage requirement for TDF fault model. As a result, the final pattern set of our procedure is the selected pattern set plus the top-off ATPG pattern set. The programs for performing crosstalk calculation, pattern evaluation, and selection were implemented using C/C++. The validation for process variations and crosstalk calculation procedures is implemented with Perl. We performed our experiments on Linux 86 servers with eight processors and 24 GB of available memory. Seven IWLS benchmarks [36] and two ISCAS benchmarks [45] were used in our experiments. The details of these benchmarks are shown in Table I. The number A. Validation of Process Variations Calculation As mentioned in Section III-A, we use (3) and (4) to calculate the mean and standard deviation of the path length. In this section, we will perform experiments to validate the equations for process variations calculation, by comparing them with full-circuit Monte Carlo simulation results. We randomly generate some sample paths (with 6 10 gates along each path) and run Monte Carlo simulation on them to obtain the mean value and standard deviation of each path, which are used as references for the experiments. Then, we run our calculation procedure and calculate the mean value and standard deviation of each target path to compare with the references. The results are shown in Table II. Columns 2 4 are the calculated mean value, the mean value obtained using simulation for each path, and the difference between them, respectively. Columns 5 7 are the standard deviations obtained using (4) and simulation of each path, and the difference between them, respectively. It can be seen from the table that the calculated mean values are very close to the simulation results, while the standard deviation difference is a slightly larger. Also, for all the paths involved in our experiments, the difference between the calculated and simulated standard deviation is under 4%. The reason behind this variation is that the delay distribution of each path segment is approximately a Gaussian distribution. B. Validation of Crosstalk Calculation In this section, we will first present the necessity of performing crosstalk analysis, and then validate our crosstalk calculation procedure by comparing with SPICE simulation. In order to show the impact of crosstalk effects, we set up a circuit with one victim net and ten aggressor nets. With different aggressor sensitization, the delay of the victim is shown in Table III. In this table, we run SPICE simulation and measure the victim delays on five cases. Case 0 (Column 2) presents

9 PENG et al.: CROSSTALK- AND PROCESS VARIATIONS-AWARE HIGH-QUALITY TESTS 1137 TABLE II COMPARISON BETWEEN THE CALCULATED PATH DELAY DISTRIBUTION USING (3) AND (4) AND SIMULATED PATH DELAY DISTRIBUTION SPICE SIMULATIONS WERE RUN FOR EACH PATH Path Mean μ (ps) Standard Deviation σ (ps) ID Cal. Sim. μ% Cal. Sim. σ % TABLE III DELAY COMPARISON BETWEEN DIFFERENT CROSSTALK AND AGGRESSOR TRANSITION SCENARIOS Case Case 0 Case 1 Case 2 Case 3 Case 4 Delay (ps) Var. (%) the victim delay without crosstalk effect (all the aggressors are static). Case 1 (Column 3) is an extreme case that all the aggressors have the same transition direction and arrival time with the victim net (speed-up), while Case 4 (Column 6) is another extreme case (slow-down) that all the aggressors have opposite transition direction but same arrival time as the victim net. Cases 2 and 3 are two random cases with the transition direction and arrival time randomly selected. The absolute delays are shown in Row 2, and the delay variations compared with no-crosstalk-impact case (Case 0) are presented in Row 3. It can be seen from Table III that with the extreme crosstalkimpact cases, the delay on the victim can be either speeded by over 40% (Case 4) or slowed down by over 30% (Case 1) compared with Case 0. The delay of Case 4 (extreme slowdown) is over 2X larger than Case 1 (extreme speed-up). For the cases with random transition direction and arrival time on the aggressors (Cases 2 and 3), it is easy to have a delay variation around 10%. Note that this is just a sample circuit with only ten aggressors. However, for the design where a victim has more aggressors, the situation may be even worse. Therefore, it is clear that we have to take crosstalk effects into consideration in order to evaluate the path length accurately. To obtain a relatively simple model, only lump load capacitance is considered for crosstalk analysis. The resistance on interconnect is ignored. We developed a tool, which can automatically generate circuits with: 1) one victim net; 2) random number of aggressors, in the range of 2 to 10; 3) random load capacitance on the victim and aggressor nets, in the range of 0 to 0.1 pf; 4) independent random coupling capacitance between the victim and aggressor nets, in the range of 0 to 0.01 pf; 5) independent random arrival time difference between the victim and aggressor nets, in the range of 5000 ps to 5000 ps; 6) independent random transition directions on the aggressors. We then run SPICE simulation on the circuit and measure the delay on the victim. Next, we run our curve-fitting-based crosstalk calculation procedure to calculate the victim delay on the same circuit so that we can compare our calculation results with SPICE simulation results. The results obtained from simulation (shown as SimDelay) and curve-fitting (shown as CalDelay) are presented in Fig. 7. We randomly generate 100 cases and do the comparison for each case. In Fig. 7, the x-axis represents the case ID, and the y-axis represents the absolute delays on the victim. It can be seen from the figure that our curve-fitting-based crosstalk calculation procedure slightly overestimated the crosstalk effects (i.e., delay). For the 100 random cases, the minimum, maximum, and average percentage errors of our calculation are 3.97%, 35.19%, and 15.15%, respectively. Even though the absolute values are different, our crosstalk calculation procedure correlates very well with the SPICE simulation results. In fact, the two data sets (simulation data and calculated data) have a correlation coefficient of The correlation coefficient is calculated with (9) ρ X,Y = E((X μ X )(Y μ Y ) (9) σ X σ Y where ρ X,Y is the calculated correlation coefficient, and X and Y are the two random variables used for correlation calculation, respectively. μ X and μ Y, σ X,andσ Y are mean values and standard deviations of X and Y, respectively [40]. C. Pattern Selection Efficiency Analysis According to our pattern weight definition in Section IV, a pattern with large weight can sensitize more LPs, i.e., is more effective in detecting SDDs. Since the pattern weight is an abstract measure, we analyze and compare different pattern sets by counting their sensitized LPs or detected SDDs in the following sections. In this section, we present experimental results for validating the efficiency of the pattern selection procedure. The validation is done by calculating the total number of sensitized unique LPs for the selected patterns. In our experiments, we set the long path threshold LP thr = 0.7T (T is clock period). We consider a path to be long if its weight is larger than 0.5, i.e., its mean value is larger than the long path threshold. Fig. 8 presents the relation between the number of selected patterns and sensitized unique LPs by the selected pattern set on IWLS benchmark tv80. In this experiment, ten-detect pattern set is used as the initial pattern repository, which has patterns, and sensitizes 1718 LPs, with long path threshold LP thr = 0.7T. From the experimental results in Fig. 8, we can see that only 520 (4.7% of the total pattern count ) patterns are needed to detect all the LPs sensitized by the ten-detect pattern set, or 316 (2.8% of the total pattern count ) patterns are needed to detect 1547 (or 90.0% of) LPs sensitized by the ten-detect pattern set. Note that these percentages are design-dependent; for different designs, the percentage of selected patterns would be different. Table IV presents the pattern percentages of all the benchmarks. Columns 2 and 3 are number and percentage of the selected patterns for 90% LPs sensitization, respectively.

10 1138 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 6, JUNE SimDelay CalDelay TABLE IV NUMBER AND PERCENTAGE OF SELECTED PATTERNS FOR LP SENSITIZATION Absolute delay value (ps) Case ID Fig. 7. Delay comparison between SPICE simulation and the crosstalk calculation procedure. Fig. 8. # of sensitized long paths X: 316 Y: 1547 X: 520 Y: # of selected patterns LP sensitization by the selected patterns for tv80. Columns 4 and 5 are number and percentage of the selected patterns for 100% LPs sensitization, respectively. All the pattern selections in this table are based on ten-detect pattern set. The total pattern count of these benchmarks can be found later in Table VII. From these results, we can see that for most of the benchmarks only a small portion of patterns are selected for the long path sensitization, except for wb_conmax and systemcaes. The reasons behind the selection of many patterns for these two benchmarks are that: 1) there are many intermediate paths in these designs; 2) although these IPs are not recognized as LPs according to our definition, they do have weight and contribute to pattern weight; and 3) our pattern selection procedure is based on the pattern weight. Therefore, the selected patterns would be effective in detecting SDDs (TDF faults with slack smaller than 0.3 according to the definition in this experiment), as well as TDFs with slack larger but close to 0.3. If we define the pattern weight to be the number of sensitized LPs, the selected patterns for this benchmark would be significantly reduced. For the benchmark s13207, only less than 1% patterns can sensitize all the LPs sensitized Benchmark 90% LP Sensitization 100% LP Sensitization 10-detect #Pat. %Pat. #Pat. %Pat. ethernet % % wb_conmax % % tv % % ac97_ctrl % % mem_ctrl % % systemcaes % % wb_dma % % s % % s % % TABLE V NUMBER OF SENSITIZED LPSFORDIFFERENT PATTERN SETS Benchmark 1-detect 10-detect t.aware sel. tff. sel + tff ethernet wb_conmax tv ac97_ctrl mem_ctrl systemcaes wb_dma s s by ten-detect pattern set. This is because there are fewer LPs and IPs in the design, and most of the paths are short. D. Pattern Set Comparison In our pattern selection procedure, a pattern weight threshold is set as the termination criterion. For example, the pattern weight threshold used in our procedure is W pattern_thr = 1, i.e., only the patterns with weight larger than 1 can be selected. Changing this threshold can impact the total number of selected patterns. Tables V and VI show the results for the number of sensitized unique LPs and detected unique SDDs. In general, n-detect and timing-aware pattern sets are expected to perform better in sensitizing unique LPs and detecting unique SDDs compared to the one-detect timing-unaware ATPG. This is indicated by the results shown in Columns 2 4 in both tables. In Table V, Column 5 presents the number of sensitized unique LPs of our selected pattern set. Column 6 presents the number of unique LPs sensitized by top-off ATPG pattern set, not sensitized by the selected pattern set. Top-off patterns are generated using a one-detect timing-unaware ATPG. Column 7 presents the total number of sensitized unique LPs for our final pattern set, i.e., the selected patterns plus top-off ATPG patterns. From the results in Table V, we can see that timingaware ATPG and ten-detect ATPG pattern sets always detect significantly higher number of LPs than one-detect pattern set except for s13207 benchmark. On the other hand, timing-

11 PENG et al.: CROSSTALK- AND PROCESS VARIATIONS-AWARE HIGH-QUALITY TESTS 1139 TABLE VI NUMBER OF DETECTED SDDSFORDIFFERENT PATTERN SETS Benchmark 1-detect 10-detect t.aware sel. tff sel + tff ethernet wb_conmax tv ac97_ctrl mem_ctrl systemcaes wb_dma s s aware ATPG is not as effective as ten-detect ATPG in long path sensitization for these circuits. However, our pattern set is more efficient than ten-detect ATPG pattern set in terms of LPs sensitization, except for s9234 benchmark, for which the number of sensitized LPs are very close. Note that for all benchmarks, our final pattern set provides the same TDF fault coverage as timing-aware ATPG. Fig. 9 presents the sensitized long path overlap between different pattern sets. It can be seen that 98.7% (( )/10882) of the LPs sensitized by one-detect pattern set can also be sensitized by either our pattern set (i.e., sel+tff ) or the timing-aware pattern set. Our final pattern set sensitizes 1309 unique LPs not sensitized by the other two test sets, and timing-aware sensitizes 688 unique LPs. Note that our pattern selection flow allows to put all these patterns together as the original pattern repository to maximize the SDD detection of the final pattern set. Table VI presents the number of SDDs for different pattern sets. Since SDDs are TDFs on the LPs, if a pattern detects many LPs, then it can also detect many SDDs. Table VII presents the number of patterns for one-detect, ten-detect, timing-aware ATPG, and our pattern set. These patterns are used for obtaining the number of sensitized LPs and detected SDDs as shown in Tables V and VI. From these results, we can see that timing-aware ATPG results in large pattern count compared to one-detect pattern set for large IWLS benchmarks. For some cases, e.g., wb_conmax, tv80, and wb_dma benchmarks, their pattern counts are even larger than the corresponding ten-detect pattern sets. For all cases, our pattern set would result in a significantly smaller number of patterns compared to ten-detect and timing-aware pattern sets. In short, our pattern set can detect a large number of LPs with pattern count close to one-detect pattern set. E. LP Threshold Analysis LP threshold, LP thr, is an important parameter for our procedure. If the long path threshold changes, the path weight calculation threshold will change accordingly. Although it will not impact the effectiveness of our selected patterns, it may impact the number of selected patterns and number of Fig. 9. Sensitized long path comparison between pattern sets for ethernet. TABLE VII COMPARISON BETWEEN THE NUMBER OF PATTERNS Benchmark 1-detect 10-detect t.aware sel. tff sel + tff ethernet wb_conmax , tv ac97_ctrl mem_ctrl systemcaes wb_dma s s TABLE VIII LP THRESHOLD S IMPACT ON PATTERN SELECTION FOR tv80 LP thr No. of sel No. of top-off Total No. No. of No. of patterns patterns patterns LPs SDDs 0.7T T detected LPs and SDDs. If the long path threshold increases, the number of selected patterns decreases and the number of top-off ATPG patterns increases to meet the fault coverage requirement. On the other hand, if we reduce the long path threshold, the number of selected patterns increases and topoff ATPG pattern count decreases. The number of sensitized LPs and SDDs will also change accordingly. The results in Section V-D is only for a fixed long path threshold LP thr (0.7T ). Table VIII presents the results for two different long path thresholds (0.7T to 0.8T) for tv80 benchmark. It can be seen that different long path threshold will significant different results. When the long path threshold increases, the weight of each pattern decreases and the number of selected pattern decreases as well. In real application, the long path threshold should be selected by analyzing silicon data, and could be different from technology to technology. F. CPU Runtime Analysis Table IX presents the CPU runtime of implementing our method on n-detect pattern sets (n = 1, 3, 5, 8, and 10) for the tv80 benchmark. It can be seen that as n increases, the pattern count increases. The CPU runtime of the pattern evaluation and selection procedure also increases with the pattern count when considering: 1) only process variations

12 1140 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 6, JUNE 2013 TABLE IX CPU RUNTIME OF DIFFERENT PATTERN SETS FOR tv80 n-detect 1-detect 3-detect 5-detect 8-detect 10-detect # patterns CPU (PV) CPU (PV+Xtalk) 48 s 2m17 s 4m2 s 6m32 s 8m3 s 18m57 s 48m28 s 1h19m2 s 2h1m59 s 2h30m3 s (Row 3 in Table IX) and 2) process variations and crosstalk (Row 4 in Table IX). Furthermore, CPU runtime increases significantly when considering crosstalk effects. This is because our procedure calculates crosstalk effects in the most accurate way by considering many parameters. For each net on the path, the procedure extracts: 1) all its neighboring nets with coupling capacitances from the layout database (i.e., the coupling capacitance threshold for aggressor filtering is 0); 2) the arrival time; and 3) transition directions on the neighboring nets (if any) for each pattern. The complexity can be a tradeoff with accuracy. For instance, if we: 1) set a coupling capacitance threshold to reduce the number of aggressors of each victim net and 2) bypass the arrival time extraction and calculation, the crosstalk analysis complexity will be reduced dramatically. We have successfully applied this technique to a large industry design, in which the pattern selection procedure can be finished in a few hours. Due to intellectual property restrictions, we are unable to include these results in this paper. Nevertheless, press releases on this aspect of this paper are available on the web [43], [44]. Note that the timing-aware TDF ATPG on the tv80 benchmark takes about 1 h and 2 min, and the CPU time of n-detect timing-unaware TDF ATPG (n = 1, 3, 5, 8, and 10) on this benchmark is less than 2 min. As seen from the table, our pattern evaluation and selection procedure consume a considerably lower CPU runtime when only process variations are considered. The top-off ATPG is quite fast and consumes a negligible CPU runtime. When taking crosstalk into consideration, the CPU runtime of evaluating five-detect pattern set is close to that of timing-aware ATPG. Even though our method is quite fast, comparing it with timingaware ATPG does not seem fair since our method takes extra features into account during pattern generation. Furthermore, we believe that our method s CPU runtime can be further reduced by better programming, optimizing the data structures and algorithms. VI. CONCLUSION In this paper, we presented a novel pattern evaluation and selection procedure for screening small delay defects. The proposed procedure takes into account process variations and crosstalk to evaluate their impact on path delay. The accuracy of the calculation procedures was validated by comparing with SPICE simulation. Although we used n-detect pattern set as our initial pattern repository, our flow can be applied to any kind of pattern repository, and efficiently identify high-quality patterns, that sensitize a large number of LPs. The method was implemented on several ISCAS and IWLS benchmarks, and the results demonstrated its effectiveness for reducing the pattern count and significantly increasing the number of sensitized LPs. As future research, we plan to perform the following works. 1) Add power supply noise to our pattern evaluation procedure to take into account its impact on path delay. 2) Perform fault classification and select critical faults, i.e., faults with small slack for this procedure. We expect such classification significantly reduces the CPU runtime. APPENDIX LINDEBERG S CONDITION AND CLT In probability theory, Lindeberg s condition is a sufficient condition for the CLT to hold for a sequence of independent random variables [40]. Let (, F, P) be a probability space, and X k : R, k N to be independent random variables defined on that space. Assume that the expected values of {X k } E[X k ]=μ k and variances Var[X k ] = σk 2 exist and finite. Also let sn 2 = N k=1 σk 2. If the sequence of independent random variables X k satisfies the Lindeberg s condition lim N 1 N { sn 2 k=1 X k μ k >ξs N } (X k μ k ) 2 dp = 0 for all ξ>0 (10) the CLT holds. The above integral is a Lebesgue integral over the set { X k μ k >ξs N } [40]. If the sequence of independent random variables satisfies lim max σ k 2 N sn 2 = 0. (11) Lindeberg s condition is both necessary and sufficient condition for the CLT. In this paper, we assume that the random variables corresponding to the delays of the path segments, X 1, X 2,...,X N are independent of each other. Let E[X i ]= μ i, Var[X i ]=σi 2,where1 i N. Let μ = σ 2 = N μ i (12) i=1 N i=1 σ 2 i. (13) Obviously, the delay variation introduced by process variations σi 2 is bounded and therefore finite. Due to the imperfection of manufacture process, σi 2 is larger than 0. Therefore, we have m σi 2 M (14) where m and M are lower and upper bounds of the delay variations, respectively. So lim σ 2 lim Nm (15) N N lim N σ 2 i σ 2 lim N M Nm 0 (16)

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Available: kes/asic/iscas/ Ke Peng (S 09 M 11) received the B.E. degree in electronic information engineering from the Northwestern Polytechnical University, Xi an, China, in 2004, the M.S. degree from the Institute of Electronics, Chinese Academy of Sciences, Beijing, China, in 2007, and the Ph.D. degree from the Electrical and Computer Engineering Department, University of Connecticut, Storrs, in He joined the DFT Team, Microcontroller Solutions Group, Freescale Semiconductor, Austin, TX, in His current research interests include design for testability, automatic test pattern generation, small-delay defects detection, and tests and diagnoses for power supply noises and crosstalks.

14 1142 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 6, JUNE 2013 Mahmut Yilmaz (S 07 M 09) received the B.S. degree from Bogazici University, Istanbul, Turkey, in 2004, and the M.S. and Ph.D. degrees from Duke University, Durham, NC, in 2006 and 2009, respectively. He is currently a Senior DFT Engineer with NVIDIA, Santa Clara, CA. His current research interests include design for testability, and physical aware and timing-aware ATPG for industrial digital circuits. Dr. Yilmaz was a recipient of the Test Technology Technical Council Best Doctoral Thesis Award in and a Distinguished Lecturer of the IEEE Circuits and Systems Society from 2012 to He is the Editor-in-Chief of the IEEE DESIGN AND TEST OF COMPUTERS and the ACM Journal on Emerging Technologies in Computing Systems. He is an Associate Editor of the IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART II: EXPRESS BRIEFS the IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYS- TEMS, the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, and the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART I: REGULAR PAPERS.HeservesasanEditoroftheJournal of Electronic Testing: Theory and Applications. Krishnendu Chakrabarty (S 92 M 96 SM 02 F 08) received the B.Tech. degree from the Indian Institute of Technology, Kharagpur, India, in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively. He is currently a Professor of electrical and computer engineering with Duke University, Durham, NC. He is a Chair Professor in software theory with Tsinghua University, Beijing, China. He has authored or co-authored 12 books on these topics, published over 400 papers in journals and refereed conference proceedings, and given over 180 invited, keynote, and plenary talks. His current research interests include testing and design for testability of integrated circuits, digital microfluidics, biochips, and cyber physical systems, and optimization of digital print and enterprise systems. Dr. Chakrabarty was a recipient of the National Science Foundation Early Faculty Award, the Office of Naval Research Young Investigator Award, the Humboldt Research Fellowship from the Alexander von Humboldt Foundation, Germany, and several Best Paper Awards at IEEE conferences. He is a Golden Core Member of the IEEE Computer Society, and a Distinguished Engineer of ACM. He was an Invitational Fellow of the Japan Society for the Promotion of Science in He was a recipient of the Duke University Graduate School Dean s Award for Excellence in Mentoring in 2008, and the Capers and Marion McDonald Award for Excellence in Mentoring and Advising in 2010, Pratt School of Engineering, Duke University. He served as a Distinguished Visitor of the IEEE Computer Society from 2005 to 2007 and as a Distinguished Lecturer of the IEEE Circuits and Systems Society from 2006 to Currently, he has been serving as an ACM Distinguished Speaker, a Distinguished Visitor of the IEEE Computer Society from 2010 to Mohammad Tehranipoor (S 02 M 04 SM 07) is currently an Associate Professor of electrical and computer engineering with the University of Connecticut, Storrs. He has authored or co-authored over 140 journal articles and refereed conference papers, two books, and seven book chapters. His current research interests include computer-aided design and tests, reliability analyses, and hardware security and trust. Dr. Tehranipoor was a recipient of the Best Paper Award from the VLSI Test Symposium (VTS) in 2005, the Best Paper Award from the North Atlantic Test Workshop (NATW), the Best Paper Award at NATW in 2009, the Honorable Mention for Best Paper Award at NATW in 2008, the Best Paper Candidate from the Design Automation Conference in 2006, and the Best Panel Award at VTS in He was a recipient of the IEEE Computer Society Meritorious Service Award in 2008, the National Science Foundation CAREER Award in 2009, and the UConn ECE Research Excellence Award. He serves on the program committee of several leading conferences and workshops. He was the Program Chair of the IEEE Defect-Based Testing Workshop in 2007, the Program Chair of the IEEE Defect and Data Driven Testing in 2008, the Co-Program Chair of the International Defect and Fault Tolerance in VLSI Systems (DFT) in 2008, and the General Chair for D3T-2009 and DFT He co-founded a new workshop called the IEEE International Workshop on Hardware-Oriented Security and Trust (HOST) and served as the HOST-2008 and the HOST General Chair and the Chair of the Steering Committee. He is currently serving as an Associate Editor for the Journal of Electronic Testing: Theory and Applications and the IEEE DESIGN AND TEST OF COMPUTERS, the Journal of Low Power Electronics. He is a member of the ACM and ACM SIGDA.