Regularity for Reduced Variability

Transcription

1 Regularity for Reduced Variability Larry Pileggi Carnegie Mellon 28 July 2006

2 CMU Collaborators Andrzej Strojwas Slava Rovner Tejas Jhaveri Thiago Hersan Kim Yaw Tong Sandeep Gupta Xin Li Norris Lui Jon Proesel Umut Arslan 28 July 2006 Slide 2

3 Layout Dependent Variations Layout dependent variations are having an increasingly dominant impact on functional and parametric yield Pattern Dependent Random Parametric Source: PDF Solutions Percent of Yield Loss 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 130nm 90nm 65nm 28 July 2006 Slide 3

4 Layout Dependencies Example: Without SRAM-layout specific SPICE models, design closure would be improbable for scaled CMOS Statistical transistor models based on all possible patterns produce a very wide noise margin distribution SRAM Number of Samples σ = nm bulk CMOS Static Noise Margin (Normalized) DR compliant SPICE models 28 July 2006 Slide 4

5 Layout Dependencies Based on 1000-simulation-run Monte Carlo SRAM Number of Samples σ = σ = Number of Samples Static Noise Margin (Normalized) DR compliant SPICE models Static Noise Margin (Normalized) SRAM-layout-specific SPICE models 28 July 2006 Slide 5

6 Micro-Regularity Grid of CD shapes with 500nm pitch Frequency response suggests that simple RETs would be effective for controlling this set of patterns 2-D FFT plots of poly-si patterns Highest peak at 2 Hz (2 objects per micron) 28 July 2006 Slide 6

7 Macro-Regularity Less restriction is required for the patterns that can be encapsulated within macro-regular pattern groups Can pre-qualify fundamental elements in silicon for known pattern neighborhoods Pattern neighborhood is known, therefore cells can be reliably implemented to create manufacturable arrays Macro-Regularity for cell-to-cell variations Micro-regularity for transistor-to-transistor variations 28 July 2006 Slide 7

8 90nm Memory Array Macro-regularity evident from repeated bit-cells Spread of impulses due to lack of micro-regularity in bit-cells, but patterns validated in silicon via trial-and-error 2-D FFT plots of poly-si patterns 28 July 2006 Slide 8

9 Standard Logic Cells Increasingly difficult to apply RETs and precisely print all patterns with a single optical setup for these 90nm std cells 2-D FFT plots of poly-si patterns 28 July 2006 Slide 9

10 Micro- and Macro-Variability Impact Ex: identical min size transistors measured for three different physical environments on the same 65nm IC Ioff (log) Source: PDF Solutions Env I Idrive Env II Env III Macro-regularity can provide for identical pattern environments for devices and cells Micro-regularity is an area/performance vs. variability trade-off 28 July 2006 Slide 10

11 Full Adder Ring Oscillator Micro-regular layout expected to enhance printability Expect reduced variability tighter Tp and Idc variation E.g. Tp ~ gate_length; Idc ~ exp(gate_length) osc B_7 A_7 Cout Cin sum B_6 A_6 Cout Cin sum B_1 A_1 Cout Cin sum B_0 A_0 Cout Cin sum 0 28 July 2006 Slide 11

12 Layout Comparison Std cell and regular mirror adders Regular adder based on SRAM FEOL-like pushed rules that are enabled by regularity to provide for comparable area design Std cell layout based on wrong-way poly with multiple jogs, diffusion routing, and multiple metal routing directions Standard cell mirror adder 3.6μm x 2.6 μm 9.4 μm 2 Regular Logic Fabrics 2.88μm x 3.2 μm 9.2 μm 2 28 July 2006 Slide 12

13 Extra Capacitance on CICO Path Larger diffusion areas due to on-grid placement of poly, contacts and metals but identical transistor sizing for both adders input output output internal internal input Standard cell mirror adder Total diffusion area at switching nodes = 0.26 μm 2 Regular Logic Fabrics Total diffusion area at switching nodes = 0.57 μm 2 28 July 2006 Slide 13

14 Wafer Probe Measurements Commercial 65nm bulk process Distributed ROs throughout wafer Measured 1 wafer thus far (147 sites) 2 sites with failed measurements for standard cell adder More measurements planned to show consistency of results across multiple wafers 28 July 2006 Slide 14

15 Delay vs. Idc for 1.2V (normalized by min current) 28 July 2006 Slide 15

16 Idc for 1.2V (values normalized by min current) 28 July 2006 Slide 16

17 Tp for 1.2V Microregularity incurs delay penalty due to extra parasitic C (values normalized by min current) 28 July 2006 Slide 17

18 Mean, Std. Deviation, and Coeff. Of Var. Mean μ = 1 N N i = 1 x i N 1 2 σ = ( x i μ) N 1 i = 1 assuming x i are independent, identically distributed samples Std. Deviation Coefficient of Variation is σ μ 28 July 2006 Slide 18

19 Static Current Comparisons (CICO) 8.0 Mean Static Current N o rm alized S tatic C urrent Normalized Standard Deviation Standard Cell Regular Fabric Vdd (V) Standard Deviation Standard Cell Regular Fabric Vdd (V) Normalized Coefficient of Variation σ/μ Coefficient of Variation Standard Cell Regular Fabric Vdd (V) 28 July 2006 Slide 19

20 Propagation Delay Comparison (CICO) Normalized Propagational Delay Normalized Standard Deviation Mean Propagational Delay Standard Cell Regular Fabric Vdd (V) Standard Deviation Standard Cell Regular Fabric Vdd (V) Slightly higher nominal delay expected due to increased parasitics for pushed-rule regular fabric adder Normalized Coefficient of Variation Coefficient of Variation Standard Cell Regular Fabric Vdd (V) 28 July 2006 Slide 20

21 Variations - Tp per Vdd = 1.2V Wafermaps of abs(x - μ), normalized by max value Standard cell mirror adder μ= σ = Regular mirror adder μ = σ = July 2006 Slide 21

22 Variations Idc per Vdd = 1.2V Wafermaps of abs(x - μ), normalized by max value Standard cell mirror adder μ= σ = Regular mirror adder μ = σ = July 2006 Slide 22

23 Outlier Count (Tp) Count of outlyers beyond 3σ σ = σ = Non-Regular mirror adder (all paths) # of outliers = Regular mirror adder (all paths) # of outliers = 0 28 July 2006 Slide 23

24 Outlier Count (Idc) Count of outliers beyond 3σ 7 6 σ = σ = Non-Regular mirror adder (all paths) # of outliers = Regular mirror adder (all paths) # of outliers = July 2006 Slide 24

25 Observations Any difference is due solely to micro-regularity of layout Both designs are macro-regular Implementations have identical transistor topology and sizing Difference in spread is most prominent in Idc Exponentially dependent on gate length We expect a greater variability impact when comparing macro-regularity differences 28 July 2006 Slide 25

26 Macro-Regular Logic Bricks Recently proposed macro-regular design via regular bricks Less cell-to-cell variation, as in SRAM bit-cells Total number of geometry patterns dramatically reduced Provides known pattern neighborhood to adjacent bricks Tighter characterization with known electrical environments Microregular logic r Microregular logic Microregular logic wellcharacterized, predictable pattern environments like memories 28 July 2006 Slide 26

27 Optimal Brick Size Big enough to satisfy optical proximity constraints Small enough to allow characterization and optimization Specific enough to minimize wasted logic Generic enough to allow reuse over multiple logic functions Total Area Small generic cells; (micro-regularity penalty) Big, generic bricks (wasted logic) Fewer Patterns Logic Efficiency Brick Size 28 July 2006 Slide 27

28 Experimental Flow 28 July 2006 Slide 28

29 ARM9 Implementation 65nm Low Power CMOS Std Cell Spec Design: 16KB D cache, 32KB I cache 250MHz worst case Area: mm 2 Bricks derived from 7 fixed-size primitives 3 Flip Flop types Various INV sizes for buffering 16 fixed-size application-specific bricks MMU DCache Identical block footprint area for bricks and std cell designs ICache 28 July 2006 Slide 29

30 ARM9 Implementation Results Std cells based on full sizing and resynthesis using complete library 40% more buffer area for bricks design due to sizing limitations Does not measure potential improvement in parametric yield Standard Cells (not on grid) Primitives (on grid) Regular Bricks (using primitive mapping) Silicon Whitespace (%) Relative WC Timing (%) Brick design has slightly less whitespace but fewer nets to route Simulation results do not capture improvement in control of variations, or improvement with Brick-specific synthesis and flow 28 July 2006 Slide 30

31 ACLV comparison Normalized Leff comparison based on ACLV simulations at nominal process conditions for DFFs: µ 3σ Std Cells FEOL push-rule Bricks July 2006 Slide 31

32 Regularity-Friendly Circuits Can further consider circuits and topologies which better match regular brick methodology and constraints Example: New DFF topology can reduce footprint, require only single clk polarity, and provide 20-40% improvement in speed 28 July 2006 Slide 32

33 Statistical Optimization Bricks can be statistically optimized for sizing w.r.t. variations We expect that macro-regularity of bricks vs. standard cells will provide substantial improvement in predictability Contact placement STI-Poly distance stress Random Dopant Active corner Adjacent stress Poly corner 28 July 2006 Slide 33

34 Conclusions and Future Directions Forms of Regular Fabrics appear to offer advantages beginning at 65nm node Benefits of reduced design margins have yet to be fully measured With limited number of bricks we can optimize them for better control and prediction of variations Both systematic (those which we can model) and random (those which cannot completely model) variations can be reduced Can carefully design bricks to reduce sensitivity to random variations 28 July 2006 Slide 34