EE582 Physical Design Automation of VLSI Circuits and Systems
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1 EE582 Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University Preliminaries
2 Table of Contents Semiconductor manufacturing Problems to solve Algorithm complexity analysis 2
3 Semiconductor Manufacturing Layout (GDSII stream format) Foundry (Semiconductor manufacturing) TSMC, Global Foundries, Bare dies 3
4 Semiconductor Manufacturing Input Layout (GDSII stream format) A set of geometric objects VDD 2 in 1 n-well out p-well 1: Layer id 3, polygon { 50, 40, 70, 40, 70, 220, 50, 220, 50, 140, 20, 140, 20, 110, 50, 110, 50, 40 } 2: Layer id 7, rectangle { 10, 105, 40, 150 } p-well n-well GND 4
5 Semiconductor Manufacturing 5
6 Semiconductor Manufacturing M3 M2 M1 p+ n+ n+ p+ p+ n+ n-well p-epi substrate 6
7 Semiconductor Manufacturing p-epi p+ substrate 7
8 Semiconductor Manufacturing SiO 2 p-epi p+ substrate Gate-oxide deposition 8
9 Semiconductor Manufacturing SiO 2 p-epi p+ substrate Photoresist 9
10 Semiconductor Manufacturing SiO 2 p-epi p+ substrate Mask 10
11 Semiconductor Manufacturing SiO 2 p-epi p+ substrate Expose (photolithography) 11
12 Semiconductor Manufacturing SiO 2 p-epi p+ substrate After photolithography 12
13 Semiconductor Manufacturing SiO 2 p-epi p+ substrate Remove mask 13
14 Semiconductor Manufacturing p-epi p+ substrate Etching 14
15 Semiconductor Manufacturing p-epi p+ substrate Etching 15
16 Semiconductor Manufacturing p-epi p+ substrate Oxide deposition 16
17 Semiconductor Manufacturing p-epi p+ substrate Photoresist 17
18 Semiconductor Manufacturing p-epi p+ substrate Mask 18
19 Semiconductor Manufacturing p-epi p+ substrate Photolithography 19
20 Semiconductor Manufacturing p-epi p+ substrate After photolithography 20
21 Semiconductor Manufacturing p-epi p+ substrate Etch 21
22 Semiconductor Manufacturing p+ (p-well) p-epi p+ substrate Doping 22
23 Semiconductor Manufacturing n+ (n-well) p+ (p-well) p-epi p+ substrate Doping 23
24 Semiconductor Manufacturing n+ (n-well) p+ (p-well) p-epi p+ substrate Poly 24
25 Semiconductor Manufacturing n+ (n-well) p+ (p-well) p-epi p+ substrate Etch 25
26 Semiconductor Manufacturing p+ p+ n+ n+ n+ (n-well) p+ (p-well) p-epi p+ substrate Doping 26
27 Semiconductor Manufacturing SiO 2 p+ p+ n+ n+ n+ (n-well) p+ (p-well) p-epi p+ substrate Oxide deposition 27
28 Semiconductor Manufacturing contact SiO 2 p+ p+ n+ n+ n+ (n-well) p+ (p-well) p-epi p+ substrate Contact 28
29 Semiconductor Manufacturing contact SiO 2 p+ p+ n+ n+ n+ (n-well) p+ (p-well) p-epi p+ substrate Metal 1 29
30 Semiconductor Manufacturing contact SiO 2 p+ p+ n+ n+ n+ (n-well) p+ (p-well) p-epi p+ substrate Via12 30
31 Semiconductor Manufacturing p-epi p+ substrate Chemical-mechanical-polishing (CMP) 31
32 Problems Partitioning You are given A set of modules M1 (area: 10), M2 (area:20), Netlist N1 (M1, M2), N2 (M2, M3, M4), Find k partitions Satisfy the following constraints: S min Size(P k ) S max Minimize Cutsize 32
33 Problems Partitioning 33
34 Problems Floorplanning You are given A set of modules M1 (w: 10, h: 20), M2 (w: 30, h: 10), Netlist N1 (M1, M2), N2 (M2, M3, M4), Find a floorplan Minimize Area Wirelength 34
35 Problems Floorplanning 35
36 Problems Floorplanning More complex floorplanning Some modules are rotatable. M1, M4, M6, Some modules are soft. M2 (w min : 10, w max : 20, area: 150), Some modules have fixed locations. The outline is fixed (fixed-outline floorplanning) Find a floorplan Minimize Area Wirelength 36
37 Problems Floorplanning More complex floorplanning Each module also has power profile. Each net has access frequency profile. Find a floorplan Minimize Area Interconnect power Worst-case temperature Maximize Performance Achieve 100% routability 37
38 Problems Placement Global placement You are given A set of standard cells (and their dimensions) C1 (NAND2_X4), C2 (FA_X4), Netlist N1 (C1/Z, C3/A, C4/A, C5/B), N2 (C2/S, C6/A), Core area Width: 1,000um, Height: 1,000um Find the (non-legal) locations of the cells Satisfy Density (W j ) D max (e.g., 70%) Minimize Total wirelength 38
39 Problems Placement More complex global placement You are also given Timing libraries Find (non-legal) locations of the cells Satisfy Density (W j ) D max (e.g., 70%) Minimize Worst net delay Worst path delay 39
40 Problems Placement More complex global placement You are also given Routing resources Find (non-legal) locations of the cells Satisfy Density (W j ) D max (e.g., 70%) Maximize Routability 40
41 Problems Placement Legalization You are given A set of standard cells (and their dimensions) Netlist C1 (NAND2_X4), C2 (FA_X4), N1 (C1/Z, C3/A, C4/A, C5/B), N2 (C2/S, C6/A), Core area Width: 1,000um, Height: 1,000um Initial (non-legal) locations of the cells C1 (100, 100), C2 (101, 100), Find the legal locations of the cells 41
42 Problems Placement Detailed placement You are given A set of standard cells (and their dimensions) C1 (NAND2_X4), C2 (FA_X4), Netlist N1 (C1/Z, C3/A, C4/A, C5/B), N2 (C2/S, C6/A), Core area Width: 1,000um, Height: 1,000um Initial (legal) locations of the cells C1 (100, 100), C2 (105, 100), Optimize Total wirelength Routability Design-rule violations 42
43 Problems Routing Global routing You are given A set of pin locations P1 (50, 100), P2 (55, 150), Netlist N1 (P1, P4, P6), N2 (P2, P3), Core area Width: 1,000um, Height: 1,000um Detailed placement result Find a global routing solution Minimize Total wirelength Minimize runtime 43
44 Problems Routing Global routing n1 n5 n4 n2 n3 Each boundary can accommodate two nets. 44
45 Problems Routing Global routing Steiner routing (for multi-fanout nets) 45
46 Problems Routing Detailed routing You are given A set of pin locations P1 (50, 100), P2 (55, 150), Netlist N1 (P1, P4, P6), N2 (P2, P3), Core area Width: 1,000um, Height: 1,000um Global routing result Detailed routing resources Find a detailed routing solution Minimize Total wirelength Maximize Routability 46
47 Problems Routing Detailed routing Channel routing Two metal layers A B C D A C D 5 tracks E B E A C D A 47
48 Problems Interconnect Delay calculation 48
49 Problems Timing Analysis 10ps d2 8ps 5ps 35ps 1ps 25ps 5ps 40ps 5ps 1ps 60ps 2ps 49
50 Problems Power Analysis IR drop VDD (M1) GND (M1) VDD (M2) GND (M2) 50
51 Problems Power Analysis LL dddd dddd noise VDD 51
52 Problems Cross-talk Aggressor Victim Delay Signal inversion 52
53 Problems Interconnect Optimization Buffer insertion You are given An RC tree A set of available buffers Bufferable locations Minimize by buffer insertion Net delay 53
54 Problems Interconnect Optimization Buffer insertion What to consider Slew computation / estimation / propagation Delay calculation Bufferable locations Routing topology generation Power consumption 54
55 Problems Interconnect Optimization Gate sizing You are given An RC tree A set of available buffers Minimize by gate sizing Net delay Path delay 55
56 Problems Clock Tree Synthesis CTS You are given F/Fs and their locations A set of available buffers RC characteristics of the interconnect Minimize Clock skew Power consumption Noise Slew 56
57 Problems Clock Tree Synthesis 57
58 Problems Low-Power Design Power gating 58
59 Problems Low-Power Design Clock gating 59
60 Problems DFM Design for Manufacturability (DFM) Chemical-Mechanical Polishing (CMP) 60
61 Problems DFM Metal fill insertion 61
62 Problems DFM Metal fill insertion 62
63 Problems DFM Lithography 63
64 Problems DFM Lithography Optical Proximity Correction (OPC) 64
65 Problems DFM Lithography Multiple patterning 65
66 Complexity Analysis Sorting algorithms Bubble sort Merge sort Bucket sort 66
67 Complexity Analysis Bubble Sort Pseudo code for ( int i=0 ; i<5 ; i++ ) { for ( int j=i+1 ; j<5 ; j++ ) { if ( array[j] < array[i] ) swap (array[i], array[j]); } } 67
68 Complexity Analysis Bubble Sort Pseudo code for ( int i=0 ; i<5 ; i++ ) { for ( int j=i+1 ; j<5 ; j++ ) { if ( array[j] < array[i] ) swap (array[i], array[j]); } } i:0, j: swap i:0, j: i:0, j: swap i:0, j: i:1, j: swap i:1, j: swap i:1, j:4 68
69 Complexity Analysis Bubble Sort Pseudo code for ( int i=0 ; i<5 ; i++ ) { for ( int j=i+1 ; j<5 ; j++ ) { if ( array[j] < array[i] ) swap (array[i], array[j]); } } i:2, j: swap i:2, j: i:3, j: swap done # iterations (for five elements): # iterations (for n elements): (n-1) + (n-2) = Complexity of the if statement: O(1) = constant Final: O(n 2 ) nn 1 nn 2 = O(n 2 ) 69
70 Complexity Analysis Merge Sort Pseudo code Split (left, right) { if ( (right left) 2 ) { Split (left, (left+right)/2); Split ((left+right)/2, right); Merge (left, (left+right)/2, right); } } 70
71 Complexity Analysis Merge Sort Idea Sorted list Sorted list 2 L Sorted list 1 Sorted list 2 L Sorted list 1 Sorted list 2 71
72 Complexity Analysis Merge Sort Idea L Sorted list 1 Sorted list 2 L Sorted list 1 Sorted list 2 L Sorted list 1 Sorted list 2 72
73 Complexity Analysis Merge Sort Idea L Sorted list 1 Sorted list 2 L Sorted list 1 Sorted list 2 L Sorted list 1 Sorted list 2 73
74 Complexity Analysis Merge Sort Idea L Sorted list 1 Sorted list 2 L Sorted list 1 Sorted list 2 L Sorted list 1 Sorted list 2 74
75 Complexity Analysis Merge Sort Height = log 2 n Step 1 Step 2 Step 3 Complexity: O(n * log 2 n) 75
76 Complexity Analysis Bucket Sort We know the range of the values. [1, 10] 7, 3, 3, 1, 6, 8, 3, 6, 8, 6, 4, 2, 2, 7, 8, 3 76
77 Complexity Analysis Bucket Sort 7 1, 3 1, 3 2, 1 1, 6 1, 8 1, 3 3, 6 2, 8 2, 6 3, 4 1, 2 1, 2 2, 7 2,
78 Complexity Analysis Bucket Sort 7 1, 3 1, 3 2, 1 1, 6 1, 8 1, 3 3, 6 2, 8 2, 6 3, 4 1, 2 1, 2 2, 7 2,
79 Complexity Analysis Bucket Sort 7 1, 3 1, 3 2, 1 1, 6 1, 8 1, 3 3, 6 2, 8 2, 6 3, 4 1, 2 1, 2 2, 7 2,
80 Complexity Analysis Bucket Sort 7 1, 3 1, 3 2, 1 1, 6 1, 8 1, 3 3, 6 2, 8 2, 6 3, 4 1, 2 1, 2 2, 7 2,
81 Complexity Analysis Bucket Sort 7 1, 3 1, 3 2, 1 1, 6 1, 8 1, 3 3, 6 2, 8 2, 6 3, 4 1, 2 1, 2 2, 7 2, Complexity: O(n)
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