An FPGA Based Adaptive Viterbi Decoder

Transcription

1 An FPGA Based Adaptive Viterbi Decoder Sriram Swaminathan Russell Tessier Department of ECE University of Massachusetts Amherst

2 Overview Introduction Objectives Background Adaptive Viterbi Algorithm Architecture and Implementation Issues Results Related Work Summary and Future Work

3 Introduction A Digital Data Communication System Source information Bitstream Bitstream with redundancy Source Encoder Channel Encoder Convolutional encoder Modulator Noise Sink Source Decoder Channel Decoder DeModulator Bitstream Viterbi

4 Goals Implement Adaptive Viterbi Algorithm on hardware Constraints Data rate (or throughput) - 20 Kbps Probability of Error or Bit Error Rate (BER) < 10-5 Minimize # of errors / Length of Sequence Design-time area

5 Convolutional Encoder Accepts information bits as a continuous stream Operates on the current b-bit input, where b ranges from 1 to 6 and some number of immediately preceding b-bit inputs to produce V output bits, V > b b =1, V =2 1 FF FF

6 Definitions Constraint Length Number of successive b-bit groups of information bits for each encoding operation Denoted by K Code Rate (or) Rate b/v Typical values K : 7 Rate : 1/2, 1/3

7 The Viterbi Algorithm Finds a bit-sequence in the set of all possible transmitted bit-sequences that most closely resembles the received data. Maximum likelihood algorithm Each bit received by decoder associated with a measure of correctness. Practical for short constraint length convolutional codes

8 State diagram State 0/00 Encoder memory Branch 0/ /11 k/ij, 1/00 where i and j represent the output bits associated with 0/01 0/10 1/01 input bit k 11 1/10

9 Trellis Diagram T=0 T=1 T=2 T= ENC IN : ENC OUT : RECEIVED: Accumulated metric 2+2,3+0 : 3 0+1,3+1 : 1 2+0,3+1 : 2 0+1,3+1 : 1 K = 3 Rate ½ Total number of states = 2 K-1

10 Adaptive Viterbi Algorithm Motivation Extremely large memory and logic for Viterbi Algorithm Fewer number of paths retained Reduced memory and computation Definitions Path Bit sequence Path metric or cost Accumulated error metric of a path Survivor Path which is retained for the subsequent time step

11 Adaptive Viterbi Algorithm Criterion for path survival 1. A threshold T is introduced such that a path is retained if and only if current path metric is less than d m +T, where d m is the minimum cost among all survivors of the previous time step. 2. The total number of survivors per time step is limited to a critical number called N max selected by user. Only best N max paths have to be retained at any time.

12 Trellis Diagram for AVA

13 Parameters in the algorithm Constraint length K Truncation length, T L Rate R Threshold T Maximum # of paths per time N max

14 Influence of Threshold T and N max Threshold T Smaller T, low average # of survivors, increased BER Larger T, high average # of survivors, reduced BER Nmax Smaller N max Possibility of discarding the best path => high BER Smaller area Larger N max Reduced BER Larger area Selection of N max and T crucial

15 Variation of BER with T and N max for K = 9 & 14 T=24 N max = 41 K = 14, SNR = 2.5 db, T L =70 T=18 N max = 9 K = 9, SNR = 3.1 db, T L =45

16 Optimal values of Nmax, T and T L for different K s K T L N max T

17 Simplified View of Adaptive Viterbi Decoder Symbols from channel Branch metric generator Branch metrics Add Compare Select Decision Bits Survivor Memory Decoded output Logic for d i < d m + T

18 Survivor Memory Store all possible bitsequences(paths) before making a decision Size of memory for Viterbi : Truncation length Rows : N max Columns : Truncation Length - (3-5) * K Two schemes Traceback Large Latency, small area, low power Register Exchange Fast, Large area, large power N max

19 Practical Considerations Serial Implementation Same ACS repeatedly used for all states Small area, Inexpensive Slow, Low throughput (data rate) Parallel Implementation Each State has its own ACS (2 K-1 ACS) Fast, High throughput (data rate) Large area, bottleneck for large K values

20 Architecture

21 Architecture (contd.) b1 sum1 b2 sum2 Add Add d i < d m + T d i < d m + T yes yes Count paths Elimination of sorting yes Count < N max no Update memory T = T-2

22 System Model Test-bench

23 FPGA Implementation FPGA can exploit the parallelism Dynamic reconfiguration for performance enhancement Implementation platform WildOne-XL FPGA board from Annapolis Microsystems Inc. 2 XC4036 FPGAs, one for user application Simulation on Virtex XCV1000

24 Hardware implementation RTL description in VHDL HDL Simulation Cadence Affirma tools Synthesis Synplicity Synplify Pro FPGA Mapping, place and route Xilinx Foundation 2.1i FPGA XC4036XL-08

25 XC4036XL FPGA Resource utilization K CLBs LUTs FFs 4i/p 3i/p K T L N max T

26 Decoding rate on XC4036 FPGA Overheads 32-bit, 33 MHz PCI bus Execution of Wildone API using VC++ Slowdown times Decoding rate in Kbps no overhead with overhead Constraint length, K FPGA freq.(mhz)

27 Issues in Reconfiguration Reconfigurable Units Number of ACS units (depends on number of survivors) Run-time survivor memory Reconfiguration types Fine-grained - infeasible Coarse-grained - feasible Motivation Performance improvement Tradeoff Small SNR (noisy channel), Large K, slow decoding Large SNR (less noisy channel), Small K, fast decoding Maintain approx. same BER

28 Coarse-timescale reconfiguration 20.9 % performance improvement over static Decoding rates (Kbps) Individual decoding rates w/o reconfiguration Average decoding rate w/ reconfiguration Less Noisy channel Constraint length K Noisy channel

29 Coarse-timescale reconfiguration Experimental Approach Vary channel noise during transmission Noise changes ~ 250,000 bits or ~1.5 to 2.5 seconds If noise change is detected Download new decoder configuration content to the FPGA on WildOne board Reconfiguration overhead ~40 ms PCI bus transfer + Noise change detection + download bitstream

30 Comparison with microprocessor Intel Celeron 366 MHz, 128 MB RAM Speed-up Up to 7.5X for XC4036 (incl. overheads) Decoding rate in Kbps w/ PCI overhead FPGA Coprocessor Celeron Processor Constraint length K

31 Conclusions and future work A new adaptive Viterbi decoder dynamically reconfigurable ~21 % improvement over static Scales linearly Speed-up up to 7.5X over a microprocessor Future Research Extend present concept to Power-aware dynamic reconfiguration