SECURE PARTIAL RECONFIGURATION OF FPGAs. Amir S. Zeineddini Kris Gaj

Transcription

1 SECURE PARTIAL RECONFIGURATION OF FPGAs Amir S. Zeineddini Kris Gaj

2 Outline FPGAs Security Our scheme Implementation approach Experimental results Conclusions

3 FPGAs SECURITY

4 SRAM FPGA Security Designer/Vendor should be able to remotely modify the configuration of FPGA without revealing its contents or accepting malicious changes introduced by an attacker Configuration Device SRAM FPGA JTAG SelectMAP Slave/Master Serial ICAP Correspond to configuration modes A series of command and data Bitstream Configuration Interface Configuration Logic Configuration Memory

5 Types of Attacks Cloning Bitstream Exact Copy Reverse Engineering Bitstream Netlist Tampering Countermeasures: Encryption and Authentication Bitstream Tampered Copy

6 Xilinx Solution XILINX ISE Configuration Device XILINX FPGA Bitstream Generator Encryption Software Encrypted Bitstream Configuration Memory Decryptor Key Storage Keys External Battery Keys Major Disadvantages: No flexibility Need of an external battery Partial reconfiguration via the external configuration interfaces is not permitted for encrypted bitstreams.

7 Algotronix Solution Initial Programming: Normal Configuration: SRAM FPGA Configuration Device SRAM FPGA Non-encrypted Bitstream Configuration Device Configuration Interface Encryption Circuit Encrypted Bitstream Configuration Interface Decryption Circuit Encrypted Bitstream Configuration Logic Configuration Memory Configuration Logic Configuration Memory Secret Key Secret Key Tom Kean. Secure Configuration of a Field Programmable Gate Array. FPL 2001 and FCCM 2001.

8 Solution by Bossuet et al. Major Advantages: No hard-wired encryption/decryption circuits No additional battery Major Disadvantages: Not feasible Management of partial reconfiguration Complex system, keys management Configuration Storage IP 1 Encrypted Decryption Circuit 1 IP 2 Encrypted Decryption Circuit 2 IP 3 Configuration Controller FPGA IP 2 IP 3 Keys IP 1 L. Bossuet, G. Gogniat, and W. Burleson. Dynamically configurable security for SRAM FPGA bitstreams. RAW2004.

9 OUR SCHEME

10 Desirable Characteristics Strong protection against: Cloning Reverse engineering Tampering Flexibility Providing the key Choice of a suitable algorithm (security policy) Least amount of fixed resources (hard IP)

11 Our Solution External Memory Xilinx FPGA IP 1 Encrypted Configuration Controller Application System IP 2 Encrypted IP 3 PowerPC or MicroBlaze IP 3 IP 2 IP 1 Processor IP Cores

12 Our Solution (cont.) Solution for a secure partial reconfiguration after initial configuration Method exploits: Embedded processor cores Dynamic Partial Reconfiguration Software Control Scheme provides: Flexibility (arbitrary algorithm for encryption/decryption) NIST approved authentication

13 IMPLEMENTATION

14 Virtex-II Pro Architecture Features: Processor Block RocketIO Multi-Gigabit Transceivers CLB and Configurable Logic SelectIO-Ultra Digital Clock Managers Multipliers and Block SelectRAM We are interested in: Embedded processor core Dynamic partial reconfigurability 4 5

15 Processor Block Contains four components: BRAM IBM CoreConnect Bus Architecture Features: Processor Local Bus (PLB) On-chip Peripheral Bus (OPB) Device Control Register (DCR) Bus BRAM Control PPC 405 Core Interface Logic BRAM BRAM FPGA CLB Array Embedded IBM PowerPC 405D5 RISC CPU core On-Chip Memory (OCM) controllers and interface Clock/control interface logic CPU-FPGA Interfaces OCM Controller OCM Controller

16 Partial Reconfiguration Loading only a subset of frames into the FPGA Different forms: Static: Rest of the device is in reset (shutdown) Dynamic: Rest of the device remains operational Advantages: Runtime reconfiguration Efficient resource utilization Self-reconfiguration: dynamic reconfiguration + specific circuit on the FPGA to control partial reconfiguration

17 Xilinx ML310 Evaluation Board RS232 SMBus System ACE Virtex-II Pro Compact Flash 256 DDR SDRAM SPI EEPROM High Speed PM 1 XC2VP30 FF896 GPIO / LEDs High Speed PM 2 3.3V PCI Intel 10/100 Ethernet NIC TI PCI 2250 RS232 (2) AMD Flash ALi M1535D+ South Bridge GPIO RJ45 5V PCI 3.3V PCI Slots Slots (2) (2) PS/2 K/M Parallel Port IDE (2) USB (2) Audio SMBus

18 Design Tools Xilinx Embedded Development Kit (EDK) Xilinx ISE Foundation design environment Software Libraries: AES encryption / decryption algorithm HMAC-SHA1 authentication algorithm (Both implemented by Dr. B. Gladman)

19 EDK Tools Flow Software Flow Hardware Flow Processor IP MPD Files VHDL / Verilog C / C++ Code PlatGen Synthesizer Compiler Microprocessor Hardware Specification File EDIF IP Netlists Object Files ISE / Xflow Linker System Constraint File Bitstream Data2MEM Download to FPGA Executable Libraries LibGen Microprocessor Software Specification File

20 PowerPC System JTAG Interface Virtex-II Pro XMD JTAG Controller UART User Interface PowerPC 405 PLB-to-OPB Bridge OPB DDR Controller ML310 DDR SDRAM HWICAP BRAM OPB Controller OPB PLB ICAP Controller ICAP PLB = Processor Local Bus OPB = On-chip Peripheral Bus ICAP = Internal Configuration Access Port HWICAP = Hardware ICAP XMD = Xilinx Microprocessor Debugger

21 Hardware Internal Configuration Access Port (HWICAP) Hardware ICAP (HWICAP) is used for: OPB OPB Controller Configuration read/write Loading partial bitstreams ICAP: Subset of SelectMAP interface Located in the lower right corner of the device ICAP Controller ICAP Dualported BRAM

22 MicroBlaze System JTAG Interface XMD Debug Module ILMB MicroBlaze DLMB UART User Interface OPB DDR Controller ML310 DDR SDRAM OPB Wd Timer HWICAP BRAM OPB Controller ICAP Controller OPB Dual Port BRAM Virtex-II Pro ICAP ILMB = Instruction-side Local Memory Bus DLMB = Data-side Local Memory Bus OPB = On-chip Peripheral Bus OPB Wd Timer = OPB Watchdog Timer ICAP = Internal Configuration Access Port HWICAP = Hardware ICAP XMD = Xilinx Microprocessor Debugger

23 EXPERIMENT METHODOLOGY

24 Xilinx Partial Reconfiguration Styles Extent of Partial Reconfiguration Small Large? Difference-based Front-end Modification (HDL Entry, Synthesis, Implementation) Module-based Back-end Modification (Using FPGA Editor) Design Entry HDL Entry/Synthesis Top-level Modified Design.ncd file Initial Design Bitstream BitGen generates a partial bitstream Initial Budgeting Module Active Module Implementation (Map, Place, Route) Final Assembly (Map, Place, Route)

25 Module-based Flow ML310 LEDs XMD JTAG Interface VirtexVirtex-II Pro ML310 DDR SDRAM Bus Macro Bus Macro Bus Macro PowerPC (left) PowerPC selfself-reconfiguring platform area (IPs not shown) XHWICAP Static Module PowerPC (right) PowerPC system in reconfigurable area (IPs not shown) 24-bit Bus Macro Reconfigurable Module ICAP

26 Bus Macro

27 Module-based Flow (cont.) JTAG PowerPC Self-reconfiguring Platform PowerPC System Special Bus Macro ICAP

28 Module-based Flow Evaluation Level of required effort High; needs more than average acquaintance with the tool Level of support of existing tools Limited with frequent errors especially for complex designs Requires: Practical limitations Benefits A full design for initial reconfiguration Special consideration for inter-module communications Different constraints for modules Automation and bounded routing

29 Difference-based Flow User Interface VirtexVirtex-II Pro ML310 LEDs XMD GPIO JTAG Interface OPB DOPB MicroBlaze CPU Core ILMB DLMB ML310 DDR SDRAM DualDual-ported BRAM PowerPC or MicroBlaze 8K of BRAM partially reconfigured in MicroBlaze system area PowerPC / MicroBlaze SelfSelf-reconfigurable platform area (IPs not shown) ICAP Static Area Reconfigurable Area

30 Difference-based Flow (cont.) PowerPC Self-reconfiguring Platform MicroBlaze System ICAP

31 Difference-based Flow Evaluation Level of required effort Medium depending on the changes made and level of acquaintance with the tool Level of support of existing tools Acceptable with occasional errors and problems Practical limitations Not recommended if routing changes are desired Benefits Small partial bitstreams (Multiple-frame Write)

32 RESULTS AND CONCLUSIONS

33 Timing Measurement Method Phases of the program running on the processor core of the configuration controller: Authentication Decryption Configuration 10 measurements 10 measurements 10 measurements

34 Timing Results I PowerPC System Difference-based Flow: 10 measurements for each phase (clock cycles) PowerPC system: no extra component (time-base register) Phase # Std. Dev. Mean % Error MicroBlaze system: OPB Watchdog Timer Size of partial bitstream: bytes Decryption 20,838,769 20,838,876 20,838,769 20,838,769 20,838,769 20,838,776 20,838,876 20,838,776 20,838,879 20,838, ,838, % Configuration 5,630,038 5,631,061 5,630,038 5,630,038 5,631,037 5,630,038 5,628,993 5,630,038 5,628,993 5,631, ,630, % MicroBlaze System Phase # Authentication 13,862,435 13,862,591 13,862,486 13,862,435 13,862,500 13,862,575 13,862,591 13,862,575 13,862,591 13,862, ,862, % Std. Dev. Mean % Error Authentication 77,649,436 77,649,453 77,649,510 77,649,416 77,649,510 77,649,349 77,649,597 77,649,597 77,649,515 77,648, ,649, % Decryption 147,201, ,201, ,201, ,201, ,201, ,201, ,201, ,201, ,201, ,201, ,201, % Configuration 3,175,996 3,175,964 3,175,420 3,175,996 3,175,943 3,175,996 3,175,996 3,175,952 3,176,008 3,175, ,175, %

35 Timing Results II System Authentication Decryption Configuration System Clock Cycles / Byte Clock Cycles / 16 Bytes Block Clock Cycles / 4 Bytes Word PowerPC MicroBlaze 982 5,502 23, ,895 1, Ave. Time Pow erpc (m s) MicroBlaze Throughput Pow erpc (KB/s) MicroBlaze Ratio PPC / MB Comparison of the timing results for each phase PowerPC Faster authentication and decryption time Slower configuration time

36 Device Utilization Summary PowerPC System Number of MULT18X18s Number of RAMB16s Number of SLICEs Number Number Number Number Number of of of of of PPC405s BUFGMUXs DCMs JTAGPPCs ICAPs MicroBlaze System Number of MULT18X18s Number of RAMB16s Number of SLICEs Number Number Number Number of of of of BUFGMUXs DCMs BSCANs ICAPs 0 out of out of out of out out out out out of of of of of out of out of out of out out out out of of of of % 3% 9% 50% 43% 25% 100% 100% 2% 3% 12% 50% 25% 100% 100% Resource usage: PowerPC MicroBlaze Xilinx MicroBlaze soft processor ~950 logic cells (475 Slices)

37 Future Improvements Security Improvements: Storing the partial bitstream in internal memory Storing the key in the battery-powered storage Use of synthesizable Intellectual Property (soft IP) cores which can be readily incorporated into an FPGA for faster decryption and authentication Use of an embedded OS

38 Conclusion It is necessary to improve the security of SRAM FPGAs against different attacks. We propose a solution for secure partial reconfiguration that takes advantage of embedded processor cores and dynamic partial reconfiguration. It provides: Feasible implementation for both hard/soft processor cores Flexibility by using any arbitrary encryption/authentication software core Reasonable resource utilization especially for processor-based systems Analyzing the available methods of partial reconfiguration for Xilinx FPGAs show: A simple methodology along with more support and automation from tools are needed to: Increase the ease of use for designers Decrease the development time

39 Comments? Questions? Thank you