Retiming. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall,

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1 Retiming ( 范倫達 ), Ph.. epartment of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2 ldvan@cs.nctu.edu.tw

2 Outlines Introduction efinitions and Properties Solving Systems of Inequalities Retiming Techniques Conclusion Supplement VLSI-SP--2

3 Introduction (/2) Retiming is a transformation technique used to change the locations of delay elements in a circuit without affecting the input/output characteristics of the circuit. Critical path is defined to be the path with the longest computation time among all paths that contain zero delay. The lower bound on the clock period of the circuit can be achieved by retiming. VLSI-SP--3

4 x(n) Application of Retiming Reduce the clock period. () W(n) () a 2 w(n)=ay(n-)+by(n-2) y(n)=w(n-)+x(n) =ay(n-2)+by(n-3)+x(n) b Introduction (2/2) Reduce the number of registers. Reduce the power consumption and logic synthesis. y(n) x(n) 33% reduction () () W(n) W2(n) 3 u.t. 2 u.t. a b 2 y(n) w(n)=ay(n-) w2(n)=by(n-2) y(n)=w(n-)+w2(n-)+x(n) =ay(n-2)+by(n-3)+x(n) VLSI-SP--

5 Outlines Introduction efinitions and Properties Solving Systems of Inequalities Retiming Techniques Conclusion Supplement VLSI-SP--5

6 efinitions G () V, U : node r (V) : retiming value () w(e) : weight of the edge e in G w r (e) : weight of the edge e in Gr w r (e)=w(e)+r(v)-r(u) ex: r()=, r=, r(3)=, r()= Gr () () w r (3 e 2)=w(3 e 2)+r-r(3) =+-= w r (2 e )=w(2 e )+r()-r =+-= VLSI-SP--6

7 Properties of Retiming.2. The weight of the retimed path p=v e V e e k- Vk is given by w r (p)=w(p)+r(vk)-r(v)..2.2 Retiming does not change the number of delays in a cycle..2.3 Retiming does not alter the iteration bound in a FG..2. Adding the constant value j to the retiming value of each node does not change the mapping from G to Gr. VLSI-SP--7

8 VLSI-SP--8 Property.2. The weight of the retimed path p=v e V e ek- Vk is given by w r (p)=w(p)+r(vk)-r(v). Proof ) ( ) ( ) ( )) ( ) ( ( ) ( )) ( ) ( ) ( ( ) ( ) ( V r V r p w V r V r w e V r V r w e e w p w k k i i k i i k i i k i i i i k i r r

9 Outlines Introduction efinitions and Properties Solving Systems of Inequalities Retiming Techniques Conclusion Supplement VLSI-SP--9

10 Solving Systems of Inequalities Step : raw a constraint graph (a) raw the node i for each of the N variables r i, i=,2.,n. (b) raw the node N+. (c) For each inequality r i -r j k, draw the edge j i from node j to i with length k. (d) For each node i, i=,2,n, draw the edge N+ i from the node N+ to i with length. Step 2: Solve using a shortest path algorithm (a) The system of inequalities has a solution if and only if the constraint graph contains no negative cycles. (b) If a solution exists, one solution is where r i is the minimumlength path from the node N+ to the node i. VLSI-SP--

11 Example.3. with M=5, N= (/2) Given Inequalities: Step : r - r2 r3 - r 5 r - r r - r3 - r3 - r Step 2 : Ref=U5 Bellman-Ford algorithm r (k) (V) r () r r (3) r () V= V=2 V=3 V= V=5 Floyd-Warshall algorithm R (6) = Solution: r =, r 2 =, r 3 =, r =- VLSI-SP--

12 Example.3. with M=5, N= (2/2) Alternative Computation for Floyd-Warshall algorithm R () = R = - - R (3) = R () = R (5) = - - R (6) = r i,j (m+)=min{r i,k (m)+r k,j ()} VLSI-SP--2

13 Outlines Introduction efinitions and Properties Solving Systems of Inequalities Retiming Techniques Cutset retiming and pipelining Systolic transformation Retiming for clock period minimization Conclusion Supplement VLSI-SP--3

14 Cutset Retiming (/2) efinition: A cutset is a set of edges that can be removed from the graph to create 2 disconnected subgraphs. Procedures: Step : Construct 2 disjointed sub-graphs G and G2 Step 2: Add k delays to each edge from G to G2 and remove k delays from each edge from G2 to G. Feasible solution of cutset retiming wr(g->g2)=w(g->g2)+r(g2)-r(g)=w(g->g2)+k wr(g2->g)=w(g2->g)+r(g)-r(g2)=w(g2->g)-k => -min{w(g->g2)} k min{w(g2->g)} VLSI-SP--

15 Cutset Retiming (2/2) Upper case Cutset = {2->, 3->2, ->} and feasible solution: k Lower case Cutset = {2->, 3->2, ->2} and feasible solution: k G2 G 2 3 k= G2 G 2 k= () () VLSI-SP--5

16 Pipelining Pipelining is a special case of cutset retiming where there are no edges in the cutset from G2 to G, i.e., pipelining applies to graphs without loops. VLSI-SP--6

17 Cutset Retiming and Slow-own Procedure: Replace each delay with N delays to create an N-slow version of the FG. Perform cutset retiming on the N-slow FG. N=2 In (a), CP= & 2 T cp =*+2*2=5 In (c), CP = 2 & 2 T cp =2*+2*2=6 VLSI-SP--7

18 Systolic Transformation z z z ai,2 S b i, 2 ai,2 S b i, 2 z z ai, S b i, ai, S b i, z z z ai, S b i, a i, S b i, Source: L.. Van, "A new 2- systolic digital filter architecture without global broadcast," IEEE Trans. VLSI Systs., vol., pp , Aug. 22. VLSI-SP--8

19 Retiming Relationship Cutset Retiming Pipelining Retiming Systolic Transformation VLSI-SP--9

20 Retiming for Clock Period Minimization (/2) VLSI igital Signal Processing Systems efinition: Φ(G) = max{t(p) : w(p)=} (min. feasible clk period) W(U,V) = min{w(p) : U e V} (U,V) = max{t(p) : U e V and w(p) = W(U,V)} Algorithm for computing W(U,V) and (U,V):. Let M=t max n, where t max is the maximum computation time of the nodes in G and n is the number of nodes in G. 2. Form a new graph G which is the same as G except the edge weights are replaced by w (e)=mw(e)-t(u) for all edges. 3. Solve the all-pairs shortest path problem on G. Let S UV be the shortest path from U to V.. If U V, then W(U,V)=ceiling (S UV /M) and (U,V)=MW(U,V)- S UV +t(v). If U=V, then W(U,V)= and (U,V)=t(U). VLSI-SP--2

21 Retiming for Clock Period Minimization (2/2) W(U,V) and (U,V) are used to determine if there is a retiming solution that can achieve a desired clock period. Given a desired clock period c, if :. feasibility constraint : r(u)-r(v) w(e) for every edge e :U V 2. critical path constraint : r(u)-r(v) W(U,V)- for all vertices U,V in G such that (U,V)>c. There is a feasible retiming solution r such that Φ(Gr) c. VLSI-SP--2

22 Example with c=3 (/3) G G () () () () Step : t max =2, n=, M=t max n=8 Step 2: As G shows. Step 3: S UV Step : W(U,V) 2 3 (U,V) VLSI-SP--22

23 Example with c=3 (2/3) Step 5: Constraints Feasibility constraint: r()-r(3) r()-r() 2 r-r() r(3)-r r()-r Critical path constraint: r()-r r-r(3) r-r() 2 r(3)-r() r(3)-r() 2 r()-r() r()-r(3) Step 6: Constraint Graph VLSI-SP--23

24 Example with c=3 (3/3) Step 7: Using either Bellman-Ford algorithm or Floyd-Warshall algorithm, the retiming values for each node are calculated as r()=r=r(3)=r()= Step 8: Retimed FG can be obtained as () () VLSI-SP--2

25 Example with c=2 (/2) Feasibility constraint: r()-r(3) r()-r() 2 r-r() r(3)-r r()-r Critical path constraint: r()-r() r-r(3) r-r() 2 r(3)-r() r(3)-r - r(3)-r() 2 r()-r() r()-r - r()-r(3) Constraint Graph VLSI-SP--25

26 Example with c=2 (2/2) Using either Bellman-Ford algorithm or Floyd- Warshall algorithm, the retiming values for each node are calculated as r()=-, r= j+ r()=, r= r(3)=-, r()=- r(3)=, r()= Retimed FG can be obtained as () () VLSI-SP--26

27 Conclusion Reduction of clock period, number of registers, and power consumption by retiming for synchronous systems Shortest path algorithms can be used to obtain a retiming solution if one exists. Retiming can also be used as a preprocessing step for folding and for computation of round-off noise as discussed in Chap 6 and, respectively. VLSI-SP--27

28 Supplement Part The Shortest Path Algorithm VLSI igital Signal Processing Systems

29 Shortest Path Algorithms Length : sum of weights Negative cycle : when sum of lengths is negative ex : cycle 2 2 S UV : the shortest path from the node U to the node V. The Bellman-Ford algorithm The Floyd-Warshall algorithm VLSI-SP--29

30 The Bellman-Ford algorithm Single-point shortest path algorithm r () (U)= For k= to n If k U r () (k)=w(u e k) For k= to n-2 For V= to n r (k+) (V)=r (k) (V) For W= to n If r (k+) (V)> r (k) (W)+w(W e V) r (k+) (V)= r (k) (W)+w(W e V) For V= to n For W= to n If r (n-) (V)>r (n-) (W)+w(W e V) return FALSE and exit return TRUE and exit VLSI-SP--3

31 Example U=2 ( node 2 ) r (k) (V) k= k=2 k=3 V= 3 3 V=2 V=3 V= r (3) (V) is the shortest path from node 2 to node V for V=,2,3, VLSI-SP--3

32 The Floyd-Warshall algorithm All-points shortest path algorithm For V= to n For U= to n r () (U,V)=w(U e V) For k= to n For V= to n For U= to n r (k+) (U,V)=r (k) (U,V) If r (k+) (U,V)> r (k) (U,k)+r (k) (k,v) r (k+) (U,V)= r (k) (U,k)+r (k) (k,v) For k= to n For U= to n If r (k) (U,U)< return FALSE and exit return TRUE and exit VLSI-SP--32

33 Example R () -3 R R (3) R () R (5) R (5) (U,V) is the shortest path from the node U to the node V. VLSI-SP--33