Implementing JTAG Testing with MPEG2Lynx
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- Emory Atkins
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1 Implementing JTAG Testing with MPEG2Lynx Allison Hicks IEEE 1394 Peripherals Applications Abstract This application brief describes what is needed to implement JTAG Testability (IEEE JTAG standard) on the MPEG2Lynx (TSB12LV41) 1394 Link Layer controller. The MPEG2Lynx implements the three required commands for IEEE JTAG compatibility: r EXTEST r BYPASS r SAMPLE/PRELOAD The MPEG2Lynx is an IEEE compliant link layer controller. It has large internal FIFOs that are also useful for transmitting/receiving large asynchronous packets, large standard isochronous packets, and MPEG2 formatted isochronous packets. The MPEG2Lynx formats MPEG2 data over the 1394 serial bus according to the IEC61883 standard. Digital TV manufacturers, DVHS, DVD, and other digital media end equipment manufacturers will find that the JTAG Testability of the MPEG2Lynx makes the system testing process easier. Contents Abstract... 1 Introduction... 2 Appendix A. BSDL File... 2 Digital Signal Processing Solutions November 1998
2 Introduction This application brief explains how to implement JTAG testing with MPEG2Lynx. A previous working knowledge of JTAG testability is assumed. Please reference the IEEE JTAG Testability Primer (Literature Number SSYA002C) for more information on JTAG testability. Appendix A contains the boundary scan chain order. It is described in the standard BSDL (Boundary Scan Description) format. The MPEG2Lynx (TSB12LV41) supports the three required IEEE (JTAG) commands: EXTEST, BYPASS, and SAMPLE/PRELOAD. Because of technology limitations, the internal pull-ups to implement these commands are not supplied. To implement JTAG, all JTAG signals (including TDI, TDO, and TMS) should be tied high through a pull-up resistor. A value of 10K Ohms for the pull-up resistor is nominal. If JTAG is not implemented, the only requirement of the JTAG port is to not allow the pins to float. Because the TRST (JTAG Reset) should be tied low, we recommend that all JTAG pins be pulled low. The only requirement for proper initialization of the device is that the JTAG TAP (Test Access Port) be initialized prior to deasserting the chip reset (RESETZ). There are two ways to initialize the TAP controller: r Assert TRST (Test Reset) for 100 ns during chip reset. r Have TMS (Test Mode Select) in the high state and TCK (Test Clock)* running for at least five clock cycles (see the following note). NOTE: The maximum TCK (Test Clock) frequency is 4MHz. One of these options must be performed before the end of chip reset for the device to be initialized properly. Appendix A. BSDL File Appendix A contains the Boundary-Scan Description Language (BSDL) file specifically designed for the MPEG2Lynx (TSB12LV41). **************************************************************************** * BSDL file for design MPEG2Lynx (TSB12LV41) Note: 1) Technical details such as max. TCK frequency may be subject of change in future releases **************************************************************************** * entity TSB12LV41 is Implementing JTAG Testing with MPEG2Lynx 2
3 This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP: string:= "TQFP100"); This section declares all the ports in the design. port ( BCLK : in bit; BDICLK : in bit; BDIEN : in bit; BDOCLK : in bit; BDOEN : in bit; MCADR0 : in bit; MCADR1 : in bit; MCADR2 : in bit; MCADR3 : in bit; MCADR4 : in bit; MCADR5 : in bit; MCADR6 : in bit; MCADR7 : in bit; MCADR8 : in bit; MCCS_Z : in bit; MCCTL0 : in bit; MCCTL1 : in bit; MCSEL0 : in bit; MCSEL1 : in bit; RESET_Z : in bit; SCANCLKEN : in bit; SCLK : in bit; SE : in bit; TCK : in bit; TDI : in bit; TMS : in bit; TRST : in bit; BDI0 : inout bit; BDI1 : inout bit; BDI2 : inout bit; BDI3 : inout bit; BDI4 : inout bit; BDI5 : inout bit; BDI6 : inout bit; BDI7 : inout bit; BDIF0 : inout bit; BDIF1 : inout bit; BDIF2 : inout bit; CONTENDER : inout bit; CTL0 : inout bit; CTL1 : inout bit; D0 : inout bit; D1 : inout bit; D2 : inout bit; D3 : inout bit; MCAD0 : inout bit; MCAD1 : inout bit; MCAD10 : inout bit; MCAD11 : inout bit; MCAD12 : inout bit; MCAD13 : inout bit; MCAD14 : inout bit; MCAD15 : inout bit; MCAD2 : inout bit; Implementing JTAG Testing with MPEG2Lynx 3
4 ); MCAD3 : inout bit; MCAD4 : inout bit; MCAD5 : inout bit; MCAD6 : inout bit; MCAD7 : inout bit; MCAD8 : inout bit; MCAD9 : inout bit; STAT1 : inout bit; BDO0 : out bit; BDO1 : out bit; BDO2 : out bit; BDO3 : out bit; BDO4 : out bit; BDO5 : out bit; BDO6 : out bit; BDO7 : out bit; BDOF0 : out bit; BDOF1 : out bit; BDOF2 : out bit; INT_Z : out bit; LREQ : out bit; RDY : out bit; STAT0 : out bit; STAT2 : out bit; STAT3 : out bit; TDO : out bit; VDD : linkage bit_vector (1 to 8); VDD5V : linkage bit_vector (1 to 4); VSS : linkage bit_vector (1 to 8) use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of TSB12LV41: entity is "STD_1149_1_1994"; attribute PIN_MAP of TSB12LV41: entity is PHYSICAL_PIN_MAP; This section specifies the pin map for each port. This information is extracted from the port-to-pin map file that was read in using the "read_pin_map" command. constant TQFP100: PIN_MAP_STRING := "BCLK : 66," & "BDICLK : 91," & "BDIEN : 93," & "BDOCLK : 16," & "BDOEN : 49," & "MCADR0 : 50," & "MCADR1 : 51," & "MCADR2 : 52," & "MCADR3 : 53," & "MCADR4 : 54," & "MCADR5 : 55," & "MCADR6 : 56," & "MCADR7 : 58," & "MCADR8 : 59," & "MCCS_Z : 86," & "MCCTL0 : 82," & "MCCTL1 : 83," & "MCSEL0 : 84," & Implementing JTAG Testing with MPEG2Lynx 4
5 "MCSEL1 : 85," & "RESET_Z : 96," & "SCANCLKEN : 94," & "SCLK : 42," & "SE : 95," & "TCK : 14," & "TDI : 13," & "TMS : 12," & "TRST : 33," & "BDI0 : 1," & "BDI1 : 2," & "BDI2 : 3," & "BDI3 : 4," & "BDI4 : 6," & "BDI5 : 7," & "BDI6 : 8," & "BDI7 : 9," & "BDIF0 : 98," & "BDIF1 : 99," & "BDIF2 : 100," & "CONTENDER : 11," & "CTL0 : 40," & "CTL1 : 39," & "D0 : 38," & "D1 : 37," & "D2 : 36," & "D3 : 35," & "MCAD0 : 80," & "MCAD1 : 78," & "MCAD10 : 75," & "MCAD11 : 73," & "MCAD12 : 70," & "MCAD13 : 68," & "MCAD14 : 63," & "MCAD15 : 61," & "MCAD2 : 76," & "MCAD3 : 74," & "MCAD4 : 71," & "MCAD5 : 69," & "MCAD6 : 64," & "MCAD7 : 62," & "MCAD8 : 79," & "MCAD9 : 77," & "STAT1 : 29," & "BDO0 : 19," & "BDO1 : 20," & "BDO2 : 21," & "BDO3 : 22," & "BDO4 : 24," & "BDO5 : 25," & "BDO6 : 26," & "BDO7 : 27," & "BDOF0 : 45," & "BDOF1 : 46," & "BDOF2 : 47," & "INT_Z : 89," & "LREQ : 44," & "RDY : 88," & "STAT0 : 28," & "STAT2 : 30," & "STAT3 : 31," & Implementing JTAG Testing with MPEG2Lynx 5
6 "TDO : 18," & "VDD : (5, 17, 32, 43, 57, 67, 81, 92)," & "VDD5V : (15, 41, 65, 90)," & "VSS : (10, 23, 34, 48, 60, 72, 87, 97)"; This section specifies the TAP ports. For the TAP TCK port, the parameters in the brackets are: First Field : Maximum TCK frequency. Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of TCK : signal is ( e+06, BOTH); attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_RESET of TRST: signal is true; Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of TSB12LV41: entity is 2; Specifies the boundary-scan instructions implemented in the design and their opcodes. attribute INSTRUCTION_OPCODE of TSB12LV41: entity is "BYPASS (11)," & "EXTEST (00)," & "SAMPLE (01)"; Specifies the bit pattern that is loaded into the instruction register when the TAP controller passes through the Capture-IR state. The standard mandates that the two LSBs must be "01". The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of TSB12LV41: entity is "01"; This section specifies the test data register placed between TDI and TDO for each implemented instruction. attribute REGISTER_ACCESS of TSB12LV41: entity is "BYPASS (BYPASS)," & "BOUNDARY (EXTEST, SAMPLE)"; Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of TSB12LV41: entity is 126; The following list specifies the characteristics of each cell in the boundary scan register from TDI to TDO. The following is a description of the label fields: num : Is the cell number. cell : Is the cell type as defined by the standard. port : Is the design port name. Control cells do not have a port name. function: Is the function of the cell as defined by the standard. Is one of input, output2, output3, bidir, control or controlr. safe : Specifies the value that the BSR cell should be loaded with for safe operation when the software might otherwise choose a random value. ccell : The control cell number. Specifies the control cell that drives the output enable for this port. Implementing JTAG Testing with MPEG2Lynx 6
7 disval : Specifies the value that is loaded into the control cell to disable the output enable for the corresponding port. rslt : Resulting state. Shows the state of the driver when it is disabled. attribute BOUNDARY_REGISTER of TSB12LV41: entity is num cell port function safe [ccell disval rslt] "125 (BC_1, BDI0, input, X), " & "124 (BC_1, BDI0, output3, X, 15, 1, Z), " & "123 (BC_1, BDI1, input, X), " & "122 (BC_1, BDI1, output3, X, 15, 1, Z), " & "121 (BC_1, BDI2, input, X), " & "120 (BC_1, BDI2, output3, X, 15, 1, Z), " & "119 (BC_1, BDI3, input, X), " & "118 (BC_1, BDI3, output3, X, 15, 1, Z), " & "117 (BC_1, BDI4, input, X), " & "116 (BC_1, BDI4, output3, X, 15, 1, Z), " & "115 (BC_1, BDI5, input, X), " & "114 (BC_1, BDI5, output3, X, 15, 1, Z), " & "113 (BC_1, BDI6, input, X), " & "112 (BC_1, BDI6, output3, X, 15, 1, Z), " & "111 (BC_1, BDI7, input, X), " & "110 (BC_1, BDI7, output3, X, 15, 1, Z), " & "109 (BC_1, CONTENDER, input, X), " & "108 (BC_1, CONTENDER, output3, X, 13, 1, Z), " & "107 (BC_4, BDOCLK, observe_only, X), " & "106 (BC_1, BDO0, output3, X, 14, 1, Z), " & "105 (BC_1, BDO1, output3, X, 14, 1, Z), " & "104 (BC_1, BDO2, output3, X, 14, 1, Z), " & "103 (BC_1, BDO3, output3, X, 14, 1, Z), " & "102 (BC_1, BDO4, output3, X, 14, 1, Z), " & "101 (BC_1, BDO5, output3, X, 14, 1, Z), " & "100 (BC_1, BDO6, output3, X, 14, 1, Z), " & "99 (BC_1, BDO7, output3, X, 14, 1, Z), " & "98 (BC_1, STAT0, output2, X), " & "97 (BC_1, STAT1, input, X), " & "96 (BC_1, STAT1, output3, X, 1, 1, Z), " & "95 (BC_1, STAT2, output3, X, 0, 1, Z), " & "94 (BC_1, STAT3, output2, X), " & "93 (BC_1, SE, input, X), " & "92 (BC_1, D3, input, X), " & "91 (BC_1, D3, output3, X, 7, 1, Z), " & "90 (BC_1, D2, input, X), " & "89 (BC_1, D2, output3, X, 8, 1, Z), " & "88 (BC_1, D1, input, X), " & "87 (BC_1, D1, output3, X, 9, 1, Z), " & "86 (BC_1, D0, input, X), " & "85 (BC_1, D0, output3, X, 10, 1, Z), " & "84 (BC_1, CTL1, input, X), " & "83 (BC_1, CTL1, output3, X, 11, 1, Z), " & "82 (BC_1, CTL0, input, X), " & "81 (BC_1, CTL0, output3, X, 12, 1, Z), " & "80 (BC_4, SCLK, observe_only, X), " & "79 (BC_1, LREQ, output3, X, 5, 1, Z), " & "78 (BC_1, BDOF0, output3, X, 14, 1, Z), " & "77 (BC_1, BDOF1, output3, X, 14, 1, Z), " & "76 (BC_1, BDOF2, output3, X, 14, 1, Z), " & "75 (BC_1, BDOEN, input, X), " & Implementing JTAG Testing with MPEG2Lynx 7
8 "74 (BC_1, MCADR0, input, X), " & "73 (BC_1, MCADR1, input, X), " & "72 (BC_1, MCADR2, input, X), " & "71 (BC_1, MCADR3, input, X), " & "70 (BC_1, MCADR4, input, X), " & "69 (BC_1, MCADR5, input, X), " & "68 (BC_1, MCADR6, input, X), " & "67 (BC_1, MCADR7, input, X), " & "66 (BC_1, MCADR8, input, X), " & "65 (BC_1, MCAD15, input, X), " & "64 (BC_1, MCAD15, output3, X, 4, 1, Z), " & "63 (BC_1, MCAD7, input, X), " & "62 (BC_1, MCAD7, output3, X, 4, 1, Z), " & "61 (BC_1, MCAD14, input, X), " & "60 (BC_1, MCAD14, output3, X, 4, 1, Z), " & "59 (BC_1, MCAD6, input, X), " & "58 (BC_1, MCAD6, output3, X, 4, 1, Z), " & "57 (BC_4, BCLK, observe_only, X), " & "56 (BC_1, MCAD13, input, X), " & "55 (BC_1, MCAD13, output3, X, 4, 1, Z), " & "54 (BC_1, MCAD5, input, X), " & "53 (BC_1, MCAD5, output3, X, 4, 1, Z), " & "52 (BC_1, MCAD12, input, X), " & "51 (BC_1, MCAD12, output3, X, 4, 1, Z), " & "50 (BC_1, MCAD4, input, X), " & "49 (BC_1, MCAD4, output3, X, 4, 1, Z), " & "48 (BC_1, MCAD11, input, X), " & "47 (BC_1, MCAD11, output3, X, 4, 1, Z), " & "46 (BC_1, MCAD3, input, X), " & "45 (BC_1, MCAD3, output3, X, 4, 1, Z), " & "44 (BC_1, MCAD10, input, X), " & "43 (BC_1, MCAD10, output3, X, 4, 1, Z), " & "42 (BC_1, MCAD2, input, X), " & "41 (BC_1, MCAD2, output3, X, 4, 1, Z), " & "40 (BC_1, MCAD9, input, X), " & "39 (BC_1, MCAD9, output3, X, 4, 1, Z), " & "38 (BC_1, MCAD1, input, X), " & "37 (BC_1, MCAD1, output3, X, 4, 1, Z), " & "36 (BC_1, MCAD8, input, X), " & "35 (BC_1, MCAD8, output3, X, 4, 1, Z), " & "34 (BC_1, MCAD0, input, X), " & "33 (BC_1, MCAD0, output3, X, 4, 1, Z), " & "32 (BC_1, MCCTL0, input, X), " & "31 (BC_1, MCCTL1, input, X), " & "30 (BC_1, MCSEL0, input, X), " & "29 (BC_1, MCSEL1, input, X), " & "28 (BC_1, MCCS_Z, input, X), " & "27 (BC_1, RDY, output3, X, 2, 1, Z), " & "26 (BC_1, INT_Z, output3, X, 6, 1, Z), " & "25 (BC_4, BDICLK, observe_only, X), " & "24 (BC_1, BDIEN, input, X), " & "23 (BC_1, SCANCLKEN, input, X), " & "22 (BC_1, RESET_Z, input, X), " & "21 (BC_1, BDIF0, input, X), " & "20 (BC_1, BDIF0, output3, X, 15, 1, Z), " & "19 (BC_1, BDIF1, input, X), " & "18 (BC_1, BDIF1, output3, X, 15, 1, Z), " & "17 (BC_1, BDIF2, input, X), " & "16 (BC_1, BDIF2, output3, X, 15, 1, Z), " & "15 (BC_1, *, controlr, 1), " & "14 (BC_1, *, controlr, 1), " & Implementing JTAG Testing with MPEG2Lynx 8
9 "13 (BC_1, *, controlr, 1), " & "12 (BC_1, *, controlr, 1), " & "11 (BC_1, *, controlr, 1), " & "10 (BC_1, *, controlr, 1), " & "9 (BC_1, *, controlr, 1), " & "8 (BC_1, *, controlr, 1), " & "7 (BC_1, *, controlr, 1), " & "6 (BC_1, *, controlr, 1), " & "5 (BC_1, *, controlr, 1), " & "4 (BC_1, *, controlr, 1), " & "3 (BC_0, *, internal, X), " & "2 (BC_1, *, controlr, 1), " & "1 (BC_1, *, controlr, 1), " & "0 (BC_1, *, controlr, 1) "; end TSB12LV41; INTERNET Register with TI&ME to build custom information pages and receive new product updates automatically via . TI Semiconductor Home Page TI Distributors PRODUCT INFORMATION CENTERS US TMS320 Hotline (281) Fax (281) BBS (281) Americas Phone +1(972) Fax +1(972) Europe, Middle East, and Africa Phone Deutsch +49-(0) English +44-(0) Francais +33-(0) Italiano +33-(0) Fax +33-(0) Japan Phone International Domestic Fax International Domestic Asia Phone International Domestic Australia Asia (continued) China Hong Kong India Indonesia Korea Malaysia New Zealand Philippines Singapore Taiwan Thailand Implementing JTAG Testing with MPEG2Lynx 9
10 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty, or endorsement thereof. Copyright 1998, Texas Instruments Incorporated TI is a trademark of Texas Instruments Incorporated. Other brands and names are the property of their respective owners. Implementing JTAG Testing with MPEG2Lynx 10
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