Optimization of Modern Memory

Transcription

1 System Design, Verificationand and Optimization of Modern Memory Interfaces (DDR3) Santa Clara, Aug 23 rd 2011 Robert Myoung Sr. Application Engineer 1

2 Agenda Introduction ECAD Geometry Translation SI/PI DDR3 Channel Extraction Design Automation and Schematic Creation DDR3 Transient Simulation Results 2

3 ANSYS for DDR3 Designs Problem Need for automated and accurate extraction of channel components and system verification for meeting strict DDR3 electrical standards and design specifications Solution Automatic physical extraction and system compliance verification for memory interface design using ANSYS Electromagnetics tools Result Detailed and accurate system simulation enables engineers to explorer pre and post layout verification for optimal memory interface design. 3 Pictures source:

4 DDR2/3 Overview DDR3 speed is MBps which is 2x DDR2 Tighter noise margins and need for less SSN DDR3 uses less voltage (1.5V from 1.2V) DDR3 has less SSN than DDR2 due to its fly by y termination 4 Information source: JEDEC 2007 DDR Workshop and HP DDR3 Application Note

5 DDR2/3 Timing Specifications Setup Margin & Hold Margin It s included timing margin and noise (voltage) margin DQ Jitter DQS V REF V IH(AC) Setup Time Hold Time V IH(DC) V IL(AC) V IL(DC) Setup Margin Hold Margin 5 DIMMs requiretighter specifications than down device memory, in the case of applying and input voltage value, DIMMs require both an AC & DC value. Down Device DDR2/3 memory generally requires only the DC input voltage value.

6 ANSYS Solution Electrical DesignerSI, SIwave, HFSS Mechanical Fluid Dynamic 6 Images and models courtesy of the Xilinx, Micron Technology, TE Connectivity.

7 Virtual System Prototyping Layout 3D CAD Virtual Prototype Electromagnetic Extraction Mechanical and Thermal Vendor Specific Driver/Receiver Models Vendor Specific VRM Models Electronics Virtual System Virtual Compliance 7

8 Virtual System Prototyping Layout Virtual Prototype 3D CAD 8

9 Xilinx ML605 Board 9 Courtesy of:

10 Layout Translation from Cadence Allegro 10 Courtesy of:

11 SODIMM board, Connector and Main Board 11 Courtesy of: Xilinx and

12 Virtual System Prototyping Layout 3D CAD Virtual Prototype Electromagnetic Extraction Mechanical and Thermal 12

13 Complex Multiple PCB Power Domains 13 Power Sources and Sinks 1.5V Memory and FPGA 1V8 2V5 2V5 FPGA 3V3 5V 12_P 12_P_IN Courtesy of:

14 SIwave DC IR solver SIwave has the ability to examine the full current path as well as each individual segment. Current/voltage/power levels set at each stage Power Supply Stability Capacitor Library Browser, PI Advisor Hot spots/bottlenecks that may cause reliability and excessive heating can be detected via current density and DC simulation results can be coupled to a thermal / airflow ifl simulation using ANSYS IcePak TM. Bidirectio onal Thermal Link SIwave Bi directional Coupling Power and Thermal Mapping Icepak 14

15 SIwave Design DDR3 1.5V Power Delivery Network with real VRM model 15V 1.5V 1.5V +/- 5% VRM 15 Courtesy of:

16 SIwave SYZ Parameter extraction Extraction example of mixed mode s parameters Power Rail and Signal Nets, DC and AC Vertex V6 to DDR3 SODIMM Memory ML605 PCB DDR3 204PIN SODIMM Connector Power/Ground separate referencing Some of thesignalreference to Power plane DDR3 204 SODIMM PCB Real VRM model 16

17 Signal Integrity S parameter Extraction & Analysis Insertion/Return Loss parameters Power/Ground Isolation effect in Frequency and Time Domain Main board with connector Main board only Main board with connector and SODIMM board 17

18 Virtual System Prototyping Layout 3D CAD Virtual Prototype Electromagnetic Extraction Mechanical and Thermal Vendor Specific Driver/Receiver Models Vendor Specific VRM Models Electronics 18

19 VRM(PTD08A010W) model from TI Fusion Digital Power designer from TI Generate real VRM model 19 Information source:

20 DDR3 PDN model DDR3 1.5V Power Delivery Network with real VRM model Multiple probing points displayed Top and bottom DDR3 package, FPGA and VRM U8 U18 20 Courtesy of: VRM

21 VRM Current Signature Profile Probe Point : VRM Output(Blue), FPGA Power(Brown) and DDR3 (Red). 1. VRM Output 2. DDR3 package 21

22 Virtual System Prototyping Layout 3D CAD Virtual Prototype Electromagnetic Extraction Mechanical and Thermal Vendor Specific Driver/Receiver Models Vendor Specific VRM Models Electronics Virtual System Virtual Compliance 22

23 System Level Signal and Power integrity Analysis While extraction and analysis are important steps of a design methodology, a system level analysis gives the engineer the ability to best balance and trade off design choices for the given performance and cost requirements. generally there are multiple lanes of serial data running side by side; these can CROSSTALK with each other. Tx + Tx + - Tx + Tx Rcv + + Rcv Rcv- + -Rcv Design Automation is essential; Automatic Schematic generation and Simulation Data analysis compare to Standard Deal with Various different data set. Power/Ground Bounce and Coupling to Signal Nets

24 Network Data Explorer Network Data Explorer (nd Explorer in Designer) 3 Stage Dynamic Link Design 36port model with mixed reference impedance Supports Touchstone 2.0 Bandwidth : DC to 20GHz Spice model Passivity and Causality enforcement 36port model of DDR3 channel 24

25 Automatic Schematic Creation SSN analysis DQS Zero Crossing and Eye Margins 25

26 DDR3 Channel Eye Diagrams Connector Effects on DQS line Zero Crossing Without Connector With Connector 26

27 DDR3 Channel Eye Diagrams and Regular Plot 27

28 DDR3 Channel Derating tables, slew rate 28

29 SODIMM board, Connector and Main Board SIwave, DesignerSI HFSS SIwave, DesignerSI and HFSS HFSS ANSYS, Inc. August 25, 2011

30 ANSYS Tools Overview DDR3 Solution for Electrical Simulations ECAD Geometry Translation ECAD Translators and AnsoftLinks SI/PI DDR3 Channel Extraction HFSS, SIwave Design Automation and Schematic Creation DesignerSI and SIwave DDR3 Transient Simulation Results DesignerSI, UDO s 30

31 Thank You 31