Apache s Power Noise Simulation Technologies
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1 Enabling Power Efficient i Designs Apache s Power Noise Simulation Technologies 1 Aveek Sarkar VP of Support Apache Design Inc, A wholly owned subsidiary of ANSYS
2 Trends in Today s Electronic Designs Low-power Multi-VDD Power Gates Clock Gating Integration IP, memories Mixed signal Stacked die High-speed GHz+ Multi-Core DDR3+ Handset Mobile Processors ~ 2.5GHz+ Data Center Processors ~ 3.5GHz+ 2
3 Trends in Today s Design Technologies I/O Perform ance Package De esign Des sign Complexit ty Wire Reliability 3
4 Impact of Increasing Design Integration Switching Power Standby Performance Noise Coupling Functionality ESD Reliability EM 4
5 Apache s Focus Areas Power Budgeting Low power need is ubiquitous Battery life Energy efficiency 5 Energy costs Interference Power Delivery Integrity Power--Induced Noise Power Right place, right time, right amount Unintentional electrical interference 2011 ANSYS, Inc. August 25, 2011
6 Apache s Power Flow Architectural Level Simulation PowerArtist Early power simulation Power reduction IC Physical Design Simulation RedHawk/Totem Design prototyping Sign off validation System Integration Simulation Sentinel / SiWave SI, PI, EMI, Thermal Co verification and optimization 6
7 Simulation Driven Power Budgeting Get maximum savings for the acceptable tbl area impact Power savings saturate here! Maximum acceptable area impact? Power vs. Area trade-off: Min area impact for ~Max savings Power Savings Area Impact 377k instances, 350MHz, 90nm 7
8 Simulation Driven Power Budgeting RTL RTL stage power analysis Design Early prediction and design prototyping Power Budgeting Track power through design process Physical Design System Integration ti Consistency in power budgeting 8
9 Simulation Driven Power Bug Isolation Logic Register r Multi core (4) design Not all four cores operational at any one time Logic Logic Logic Register Register Register Assuming only first core is operational, rest are shut off Typically clock is shut off for non active blocks But data continues to come in Logic continues to burn power PowerArtist Identified this Power Bug Reducing Power by 22% 9
10 Power Noise Integrity Impact of Low Power Techniques MultipleVoltage Islands 100+ VDD/VSS domains No re distribution or plane sharing Power Gating Disrupts continuity of PDN Over design = large cost On chip Voltage Regulators (LDO) Non ideal voltage supply Stability and noise immunity 10
11 Power Noise Integrity Impact of Technology Migration ITRS, Trends in technology scaling Higher drive strength devices di/dt Source: Mezhiba et al. Scaling Trends of On Chip Power Distribution Noise Higher impact of inductive noise Ldi/dt But noise margin continues to reduce Reduced F MAX Functionality failures Over design requirements 11
12 RedHawk Power Noise Analysis Flow Design Import CAD design flow independent Operate on industry standard formats: PG Extraction Only solution for on die L extraction and simulation Silicon validated down to 28nm and beyond Simulation Pico second resolution, native multi domain Best in class performance Root Cause Enable automatic and user guided debug Identification Interactive what if and incremental simulation Chip Power Model Single step model creation out of RedHawk Multi domain, distributed and coupled 12
13 RedHawk Power Noise Analysis Coverage Core Noise Core I/O Core Analog noise source guard ring PLL victim Scenario 3 Scenario 2 Scenario 1 Multi core switching Power gate turn on/off I/O,core SSO Irregular bump, package High speed digital Insufficient isolation 13
14 Addressing Customer s Market Needs Exploding design and mask costs Accurate pre silicon power delivery simulations are an essential tool to predict the impacts of tester and system power delivery performance on silicon frequency and reliability. Dr. M. Pant, Lead technologist and power delivery architect, Xeon and Itanium server products GSA Global Electronic System Design Considerations to Meet Emerging Market Needs 14
15 Apache s Power Tools Architecture IP SoC Package PCB Power Budgeting Power Delivery Integrity Power Induced Noise 15
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