GCU ARCHITECTURE PROPOSAL

Transcription

1 GCU ARCHITECTURE PROPOSAL M. Bellato, R. Brugnera, F. Dal Corso, S. Dusini, A. Garfagnini, R. Isocrate, I. Lippi, G. Meng, D. Pedretti INFN and University of Padova

2 GCU ARCHITECTURE PROPOSAL LCU DCS VD HV GCU ADU ETHERNET SWITCH DAQ POWER ~ GCU should : CLOCK And TRIGGER CLK TRIGGER Store ADU data waiting for a trigger Send trigger request to LCU Receive the trigger validations Send data to DAQ Provide power and slow control to HV module

3 Data and trigger processing scheme JUNO PMT 62.5 MHz Clock TRIGGER REQUESTS ADCs (ASIC) Trigger primitive generator Trigger matching 48 bit TIMESTAMP 24 bit EV COUNTER Digital pipeline Readout Window 100Mb/s Ethernet L2 Trigger Accept Backpressure DATA READOUT ASYNC RESETS Processing element Derandomizer FAST CONTROLS PARAMETERS Backpressure MULTIPLEXED READOUT Processing Element Time Tag TO DAQ FARM Event Tag FE Identifier

4 Data synchronization of distributed readout

5 Asynchronous data link IPBUS IPbus is a simple, IP-based control protocol Originally created by Jeremy Mans, et al in 2009/2010 Now all s/w and f/w development is being done by a UK collaboration University of Bristol and Imperial College London Designed for controlling CMS trigger and readout h/w Control standard for μtca or TCA-based hardware over Gigabit Ethernet Protocol describes basic transactions needed to control h/w Read/write, nonincrementing read/write, etc, etc. UDP is the recommended transport implementation Easiest to implement in firmware Uses relatively few FPGA resources IPBUS is very interesting for JUNO detector, can be use for asynchronous data link to GCU for DAQ and slow control using as transport layer commercial fast Ethernet switches, giving to software developers directly visibility to GCUs FPGAs registers

6 Clock and GCU time stamps synchronization LCU CGU1 GCU2 GCUn RTT1 RTT2 GCU1 waits GTC value GCU2 waits GTC value OFS1 OFS2

7 Alternative (under evaluation) Clock and GCU time stamps synchronization via synchronous Ethernet (IEEE1588) IEEE 1588 is a protocol designed to synchronize real-time clocks in the nodes of a distributed system that communicate using a network the big advantage to be exploited is that the same infrastructure can be used for both data transmission and synchronization NETWORK We can evaluate to use of the Texas Instrument DP83640 physical layer Synchronous Ethernet at 100 Mb/s, a feature unique to the DP83640, enables very accurate synchronization between IEEE 1588 Precision Time Protocol (PTP) systems connected via Ethernet. Using this feature, it is possible to maintain sub-nanosecond master to slave synchronization precision in PTP applications operating within required network topological constraints. It is also possible to generate a slave node clock output which is locked and aligned to the Master PTP clock.

8 Ethernet POE Switch system 48Vdc POE PDS ETHERNET PHY LAYER ASYNCRONOUS 100Mbit Ethernet GCU block diagram IPBUS CORE FPGA SLOW CONTROL ADC DECODE OPTO ADC SPI bus ADU ANALOG FE HV REGS PWM ADC DAC VD Clock & Trigger cards LCU LOCAL CLOCK CABLE DRIVER CABLE EQUALIZER JITTER CLEANER 125Mbit data 62.5MHz clock TRG AND EVENT DISP TRIGGER ALG DDR CTL CORE BITSTREAM SELECTOR 20/28 bit 500MHz 64bit 400MHz BITSTREAM FLASH GOLDEN DDR RAM 2Gb CURRENT PMT

9 FPGA reprogramming and disaster recovering The 7 th JUNO collaboration meeting Xiamen January 2016 Production D[0..7] DONE D[0..7] MODE PINS Golden CE CEO CLK CCLK CSI_B EN_EXT_SEL RDWR_B OE/RESET INIT_B CF I/O REVISION_SEL BUSY PROG_B I/O 62.5MHz External clock Q POR reset

10 POE and Power distribution system Power over Ethernet or PoE is a system which pass electrical power along with data on Ethernet cabling. This allows a single cable to provide both data connection and electrical power to devices

11 POE and Power distribution system 48v to HV module BUCK REG +1.0v PICOR Active EMI Filter +48v Flyback 48v - 12v +12v BUCK REG BUCK REG +2.5v +1.8v Ethernet pairs BUCK REG +3.3v BUCK REG +1.5v BUCK REG +5v LDO? ADU

12 POE and Power distribution system Power over Ethernet Implementation on EDISON Board Noise measurement on 1.2 volt Power 50ohm AC coupled probe Istvan Novak, What's the Best Method for Probing a PDN? August 2012

13 Cable driver and equalizer evaluation The 62.5MHz Reference clock and the Trigger information are send to LCU system via ~80meters of UTP cable. We have done some measurements in order to evaluate if a cat5e UTP cable coupled by cable driver and equalizers could be reliable for JUNO applications. Tektronics DTG5274 Data and Timing generator Up to 2.7Gs/s Measurements setup 100mt UTP cable AGILENT DS691204A DSO 12GHz bandwith 40Gs/s DS30BA101 evaluation module Cable driver DC to Gs/s DS30EA101 evaluation module Cable equalizer DC to Gs/s

14 Cable driver and equalizer evaluation Brief description of choose cable driver and equalizer DS30BA101 evaluation module Cable driver DC to Gs/s DS30EA101 evaluation module Cable equalizer DC to Gs/s

15 Cable driver and equalizer evaluation Measurements: 62.5MHz Clock transmission, Jitter evaluation 125Mbit/s Data transmission PRBS-9 test pattern 62.5Mbit/s Data transmission Trigger information (125Mbit/s 1-2 Manchester encoding)

16 Cable driver and equalizer evaluation Measurements : 62.5MHz Clock transmission, Jitter evaluation 125Mbit/s Data transmission PRBS-9 test pattern 62.5Mbit/s Data transmission Trigger information (125Mbit/s 1-2 Manchester encoding)

17 Cable driver and equalizer evaluation Measurements : 62.5MHz Clock transmission, Jitter evaluation TIE 177ps pp / 20ps rms TIE 39ps pp / 3ps rms Jitter of received clock after 100mt of cat5e UTP cable (no shield) Jitter of received clock after 100mt of cat5e STP cable (shield) So! It is recommended to install shielded cables

18 Cable driver and equalizer evaluation Measurements : 62.5MHz Clock transmission, Jitter evaluation 62.5Mbit/s Data transmission PRBS pattern (125Mbit/s 1-2 Manchester encoding) 62.5Mbit/s Data transmission Trigger information (125Mbit/s 1-2 Manchester encoding)

19 The 7th JUNO collaboration meeting Xiamen January 2016 Cable driver and equalizer evaluation Measurements : 125Mbit/s Data transmission PRBS-9 test pattern Eye pattern received data with 100mt of cat5e UTP cable (no shield) Eye pattern received data with 100mt of cat5e STP cable (shield)

20 Cable driver and equalizer evaluation Measurements : 62.5MHz Clock transmission, Jitter evaluation 125Mbit/s Data transmission PRBS/9 test pattern 62.5Mbit/s Data transmission Trigger information (125Mbit/s 1-2 Manchester encoding)

21 Cable driver and equalizer evaluation Measurements : 62.5Mbit/s Data transmission Trigger information (125Mbit/s 1-2 Manchester encoding) Test pattern generated thinking at 10 samples of time over threshold of the input signal PMT signal Threshold Trigger signal (time over threshold) Transmitted pattern (Manchester encoded)

22 The 7th JUNO collaboration meeting Xiamen January 2016 Cable driver and equalizer evaluation Measurements : 62.5Mbit/s Data transmission Trigger information (125Mbit/s 1-2 Manchester encoding) Eye pattern received data with 100mt of cat5e UTP cable (no shield) Eye pattern received data with 100mt of cat5e STP cable (shield)

23 Cable driver and equalizer evaluation Measurements : 62.5MHz Clock transmission, Jitter evaluation 125Mbit/s Data transmission PRBS-9 test pattern 62.5Mbit/s Data transmission Trigger information (125Mbit/s 1-2 Manchester encoding) Further tests and measurements Repeat all the test with cable driver in all measurements Test including Ethernet 100Mbit traffic and POE supply on same cable Test using the FPGA (KC705 Xilinx Kintex FPGA evaluation board)

24 Cable driver and equalizer evaluation Conclusions : Cat5e cable is a good choice for reference clock and data transmission, it is preferable to install cat5e STP cable shielded. Further tests needed for evaluate data degradation when Ethernet traffic and POE are included in the same cable.

25 GCU Hardware (VHDL) evaluation Cable drivers and equalizers connected to FMC LPC adapter Xilinx KC705 Evaluation board Kintex ADC 500Msps Evaluation board connected to FMC HPC adapter 64bit DDR3 RAM Ethernet PHY layer

26 GCU Hardware (VHDL) evaluation KC705 block diagram

27 Ethernet POE Switch system 48Vdc POE PDS ETHERNET PHY LAYER ASYNCRONOUS 100Mbit Ethernet GCU block diagram IPBUS CORE FPGA SLOW CONTROL ADC DECODE OPTO ADC SPI bus ADU ANALOG FE HV REGS PWM ADC DAC VD Clock & Trigger cards LCU LOCAL CLOCK CABLE DRIVER CABLE EQUALIZER JITTER CLEANER 125Mbit data 62.5MHz clock TRG AND EVENT DISP TRIGGER ALG DDR CTL CORE BITSTREAM SELECTOR 20/28 bit 500MHz 64bit 400MHz BITSTREAM FLASH GOLDEN DDR RAM 2Gb CURRENT PMT

28 Ethernet POE Switch system 48Vdc POE PDS ETHERNET PHY LAYER ASYNCRONOUS ETHERNET PHY LAYER SYNCRONOUS 100Mbit Ethernet GCU prototype block diagram IPBUS CORE IPBUS CORE FPGA SLOW CONTROL ADC DECODE OPTO SPI bus HV REGS PWM ADC DAC VD Clock & Trigger cards LCU LOCAL CLOCK clock CABLE DRIVER CABLE EQUALIZER JITTER CLEANER 100Mbit Ethernet 125Mbit data 62.5MHz clock TRG AND EVENT DISP TRIGGER ALG DDR CTL CORE BITSTREAM SELECTOR 20/28 bit 500MHz 64bit 400MHz BITSTREAM FLASH GOLDEN FMC DDR RAM 2Gb CURRENT PMT

29 GCU ARCHITECTURE PROPOSAL THANK YOU