JESD204B Xilinx/IDT DAC1658D-53D interoperability Report
|
|
- Shawn Damon White
- 6 years ago
- Views:
Transcription
1 [Interoperability Report] Rev 0.4 Page 1 of 14 JESD204B Xilinx/IDT DAC1658D-53D interoperability Report
2 [Interoperability Report] Rev 0.4 Page 2 of 14 CONTENTS INTRODUCTION... 3 SCOPE... 3 HARDWARE... 3 XILINX KC705 EVAL BOARD... 3 IDT DAC1658D/DAC1653D HW EVAL BOARD... 3 XILINX IP CONFIGURATION... 4 INTEROPERABILITY TEST RESULTS... 5 COMPLIANCE TO JESD204B SPECIFICATION DOCUMENT HISTORY... 14
3 [Interoperability Report] Rev 0.4 Page 3 of 14 Introduction This document describes the method and tests to be carried out to test interoperability between the Xilinx(R) LogiCORE(TM) JESD204 IP and the IDT DAC1658D and DAC1653D. Scope Interoperability testing used existing hardware supporting JESD204B subclasses 0, 1 and 2. Line rates of 3.125G, 6.375G, 10G, and 12.5Gbps were tested. Hardware Xilinx KC705 Eval Board The Kintex -7 FPGA KC705 Evaluation Kit includes all the basic components of hardware, design tools, IP, and a preverified reference design for system designs that demand high-performance, serial connectivity and advanced memory interfacing. The included pre-verified reference designs and industry-standard FPGA Mezzanine Connectors (FMC) allow scaling and customization with daughter cards. IDT DAC1658D/DAC1653D HW Eval Board The board used is referenced as DAC1653D1G5-DB or DAC1658D1G5-DB.Its main characteristics are: One dual high-speed serial JESD204B DAC with four lanes input. Populated device can be DAC1658D1G5 or DAC1653D1G5; One (SAMTEC FMC) high density connector to interface with compatible carrier board; One USB to SPI master device. It can be bypassed and the demo board can be controlled from the carrier through the FMC connector; On-board voltage regulators for all devices on the board; Clock divider (by 1, 2, 4, 8 or 16) to drive carrier board clock input. The DAC1653D and the DAC1658D are high-speed high-performance 16-bit dual channel Digital-to-Analog Converters (DACs). The devices provide sample rates up to 2 Gsps with selectable 2X, 4X and 8X interpolation filters optimized for multi-carrier and broadband wireless transmitters. The DAC165xD integrates a JEDEC JESD204B compatible high-speed serial input data interface running up to 10 Gbps allowing dual channel input sampling at up to 1 Gsps over four differential lanes. There are two versions of the DAC165xD: Low common-mode output voltage (part identification DAC1653D) High common-mode output voltage (part identification DAC1658D) An optional on-chip digital modulator converts the complex I/Q pattern from baseband to IF. The mixer frequency is set by writing to the Serial Peripheral Interface (SPI) control registers associated with the on-chip 40-bit Numerically
4 [Interoperability Report] Rev 0.4 Page 4 of 14 Controlled Oscillator (NCO). This accurately places the IF carrier in the frequency domain. The 16-bit phase adjustment feature, the 12-bit digital gain and the 16-bit digital offset enable full control of the analog output signals. The DAC165xD is fully compatible with device subclass 0 and 1 of the JEDEC JESD204B standard, guaranteeing deterministic and repeatable interface latency using the differential SYSREF signal. The device also supports harmonic clocking to reduce system-level clock synthesis and distribution challenges. Multiple Device Synchronization (MDS) enables multiple DAC channels to be sample synchronous MDS and phase coherent to within one DAC clock period. MDS is ideal for LTE and LTE-A MIMO transceiver applications. The DAC165xD includes a 2, 4 or 8 divider to achieve the best possible noise performance at the analog outputs, allowing harmonic clocking through the system. Hardware Setup The KC705 is configured in its default state and powered using the supplied PSU. The USB JTAG is required for connection to the controlling PC. The DAC165xD1G5-DB HW evaluation board connects directly to the KC705 (HPC) FMC connector. A separate power supply is required for the DAC165xD. The USB cable is required to connect to the controlling PC. The frequency generator is connected to DAC board DAC_CK SMA connector. Reference clock to FPGA is supplied from the DAC board via FMC connector. To supply the correct frequency, S0, S1 and S2 jumpers have to be properly set to divide down by 2. As, example, if the DAC clock frequency is 1,2GHz, the FPGA reference clock is 600MHz and the data rate on the lanes will be 6Gbps. DAC must be set to operate in by 2 interpolation and use all the 4 lanes. Chipscope(TM) is continuously polling KC705 through the USB and so is doing IDT control software with the DAC board. Some access conflicts might arise. To overcome this situation, one should disable chipscope polling. Xilinx IP Configuration The Xilinx LogiCORE JESD204 IP Core supports JESD204A and JESD204B on Virtex(R)-6 and Kintex-7 devices. See the IP User Guide for details. The IP shall be configured for Kintex-7 devices only for interoperability testing. The Example design RTL will require modification in order to generate the correct control and data signals to complete interoperability testing.
5 [Interoperability Report] Rev 0.4 Page 5 of 14 Interoperability Test Results The following table details teh tests carried out and the results. Test Number Test Description Interoperable Notes 1 Sync request Test correct operation when sync~ is requested by the receiver. Subclass 0 and 2. The receiver should request sync following reset. It also possible to force sync~ low when the FPGA is the receiver to re-request sync. Subclass 1. The receiver should request sync a number of frame clock cycles following the rising edge of SYSREF. It also possible to force sync~ low when the FPGA is the receiver to re-request sync. 1.1 Check K28.5 transmitted by transmitter in response to sync request. 1.2 Check ILA or Data follows K28.5 when sync~ goes high. 1.3 Check ILA or Data following K28.5 is aligned to frame clock. The receiver was seen to drive SYNC~ low after a reset. K28.5 characters were seen at the receiver in response to a sync request. The ILA was seen after SYNC~ goes high. 2 Initialization Test the link initializes correctly from reset and power on. 2.1 Check Alignment correct at receiver by inspecting sync~ de-assertion. The link was seen to initialize correctly. Alignment was seen to be correct 2.2 Check ILA transmitted and received following K28.5 when ILA supported. Duplicate of Check data frames transmitted and received following K28.5 when ILA disabled. When ILA is disabled at both side of the link, valid data are still available at the
6 [Interoperability Report] Rev 0.4 Page 6 of 14 output. 3 Deterministic Latency (Device Subclass 1) Test data is passed across the link with a deterministic latency in respect to SYSREF. 3.1 SYSREF Generation and sampling. The FPGA shall be programmed to output a one-shot and a periodic SYSREF. The converter devices should align their internal LMFC to the rising edge of SYSREF. 3.2 For each frame format supported by the IDT DAC, the IP will be reconfigured. The latency between the data entering the IP and the data output is measured using a scope. 3.3 Minimum Deterministic Latency. The latency will be set to the minimum as described in section 6.3 and measured using a scope. DAC was seen to align LMFC to the incoming periodic SYSREF pulses. Check that total latency is within one DAC clk. Tested with K = 32, LMF = 421, 422, 222, 124 and DAC interpolation ratio of x4, x2, x8 IDT DAC has an offset register to release data to yet another moment than the LMFC bondary. 4 Deterministic Latency (Device Subclass 2) Test data is passed across the link with a deterministic latency in respect to SYNC~ assertion. 4.1 For each frame format supported by the IDT DAC the IP will be reconfigured and the latency between SYNC~ going high and the data output measured via Chipscope on the FPGA. 4.2 Minimum Deterministic Latency. The latency will be set to the minimum as described in section 6.3 and measured via Chipscope. N.A. N.A. Suclass 2 devices not supported by DAC. Suclass 2 devices not supported by DAC. 5 Framing Test the data passes correctly for all framing formats supported by the hardware.
7 [Interoperability Report] Rev 0.4 Page 7 of For each frame format supported by the IDT DAC the IP will be reconfigured and the link reestablished and the sample data verified by comparing the analogue data with the expected pattern. Framing format L=4, F=1, K=18 was tested. Framing format L=4, F=2, K=18 was tested. Framing format L=2, F=2, K=18 was tested. Framing format L=1, F= 4, K=18 was tested. Sine wave data checked on signal analyzer. 6 Initial Lane Sync Sequence Test the initial lane sequence is generated and received correctly including correct passing of the JESD204 configuration bytes. 6.1 Check the ILA is generated with the correct frame and multiframe numbers. 6.2 Check the Configuration data bytes are transferred correctly by inspecting register contents. The frame and multi-frame numbers were checked in DAC software. The configuration parameters were read from the DAC via SPI. 7 Data Samples and Control Bits Test the sample data is passed without error. 7.1 Check the analogue data from the DAC matches the pattern generated by the IP test pattern generator. A 1ksample lookup table based pattern generator shall be implemented to stimulate the IP. 7.2 Check the data received by the IP matches the analogue data stimulating the ADC. A repeating data pattern shall be injected into the ADC and captured by the IP using Xilinx Chipscope with a 2ksample window. N.A. Sine wave sent from FPGA with a step size of 1. Data checked on oscilloscope and signal analyzer at DAC. 8 Scrambling Test for correct link operation with scrambling enabled and disabled.
8 [Interoperability Report] Rev 0.4 Page 8 of Check for correct data with scrambling disabled. 8.2 Check for correct data with scrambling enabled. 8.3 Check the first few octets following the ILA are correct by using logic analyzer to check early sync option if applicable. 9 Test Patterns Test generation and reception of all test patterns detailed in JESD204B. 9.1 Check PRBS7 9.2 Check PRBS Check PRBS Check PRBS Check Short Transport Layer Test Pattern defined in section Check Long Transport Layer Test Pattern defined in section Check pattern two defined in section is transmitted and verified correctly. 9.8 Check pattern three defined in section is transmitted and verified correctly. 9.9 Check RPAT/JSPAT pattern defined in section is transmitted and verified correctly. N/A N/A Check BER counter inside DAC. Check BER counter inside DAC. Check BER counter inside DAC. Check BER counter inside DAC. Tested for F=1 with scrambler on. Not supported by DAC. Continuous sequence of /K28.5/ is supported. Code group synchronization followed by repetitive alignment sequence is supported. Not applicable. The test patterns are optional and are not supported by the DAC or FPGA core.
9 [Interoperability Report] Rev 0.4 Page 9 of Check JTSPAT pattern is transmitted and verified correctly. N/A Not applicable. The test patterns are optional and are not supported by the FPGA core. 10 Supported Line Rates Test correct operation at all rates supported by hardware Check operation at 3.125Gbps line rate Check operation at 6.375Gbps line rate Check operation at 10Gbps line rate Check operation at 12.5Gbps line rate using KC325T-3 device The DAC link was tested at 3.125Gbps. The DAC link was tested at 6.375Gbps. The DAC link was tested at 10Gbps. The DAC link was tested at 12.5Gbps on selected samples. 11 Alignment character replacement Test the correct insertion (Tx) and reinstatement (Rx) of alignment characters during normal data transmission as per and Check for alignment character insertion using logic analyzer in FPGA Check for alignment character insertion when scrambling disabled and ILA supported Check for alignment character insertion when scrambling disabled and ILA not supported Check for alignment character insertion when scrambling enabled Check when alignment character insertion is disabled and scrambling enabled Check when alignment character insertion is disabled and scrambling disabled. N.A. N.A.
10 [Interoperability Report] Rev 0.4 Page 10 of 14 Compliance to JESD204B Specification The interoperability tests in the previous section shall cover the items detailed in the table below. Spec section Contents Tested by Interop Notes 1 Scope N/A 2 References N/A 3 Terminology N/A 4 Electrical Partial Electrical interoperability is tested but compliance is not. 4.1 Overview Partial Electrical interoperability is tested but compliance is not. 4.2 Compliance Types Partial Electrical interoperability is tested but compliance is not. AC compliance only. 4.3 Interconnect Partial Electrical interoperability is tested but compliance is not Interconnect Insertion Loss Partial Electrical interoperability is tested but compliance is not. 4.4 LV-OIF-SxI5 Data Signals Partial Electrical interoperability is tested but compliance is not Compliance verification Partial Electrical interoperability is tested but compliance is not Transmitter Spec Partial Electrical interoperability is tested but compliance is not Receiver Spec Partial Electrical interoperability is tested but compliance is not. 4.5 LV-OIF-6G-SR Data Signals Partial Electrical interoperability is tested but compliance is not Compliance verification Partial Electrical interoperability is tested but compliance is not Transmitter Spec Partial Electrical interoperability is tested but compliance is not Receiver Spec Partial Electrical interoperability is tested but compliance is not. 4.6 LV-OIF-11G-SR Data Signals No 12.5G testing not carried out Compliance verification No 12.5G testing not carried out Transmitter Spec No 12.5G testing not carried out Receiver Spec No 12.5G testing not carried out 4.7 Device Clock Partial Compliance not tested. 4.8 Frame Clock, and Local Multiframe Clock Partial Frame clock used by FPGA but compliance not tested. 4.9 SYNC Interface Partial SYNC~ signal is used in interop testing but compliance not tested Lane-to-lane Inter-device Sync Interface No Left to user for subclass 0 devices in JESD204B Spec. Not necessary in subclass 1 and 2 devices. Unable to test in interop SYSREF signal Partial SYSREF signal is used in interop testing but compliance not tested Skew Budget No Unable to test in interop Control Interfaces N/A Left to user in JESD204B Spec. Out with scope of interop 5 Data Stream Partial See subsections 5.1 Transport Layer Partial See subsections Overview N/A User Data Format for and Partial Multi-lane devices used in interop
11 [Interoperability Report] Rev 0.4 Page 11 of 14 Independent Lane User Data Format for Multiple Lanes Partial Only formats supported by IDT DAC shall be tested Tail Bits No Formats supported by interop hardware do require tail bits Idle Mode No Unable to test in interop General No Unable to test in interop Dummy Samples No Unable to test in interop Test Modes No Additional logic required in FPGA as this function is not included in the IP Core General No Additional logic required in FPGA as this function is not included in the IP Core Short Transport Layer Test Pattern No Additional logic required in FPGA as this function is not included in the IP Core Long Transport Layer Test Pattern No Additional logic required in FPGA as this function is not included in the IP Core 5.2 Scrambling Polynomial Bit Order Scrambler Type Early Sync Option Only possible if there is a way of inspecting octets from the data stream individually Initial State N/A Early Sync implemented so Initial State is irrelevant Scrambling Disable 5.3 Data Link Layer Partial See subsections B10B Transmission Order Link Operation Partial See subsections Code Group Sync SYNC~ Signal Combining Initial Frame Sync Frame Alignment monitoring and Correction No Not possible to inject alignment errors Alignment Characters Character Replacement without Scrambling Character Replacement with Scrambling Frame Alignment Correction in Rx Partial Not possible to inject alignment errors in FPGA Initial Lane Synchronisation Lane alignment monitoring and correction Partial Not possible to inject alignment errors in FPGA Link re-initialization
12 [Interoperability Report] Rev 0.4 Page 12 of Test Modes General Test Sequences Partial Only /K28.5/ and lane alignment sequence tests are supported by the IP Core 6 Deterministic Latency Partial See subsections 6.1 Introduction N/A 6.2 No Support for Deterministic Latency (Device subclass 0) Partial Not tested above 6.25Gbps 6.3 Deterministic Latency Using SYSREF (Device subclass 1) Partial Not tested above 6.25Gbps 6.4 Deterministic Latency Using SYNC~ Detection (Device subclass 2) Partial Not tested above 6.25Gbps. See subsections Principles of SYNC~ Sampling N/A SYNC~ Generation at the RX Device Partial SYNC~ is generated on the RX device clock in the FPGA Adjustment Resolution and Adjustment Clock Detection Resolution at the TX Device Partial SYNC~ is detected on the TX device clock in the FPGA SYNC~ De-assertion and the Detection Interval No The IP Core transmitter aligns its LMFC to SYNC~ sampled on the device clock Master and Slave Configurations N/A ADC Master and Slave Configuration N/A DAC Master and Slave Configurations No Additional logic required in FPGA as phase adjustment is not included in the IP Core Summary of Requirements for Subclass 2 Deterministic Latency N/A 6.5 Interoperability Between JESD204A and JESD204B Devices 7 Receiver Operation Partial See subsections 7.1 Code Group Synchronisation 7.2 Initial Frame Synchronization 7.3 Frame Alignment monitoring and correction Partial Not possible to inject alignment errors in FPGA 7.4 Initial Lane Synchronisation May not be possible to check time to align 7.5 Lane alignment monitoring and correction Partial Not possible to inject alignment errors in FPGA 7.6 Error Handling No Not possible to inject errors Error Kinds No Not possible to inject errors
13 [Interoperability Report] Rev 0.4 Page 13 of Data Output on Error No Not possible to inject errors Errors Requiring reinitialization No Not possible to inject errors Error Reporting via SYNC interface No Not possible to inject errors Error Reporting via control interface No Not possible to inject errors 8 Transmitter Operation 8.1 Synchronisation 8.2 Initial Lane Alignment Sequence 8.3 Link Configuration Data and Encoding 8.4 SYNC Signal Decoding 8.5 SYNC~ Detection (Device Subclass 2) Partial Additional logic required in FPGA as phase adjustment is not included in the IP Core 9 Device Classification N/A
14 [Interoperability Report] Rev 0.4 Page 14 of 14 Document History Revision Date Name Change Details Aug 2012 N. McKay Initial Draft for review by IDT Aug 2012 D.Ramsay Minor edits after review May 2013 D. Ramsay Add IDT Logo October 2013 P. Lieutaud Add some extra tests.
Validating ADI Converters inter-operability with Xilinx FPGA and JESD204B IP
Validating ADI Converters inter-operability with Xilinx FPGA and JESD204B IP Introduction ADI continues to develop world class converter technologies and as a result requires us to develop high throughput
More informationAN 779: Intel FPGA JESD204B IP Core and ADI AD9691 Hardware Checkout Report
AN 779: Intel FPGA JESD204B IP Core and ADI AD9691 Hardware Checkout Report Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel FPGA JESD204B IP Core and AD9691 Hardware
More informationUnderstanding JESD204B High-speed inter-device data transfers for SDR
Understanding JESD204B High-speed inter-device data transfers for SDR Lars-Peter Clausen Introduction JESD204 Standard Designed as high-speed serial data link between converter (ADC, DAC) and logic device
More informationAltera JESD204B IP Core and ADI AD9680 Hardware Checkout Report
2015.05.11 Altera JESD204B IP Core and ADI AD9680 Hardware Checkout Report AN-710 Subscribe The Altera JESD204B IP core is a high-speed point-to-point serial interface intellectual property (IP). The JESD204B
More informationAN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report
AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents Intel FPGA JESD204B IP Core and ADI AD9208 Hardware
More informationJESD204A, PCB2064-3, PCB , Demonstration board, DAC, Labview, DAC1408D, DAC1208D, DAC1008D
DAC1x08 demonstrator: Demonstration board for DAC1x08D Rev. 02 2 July 2012 User manual Document information Info Keywords Abstract Content JESD204A, PCB2064-3, PCB2064-4.0, Demonstration board, DAC, Labview,
More informationHardware Demonstration Design
Hardware Demonstration Design JESD204 Hardware Demonstration User Guide 1 A hardware demonstration design, targeting the Kintex-7 KC705, Zynq-7000 ZC706, Virtex-7 VC709 or Artix-7 AC701 evaluation platforms,
More informationAD9144-FMC-EBZ Evaluation Board Quick Start Guide
One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 Tel: 781.329.4700 Fax: 781.461.3113 www.analog.com AD9144-FMC-EBZ Evaluation Board Quick Start Guide Getting Started with the AD9144-FMC-EBZ Evaluation
More informationTechnical Article MS-2442
Technical Article MS-2442. JESD204B vs. Serial LVDS Interface Considerations for Wideband Data Converter Applications by George Diniz, Product Line Manager, Analog Devices, Inc. Some key end-system applications
More informationAN 833: Intel Stratix 10 GX 16- Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
AN 833: Intel Stratix 10 GX 16- Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents Intel Stratix 10 GX 16-Lane
More informationKC705 GTX IBERT Design Creation October 2012
KC705 GTX IBERT Design Creation October 2012 XTP103 Revision History Date Version Description 10/23/12 4.0 Regenerated for 14.3. 07/25/12 3.0 Regenerated for 14.2. Added AR50886. 05/30/12 2.1 Minor updates.
More informationJESD204B IP Core User Guide
FPGA-IPUG-02010 Version 2.3 June 2017 Contents 1. Introduction... 4 1.1. Quick Facts... 4 1.2. Features... 5 1.3. What is Not Supported... 5 1.4. Conventions... 6 1.5. Data Ordering and Data Types... 6
More informationImplementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)
2015.12.30 Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow) AN-755 Subscribe The Altera JESD204B IP core is a high-speed point-to-point serial interface
More informationS2C K7 Prodigy Logic Module Series
S2C K7 Prodigy Logic Module Series Low-Cost Fifth Generation Rapid FPGA-based Prototyping Hardware The S2C K7 Prodigy Logic Module is equipped with one Xilinx Kintex-7 XC7K410T or XC7K325T FPGA device
More informationAD916x API Specification Rev 1.0
AD916x API Specification Rev 1.0 Page 1 of 84 TABLE OF CONTENTS Introduction...5 Purpose...5 Scope...5 DISCLAIMER...5 Software Architecture...6 Folder Structure...7 API Interface...8 Overview...8 ad916x.h...8
More informationArria 10 JESD204B IP Core Design Example User Guide
Arria 10 JESD204B IP Core Design Example User Guide UG-DEX-A10-JESD204B 2017.05.08 Last updated for Intel Quartus Prime Design Suite: 17.0 Subscribe Send Feedback Contents Contents 1 Arria 10 JESD204B
More informationAD9164 API Specification Rev 1.0
AD9164 API Specification Rev 1.0 Page 1 of 89 ADI Confidential TABLE OF CONTENTS Introduction...5 Purpose...5 Scope...5 DISCLAIMER...5 Software Architecture...6 Folder Structure...7 API Interface...8 Overview...8
More informationSMT9091 SMT148-FX-SMT351T/SMT391
Unit / Module Description: Unit / Module Number: Document Issue Number: Issue Date: Original Author: This Document provides an overview of the developed system key features. SMT148-FX-SMT351T/SMT391 E.Puillet
More informationAN 803: Implementing Analog-to- Digital Converter Multi-Link Designs with Intel Arria 10 JESD204B RX IP Core
AN 803: Implementing Analog-to- Digital Converter Multi-Link Designs with Intel Arria 10 JESD204B RX IP Core Subscribe S Feedback Latest document on the web: PDF HTML Contents Contents Implementing Analog-to-Digital
More informationRiseUp RU8-DP-DV Series 19mm Stack Height Final Inch Designs in PCI Express Applications. Revision Date: March 18, 2005
RiseUp RU8-DP-DV Series 19mm Stack Height Final Inch Designs in PCI Express Applications Revision Date: March 18, 2005 Copyrights and Trademarks Copyright 2005 Samtec, Inc. Developed in conjunction with
More informationOne Technology Way P.O. Box 9106 Norwood, MA Tel: Fax:
One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 Tel: 781.329.4700 Fax: 781.461.3113 www.analog.com DPG3 The DPG3, or Data Pattern Generator 3, is a device designed to support the evaluation of
More informationTEST REPORT POWER SUPPLY AND THERMAL V2
CERN European Organization for Nuclear Research Beams Department Radio Frequency RF Feedbacks and Beam Control TEST REPORT POWER SUPPLY AND THERMAL V2 By: Petri Leinonen BE-RF-FB Date: 27.06.2012 TABLE
More information10Gb Ethernet PCS Core
July 2002 Features Complete 10Gb Ethernet Physical Coding Sublayer (PCS) Solution Based on the ORCA 10 Gbits/s Line Interface (ORLI10G) FPSC, Enabling Flexible10GbE LAN/WAN Application Solutions. IP Targeted
More informationQ Pairs QTE/QSE-DP Final Inch Designs In PCI Express Applications 16 mm Stack Height
Application Note Q Pairs QTE/QSE-DP Final Inch Designs In PCI Express Applications 16 mm Stack Height Copyrights and Trademarks Copyright 2004 Samtec, Inc. Developed in conjunction with Teraspeed Consulting
More informationTechnical Article MS-2503
Technical Article MS-2503. Slay Your System Dragons with JESD204B by Ian Beavers, Applications Engineer, Analog Devices, Inc. The JESD204B serial data link interface was developed to support the growing
More informationJESD204B Intel Cyclone 10 GX FPGA IP Design Example User Guide
JESD204B Intel Cyclone 10 GX FPGA IP Design Example User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. JESD204B
More informationPMC429-4/8/16/32 Hardware Manual
PMC429-4/8/16/32 Hardware Manual 4/8/16/32 Channel Conduction Cooled ARINC429 Module for PMC November 2014 V02.00 Rev. C PMC429-4/8/16/32 Hardware Manual 4/8/16/32 Channel Conduction Cooled ARINC429 Module
More informationSATA Storage Duplicator Instruction on KC705 Rev Sep-13
SATA Storage Duplicator Instruction on KC705 Rev1.0 24-Sep-13 This document describes the step to run SATA Duplicator Demo for data duplication from one SATA disk to many SATA disk by using Design Gateway
More informationQ2 QMS/QFS 16mm Stack Height Final Inch Designs In PCI Express Applications Generation Gbps. Revision Date: February 13, 2009
Q2 QMS/QFS 16mm Stack Height Final Inch Designs In PCI Express Applications Generation 2 5.0 Gbps Revision Date: February 13, 2009 Copyrights and Trademarks Copyright 2009 Samtec, Inc. Developed in conjunction
More informationML605 GTX IBERT Design Creation
ML605 GTX IBERT Design Creation December 2010 Copyright 2010 Xilinx XTP046 Revision History Date Version Description 12/21/10 12.4 Recompiled under 12.4. 10/05/10 12.3 Recompiled under 12.3. AR36576 fixed.
More informationcpci-dart Base-Board & Daughter-Board
DYNAMIC ENGINEERING 150 DuBois, Suite C Santa Cruz, CA 95060 (831) 457-8891 Fax (831) 457-4793 http://www.dyneng.com sales@dyneng.com Est. 1988 User Manual cpci-dart Base-Board & Daughter-Board Eight-Channel
More informationQPairs QTE/QSE-DP Multi-connector Stack Designs In PCI Express Applications 16 mm Connector Stack Height REVISION DATE: OCTOBER 13, 2004
Application Note QPairs QTE/QSE-DP Multi-connector Stack Designs In PCI Express Applications 16 mm Connector Stack Height REVISION DATE: OCTOBER 13, 2004 Copyrights and Trademarks Copyright 2004 Samtec,
More informationOptimal Management of System Clock Networks
Optimal Management of System Networks 2002 Introduction System Management Is More Challenging No Longer One Synchronous per System or Card Must Design Source-Synchronous or CDR Interfaces with Multiple
More informationTitanMIMO-X. 250 MHz OTA Real-Time BW Massive MIMO Testbed PRODUCT SHEET. nutaq.com MONTREAL QUEBEC
TitanMIMO-X 250 MHz OTA Real-Time BW Massive MIMO Testbed PRODUCT SHEET QUEBEC I MONTREAL I N E W YO R K I nutaq.com TitanMIMO-X 5G, Millimeter Wave and Massive MIMO research without the shortage in real-time
More informationIntroduction Technology Equipment Performance Current developments Conclusions. White Rabbit. A quick introduction. Javier Serrano
White Rabbit A quick introduction Javier Serrano CERN BE-CO Hardware and Timing section ICALEPCS pre-conference workshop Barcelona, 7 October 2017 Javier Serrano Introduction to White Rabbit 1/29 Outline
More informationSerialLite III Streaming IP Core Design Example User Guide for Intel Arria 10 Devices
IP Core Design Example User Guide for Intel Arria 10 Devices Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Quick Start
More informationECE 485/585 Microprocessor System Design
Microprocessor System Design Lecture 16: PCI Bus Serial Buses Zeshan Chishti Electrical and Computer Engineering Dept. Maseeh College of Engineering and Computer Science Source: Lecture based on materials
More informationSP605 GTP IBERT Design Creation
SP605 GTP IBERT Design Creation October 2010 Copyright 2010 Xilinx XTP066 Revision History Date Version Description 10/05/10 12.3 Recompiled under 12.3. ARs Present in Spartan-6 IBERT Design: AR36775 Delay
More informationSP605 GTP IBERT Design Creation
SP605 GTP IBERT Design Creation January 2010 Copyright 2009, 2010 Xilinx XTP066 Note: This Presentation applies to the SP605 SP605 IBERT Overview Xilinx SP605 Board Software Requirements Setup for the
More information10GBase-R PCS/PMA Controller Core
10GBase-R PCS/PMA Controller Core Contents 1 10GBASE-R PCS/PMA DATA SHEET 1 1.1 FEATURES.................................................. 1 1.2 APPLICATIONS................................................
More informationSignal Conversion in a Modular Open Standard Form Factor. CASPER Workshop August 2017 Saeed Karamooz, VadaTech
Signal Conversion in a Modular Open Standard Form Factor CASPER Workshop August 2017 Saeed Karamooz, VadaTech At VadaTech we are technology leaders First-to-market silicon Continuous innovation Open systems
More informationHIGH SPEED SIGNAL CHAIN SELECTION GUIDE
HIGH SPEED SIGNAL CHAIN SELECTION GUIDE Includes High Speed Cs, DACs, Amplifiers, and Clocking Solutions Visit analog.com and linear.com High Speed Signal Chain Product Selection Guide TABLE OF CONTENTS
More informationAvnet S6LX16 Evaluation Board and Maxim DAC/ADC FMC Module Reference Design
Avnet S6LX16 Evaluation Board and Maxim DAC/ADC FMC Module Reference Design By Nasser Poureh, Avnet Technical Marketing Manager Mohammad Qazi, Maxim Application Engineer, SP&C Version 1.0 August 2010 1
More informationAbstract. 2. Literature Review. Keywords. 1. Introduction. Neeta S. Matti 1, Saroja V. Siddamal 2
To Develop Prototype Model of FPGA and RF UP Converter Neeta S. Matti 1, Saroja V. Siddamal 2 Abstract Radio jamming is the transmission of radio signals that disrupt communications by decreasing the signal
More informationNew! New! New! New! New!
New! New! New! New! New! Model 5950 Features Supports Xilinx Zynq UltraScale+ RFSoC FPGAs 18 GB of DDR4 SDRAM On-board GPS receiver PCI Express (Gen. 1, 2 and 3) interface up to x8 LVDS connections to
More informationHello, and welcome to this presentation of the STM32 Universal Synchronous/Asynchronous Receiver/Transmitter Interface. It covers the main features
Hello, and welcome to this presentation of the STM32 Universal Synchronous/Asynchronous Receiver/Transmitter Interface. It covers the main features of this USART interface, which is widely used for serial
More informationTerasic THDB-SUM SFP. HSMC Terasic SFP HSMC Board User Manual
Terasic THDB-SUM SFP HSMC Terasic SFP HSMC Board User Manual Document Version 1.00 AUG 12, 2009 by Terasic Introduction Page Index INTRODUCTION... 1 1.1 1.1 FEATURES... 1 1.2 1.2 ABOUT THE KIT... 2 1.3
More informationSundance Multiprocessor Technology Limited. Capture Demo For Intech Unit / Module Number: C Hong. EVP6472 Intech Demo. Abstract
Sundance Multiprocessor Technology Limited EVP6472 Intech Demo Unit / Module Description: Capture Demo For Intech Unit / Module Number: EVP6472-SMT911 Document Issue Number 1.1 Issue Data: 6th October
More informationNew Software-Designed Instruments
1 New Software-Designed Instruments Nicholas Haripersad Field Applications Engineer National Instruments South Africa Agenda What Is a Software-Designed Instrument? Why Software-Designed Instrumentation?
More informationEV10AQ190-DK Demo Kit Quad10 ADC
Demo Kit Quad10 ADC Demo Kit Summary Main Features Demonstrator Board with VITA57 Standard Connectors Quad ADC with 10-bit Resolution Sampling Rate in 4-channel Mode (1) 2.5 Gsps Sampling Rate in 2-channel
More informationDesigning with the Xilinx 7 Series PCIe Embedded Block. Tweet this event: #avtxfest
Designing with the Xilinx 7 Series PCIe Embedded Block Follow @avnetxfest Tweet this event: #avtxfest www.facebook.com/xfest2012 Why Would This Presentation Matter to You? 2 If you are designing a PCIe
More information5 GT/s and 8 GT/s PCIe Compared
5 GT/s and 8 GT/s PCIe Compared Bent Hessen-Schmidt SyntheSys Research, Inc. Copyright 2008, PCI-SIG, All Rights Reserved 1 Disclaimer The material included in this presentation reflects current thinking
More informationDYNAMIC ENGINEERING 150 DuBois St. Suite C, Santa Cruz, Ca Fax Est.
DYNAMIC ENGINEERING 150 DuBois St. Suite C, Santa Cruz, Ca 95060 831-457-8891 Fax 831-457-4793 http://www.dyneng.com sales@dyneng.com Est. 1988 User Manual PMC-PARALLEL-TTL-BA16 Digital Parallel Interface
More informationSerialLite III Streaming IP Core Design Example User Guide for Intel Stratix 10 Devices
SerialLite III Streaming IP Core Design Example User Guide for Intel Stratix 10 Devices Updated for Intel Quartus Prime Design Suite: 17.1 Stratix 10 ES Editions Subscribe Send Feedback Latest document
More informationThe Lekha 3GPP LTE Turbo Decoder IP Core meets 3GPP LTE specification 3GPP TS V Release 10[1].
Lekha IP Core: LW RI 1002 3GPP LTE Turbo Decoder IP Core V1.0 The Lekha 3GPP LTE Turbo Decoder IP Core meets 3GPP LTE specification 3GPP TS 36.212 V 10.5.0 Release 10[1]. Introduction The Lekha IP 3GPP
More informationA (Very Hand-Wavy) Introduction to. PCI-Express. Jonathan Heathcote
A (Very Hand-Wavy) Introduction to PCI-Express Jonathan Heathcote Motivation Six Week Project Before PhD Starts: SpiNNaker Ethernet I/O is Sloooooow How Do You Get Things In/Out of SpiNNaker, Fast? Build
More informationAN 836: RapidIO II Reference Design for Avalon-ST Pass-Through Interface
AN 836: RapidIO II Reference Design for Avalon-ST Pass-Through Interface Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 RapidIO II Reference Design for Avalon -ST Pass-Through
More informationEnabling MIPI Physical Layer Test
Enabling MIPI Physical Layer Test High Speed Test and Characterization High Speed Digital Test The Explosion of Functions within Mobile Devices Multiple RF functions GPS Bluetooth WCDMA GSM WLAN FM Multiple
More informationLatticeSC/Marvell. XAUI Interoperability. Introduction. XAUI Interoperability
LatticeSC/Marvell XAUI Interoperability November 2006 Introduction Technical Note TN1128 The document provides a report on a XAUI interoperability test between a LatticeSC device and the Marvell 88X2040
More informationUltraScale Architecture Integrated IP Core for Interlaken v1.3
UltraScale Architecture Integrated IP Core for Interlaken v1.3 LogiCORE IP Product Guide Vivado Design Suite Table of Contents IP Facts Chapter 1: Overview Feature Summary..................................................................
More informationSMT943 APPLICATION NOTE 1 APPLICATION NOTE 1. Application Note - SMT372T and SMT943.doc SMT943 SUNDANCE MULTIPROCESSOR TECHNOLOGY LTD.
APPLICATION NOTE 1 Application Note - SMT372T + SMT943 SMT943 SUNDANCE MULTIPROCESSOR TECHNOLOGY LTD. Date Comments / Changes Author Revision 07/07/10 Original Document completed CHG 1 Date 13/05/2010
More informationSMT-FMC211. Quad DAC FMC. Sundance Multiprocessor Technology Limited
Sundance Multiprocessor Technology Limited Form : QCF51 Template Date : 10 November 2010 Unit / Module Description: Quad DAC FMC Unit / Module Number: Document Issue Number: 1.1 Original Issue Date: 11
More information10 Gigabit Ethernet Consortium 10GBASE-R PCS Test Suite version 0.4
10GBASE-R PCS Test Suite version 0.4 UNH-IOL 121 Technology Drive, Suite 2 Durham, NH 03824 +1-603-862-0090 10geclab@iol.unh.edu +1-603-862-0205 Vendor X August 21, 2005 Company Name Report Rev. 1.0 Street
More informationA HT3 Platform for Rapid Prototyping and High Performance Reconfigurable Computing
A HT3 Platform for Rapid Prototyping and High Performance Reconfigurable Computing Second International Workshop on HyperTransport Research and Application (WHTRA 2011) University of Heidelberg Computer
More informationUltraScale Architecture Integrated Block for 100G Ethernet v1.4
UltraScale Architecture Integrated Block for 100G Ethernet v1.4 LogiCORE IP Product Guide Vivado Design Suite Table of Contents IP Facts Chapter 1: Overview Feature Summary..................................................................
More informationVirtex 6 FPGA Broadcast Connectivity Kit FAQ
Getting Started Virtex 6 FPGA Broadcast Connectivity Kit FAQ Q: Where can I purchase a kit? A: Once the order entry is open, you can purchase your Virtex 6 FPGA Broadcast Connectivity kit online or contact
More informationNew! New! New! New! New!
New! New! New! New! New! Model 5950 Features Supports Xilinx Zynq UltraScale+ RFSoC FPGAs 18 GB of DDR4 SDRAM On-board GPS receiver PCI Express (Gen. 1, 2 and 3) interface up to x8 LVDS connections to
More informationTrends in Digital Interfaces for High-Speed ADCs
Trends in Digital Interfaces for High-Speed ADCs Robbie Shergill National Semiconductor Corp. INTRODUCTION The analog-to-digital converter is a critical component in many of the most demanding applications
More informationAppNote-US2400-EVB Low Power 2.4GHz Transceiver
US2400-EVB for IEEE 802.15.4 Standard Revision History Hardware Revision Date Description of Changes V01 / V02 Sep. 2011 Initial release V03 Dec 2011 Addition 4.1 Evaluation Board Variants and 5.3 Connector
More informationQuick Start PCB2115 Demonstration Board ADC1613D, ADC1413D, ADC1213D, ADC1113D series Rev. 1 10th March 2010
Quick Start PCB2115 Demonstration Board ADC1613D, ADC1413D, ADC1213D, ADC1113D series Rev. 1 10th March 2010 Document information Info Keywords Abstract Block Diagram Content PCB2115, Demonstration board,
More informationPretty Good Protocol - Design Specification
Document # Date effective October 23, 2006 Author(s) Ryan Herbst Supersedes Draft Revision 0.02 January 12, 2007 Document Title Pretty Good Protocol - Design Specification CHANGE HISTORY LOG Revision Effective
More informationStrategies for Deploying RFSoC Technology for SIGINT, DRFM and Radar Applications. Rodger Hosking Pentek, Inc. WInnForum Webinar November 8, 2018
Strategies for Deploying RFSoC Technology for SIGINT, DRFM and Radar Applications Rodger Hosking Pentek, Inc. WInnForum Webinar November 8, 2018 1 Topics Xilinx RFSoC Overview Impact of Latency on Applications
More informationThe Benefits of FPGA-Enabled Instruments in RF and Communications Test. Johan Olsson National Instruments Sweden AB
The Benefits of FPGA-Enabled Instruments in RF and Communications Test Johan Olsson National Instruments Sweden AB 1 Agenda Introduction to FPGAs in test New FPGA-enabled test applications FPGA for test
More informationSMT166-FMC User Guide
Sundance Multiprocessor Technology Limited Product Specification Unit / Module Description: Unit / Module Number: Document Issue Number: Issue Date: Original Author: SMT166-FMC User Guide Revision History
More informationSFPFMC User Manual Rev May-14
SFPFMC User Manual Rev1.0 15-May-14 1 Introduction Thank you for choosing SFPFMC board [Part Number: AB15-SFPFMC]. SFPFMC board is compliant with FMC standard (HPC) and provides four SFP+ channels, so
More informationSOFTWARE DEFINED RADIO
SOFTWARE DEFINED RADIO USR SDR WORKSHOP, SEPTEMBER 2017 PROF. MARCELO SEGURA SESSION 1: SDR PLATFORMS 1 PARAMETER TO BE CONSIDER 2 Bandwidth: bigger band better analysis possibilities. Spurious free BW:
More informationUART TO SPI SPECIFICATION
UART TO SPI SPECIFICATION Author: Dinesh Annayya dinesha@opencores.org Table of Contents Preface... 3 Scope... 3 Revision History... 3 Abbreviations... 3 Introduction... 3 Architecture... 4 Baud-rate generator
More informationUsing PEX 8648 SMA based (SI) Card
Using PEX 8648 SMA based (SI) Card White Paper Version 1.3 July 2010 Website: Technical Support: www.plxtech.com www.plxtech.com/support Copyright 2008 by PLX Technology, Inc. All Rights Reserved Version
More informationSimplifying Validation and Debug of USB 3.0 Designs - Tektronix USB Testing Solutions Introduction. name title
Simplifying Validation and Debug of USB 3.0 Designs - Tektronix USB Testing Solutions Introduction name title Agenda Introduction USB 3.0 SuperSpeed Why USB 3.0? Timeline Cable Transmitter Receiver Protocol
More informationRelationship of 1000BASE-T1 to other standards
97.1.2 Relationship of 1000BASE-T1 to other standards Relations between the 1000BASE-T1 PHY, the ISO Open Systems Interconnection (OSI) Reference Model, and the IEEE 802.3 CSMA/CD LAN Model are shown in
More informationUG0850 User Guide PolarFire FPGA Video Solution
UG0850 User Guide PolarFire FPGA Video Solution Microsemi Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136
More information40-Gbps and 100-Gbps Ethernet in Altera Devices
40-Gbps and 100-Gbps Ethernet in Altera Devices Transceiver Portfolio Workshops 2009 Agenda 40/100 GbE standards 40/100 GbE IP in Altera devices Stratix IV GT FPGA features and advantages Altera standards
More informationPCI Express 1.0a and 1.1 Add-In Card Transmitter Testing
Abstract PCI Express 1.0a and 1.1 Add-In Card Transmitter Testing Joan Gibson November 2006 SR-TN062 Add-in cards designed for PCI Express require numerous tests to assure inter-operability with different
More informationDebugging Transceiver Links
Debugging s 11 QII53029 Subscribe This chapter describes using the Transceiver Toolkit to optimize high-speed serial links in your board design. The Transceiver Toolkit provides real-time control, monitoring,
More informationArria II GX FPGA Development Kit HSMC Loopback Tests Rev 0.1
Arria II GX FPGA Development Kit HSMC Loopback Tests Rev 0.1 High Speed Design Team, San Diego Thursday, July 23, 2009 1 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions
More informationQuick start ADC1453D, ADC1159D evaluation board
ADC1453D, ADC1159D evaluation board Rev. 01 14 Nov 2013 Document information Info Keywords Abstract Overview Content ADC1453D, ADC1159D, ADC1453DxxxW1-DB, evaluation board, ADC, Converter, JESD204B, BSX0254.
More informationNew! New! New! New! New!
New! New! New! New! New! Model 3320 Features Sold as the: FlexorSet Model 5973-320 FlexorSet Model 7070-320 Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across Two 3.0 GHz*
More information10-Gbps Ethernet Hardware Demonstration Reference Design
10-Gbps Ethernet Hardware Demonstration Reference Design July 2009 AN-588-1.0 Introduction This reference design demonstrates wire-speed operation of the Altera 10-Gbps Ethernet (10GbE) reference design
More informationViterbi Decoder Block Decoding - Trellis Termination and Tail Biting Authors: Bill Wilkie and Beth Cowie
Application Note: All Virtex and Spartan FPGA Families XAPP551 (1.0) February 14, 2005 R Viterbi Decoder Block Decoding - Trellis Termination and Tail Biting Authors: Bill Wilkie and Beth Cowie Summary
More informationThe White Rabbit Project
WR Project Status 1/ 1 The White Rabbit Project Technical introduction and status report T. W lostowski BE-CO Hardware and Timing section CERN November 11, 2010 WR Project Status 2/ 1 Introduction Outline
More informationEnglish Japanese
Spartan -6 FPGA Consumer Video Kit FAQ General Questions: Q: What is the Spartan -6 FPGA Consumer Video Kit? A: The Spartan-6 FPGA Consumer Video Kit (CVK) consists of a Spartan-6 LX150T base board, four
More informationMC20902-EVB. MC20902 D-PHY 5-Channel Master Transmitter Evaluation Board User's Guide PRELIMINARY DATASHEET. Version February 2014.
C O N F MC20902 D-PHY 5-Channel Master Transmitter Evaluation Board User's Guide I D E N PRELIMINARY DATASHEET Version 1.00 T February 2014 I Meticom GmbH A L Meticom GmbH Page 1 of 14 Revision History
More informationADC1x13S Demonstration Board for ADC1x13S
Quick Start ADC1x13S Demonstration Board for ADC1x13S Rev. 2 2 July 2012 Document information Info Keywords Abstract Block Diagram Content DEMO ADC1x13S, PCB2120-1, Demonstration board, ADC, Converter,
More informationSATA PHY Design Manual
SATA PHY Design Manual BeanDigital (v1.0) 1 July 2012 Revision History Date Version Revision 11/07/12 1.0 Initial release Page 2 1 Contents 2 Introduction... 4 3 Block Diagram... 4 4 Interface... 5 5 Parameters...
More informationLogiCORE IP RXAUI v2.4
LogiCORE P RXAU v2.4 Product Guide Table of Contents SECTON : SUMMARY P Facts Chapter 1: Overview Feature Summary.................................................................. 7 Applications......................................................................
More informationBlazePPS (Blaze Packet Processing System) CSEE W4840 Project Design
BlazePPS (Blaze Packet Processing System) CSEE W4840 Project Design Valeh Valiollahpour Amiri (vv2252) Christopher Campbell (cc3769) Yuanpei Zhang (yz2727) Sheng Qian ( sq2168) March 26, 2015 I) Hardware
More informationPXDAC4800. Product Information Sheet. 1.2 GSPS 4-Channel Arbitrary Waveform Generator FEATURES APPLICATIONS OVERVIEW
Product Information Sheet PXDAC4800 1.2 GSPS 4-Channel Arbitrary Waveform Generator FEATURES 4 AC-Coupled or DC-Coupled DAC Channel Outputs 14-bit Resolution @ 1.2 GSPS for 2 Channels or 600 MSPS for 4
More informationRECONFIGURABLE SPI DRIVER FOR MIPS SOFT-CORE PROCESSOR USING FPGA
RECONFIGURABLE SPI DRIVER FOR MIPS SOFT-CORE PROCESSOR USING FPGA 1 HESHAM ALOBAISI, 2 SAIM MOHAMMED, 3 MOHAMMAD AWEDH 1,2,3 Department of Electrical and Computer Engineering, King Abdulaziz University
More informationPCI Express 4.0. Electrical compliance test overview
PCI Express 4.0 Electrical compliance test overview Agenda PCI Express 4.0 electrical compliance test overview Required test equipment Test procedures: Q&A Transmitter Electrical testing Transmitter Link
More informationHDMI Solution. U N Vasudev - Strategic Product Planner
HDMI Solution U N Vasudev - u.n.vasudev@tek.com Strategic Product Planner Agenda HDMI Overview and updates Additional resources HDMI High Definition Multimedia Interface HDMI 2.0 Testing Customer presentation
More information