TOP VIEW GND 1 6 EN TOP MARK PACKAGE CODE. Maxim Integrated Products 1

Transcription

1 9-3266; Rev 2; 2/4 +.2V to +3.6V,.µA, Mbps, General Description The MAX33/MAX34/MAX323 single-/dual-/quadlevel translators provide the level shifting necessary to allow Mbps data transfer in a multivoltage system. Externally applied voltages, and, set the logic levels on either side of the device. Logic signals present on the side of the device appear as a higher voltage logic signal on the VCC side of the device, and viceversa. The MAX33 single-, the MAX34 dual-, and the MAX323 (UCSP package) quad-level translators feature an enable () input. The MAX323 (TSSOP package) quad-level translator features and inputs. When disabled, each device places all inputs/outputs on both sides in tri-state and reduces the supply current to.3µa, and the supply current to.µa. These devices operate at a guaranteed Mbps data rate for >.8V. The MAX33/MAX34/MAX323 accept a +.65V to +3.6V voltage and a +.2V to ( -.4V) voltage, making them ideal for data transfer between low-voltage ASICs/programmable logic devices (PLDs) and higher voltage systems. The MAX33 is available in 3 x 2 UCSP and 6-pin SC7 packages. The MAX34 is available in 3 x 3 UCSP and 8-pin SOT23 packages. The MAX323 is available in 4 x 3 UCSP and 4-pin TSSOP packages. All devices operate over the extended -4 C to +85 C temperature range. Applications CMOS Logic-Level Translation Low-Voltage ASIC Level Translation Cell Phones SPI, MICROWIRE Level Translation Portable POS Systems Portable Communication Devices GPS Telecommunications Equipment Features Mbps Guaranteed Data Rate Bidirectional Level Translation MAX33 (Single) MAX34 (Dual) MAX323 (Quad) Operation Down to +.2V Ultra-Low.µA Supply Current When Disabled Low-Quiescent Current (.µa) UCSP, SC7, SOT23, and TSSOP Packages TOP VIEW +.8V GND I/O V SYSTEM CONTROLLER GND MAX SC7 CLK DATA.µF 5 Typical Operating Circuit I/O I/O 2 Pin Configurations I/O MAX34 GND A B I/O I/O I/O MAX33 I/O 3 x 2 UCSP TOP VIEW (BUMPS ON BOTTOM OF DIE).µF CLK +3.3V SYSTEM DATA GND GND +3.3V Ordering Information/Selector Guide MAX33/MAX34/MAX323 PART TEMP RANGE PIN-PACKAGE MICROWIRE is a trademark of National Semiconductor Corp. SPI is a trademark of Motorola, Inc. UCSP is a trademark of Maxim Integrated Products, Inc. PACKAGE CODE TOP MARK NUMBER OF TRANSLATORS Number of TRANSLATORS MAX33EXT -4 C to +85 C 6 SC7 ACD Pin Configurations continued at end of data sheet. Ordering Information/Selector Guide continued at end of data sheet. Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 +.2V to +3.6V,.µA, Mbps, MAX33/MAX34/MAX323 ABSOLUTE MAXIMUM RATINGS All voltages are referenced to GND V to +4V V to +4V I/O _...-.3V to ( +.3V) I/O _...-.3V to ( +.3V),...-.3V to ( +.3V) Short-Circuit Duration I/O _, I/O _ to GND...Continuous Continuous Power Dissipation (T A = +7 C) 6-Pin SC7 (derate 3.mW/ C above +7 C)...245mW Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS 6-Bump UCSP (derate 3.9mW/ C above +7 C)...38mW 8-Bump UCSP (derate 4.7mW/ C above +7 C)...379mW 8-Pin SOT23 (derate 9.mW/ C above +7 C)...727mW 2-Bump UCSP (derate 6.5mW/ C above +7 C) mW 4-Pin TSSOP (derate 9.mW/ C above +7 C)...727mW Operating Temperature Range...-4 C to +85 C Junction Temperature...+5 C Storage Temperature Range C to +5 C Lead Temperature (soldering, s)...+3 C ( = +.65V to +3.6V, = +.2V to ( -.4V), =, = open (MAX323 TSSOP package only), C IOVL 5pF, C IOVCC 4pF, T A = T MIN to T MAX. Typical values are at T A = +25 C.) (Notes, 2) POWER SUPPLY PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Range V Supply Range V Supply Current from IQ I/O _ =, I/O _ = or I/O _ =, I/O _ =. µa Supply Current from IQ I/O _ =, I/O _ = or I/O _ =, I/O _ =, < -.2V I/O _ =, I/O _ = or I/O _ =, I/O _ =.2 2 µa Tri-state Output-Mode Supply Current Tri-state Output-Mode Supply Current (MAX33/MAX34) I TS-VCC T A = +25 C, =.3 µa T A = +25 C, =..2 I TS-VL µa T A = +25 C, =, = -.2V 2 Tri-state Output-Mode Supply Current (MAX323 TSSOP Package Only) T A = +25 C, = 5 7 I TS-VL T A = +25 C, =, = -.2V µa I/O Tri-state Output-Mode T A = +25 C, =.5 Leakage Current T A = +25 C, =, = -.2V 2 µa 2

3 +.2V to +3.6V,.µA, Mbps, ELECTRICAL CHARACTERISTICS (continued) ( = +.65V to +3.6V, = +.2V to ( -.4V), =, = open (MAX323 TSSOP package only), C IOVL 5pF, C IOVCC 4pF, T A = T MIN to T MAX. Typical values are at T A = +25 C.) (Notes, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LOGIC-LEVEL THRESHOLDS I/O _ Input-Voltage High V IHL 2/3 x V I/O _ Input-Voltage Low V ILL /3 x V Pullup Resistance on I/O _ 2 Ω Pulldown Resistance on I/O _ 75 Ω I/O _ Input-Voltage High V IHC 2/3 x V I/O _ Input-Voltage Low V ILC /3 x V Pullup Resistance on I/O _ 2.5 kω Pulldown Resistance on I/O _ 2.5 kω, Input-Voltage High V IH 2/3 x V, Input-Voltage Low V IL /3 x V Input Current MAX33/MAX µa Pullup Resistance on MAX kω Pulldown Resistance on MAX323, TSSOP package only kω I/O _ Output-Voltage High V OHL I/O source current = 2µA 2/3 x V I/O _ Output-Voltage Low V OLL I/O sink current = 2µA /3 x V I/O _ Output-Voltage High V OHC I/O source current = 2µA 2/3 x V I/O _ Output-Voltage Low V OLC I/O sink current = 2µA /3 x V MAX33/MAX34/MAX323 3

4 +.2V to +3.6V,.µA, Mbps, MAX33/MAX34/MAX323 TIMING CHARACTERISTICS ( = +.65V to +3.6V, = +.2V to ( -.4V), =, = open (MAX323 TSSOP package only), C IOVL 5pF, C IOVCC 4pF, T A = T MIN to T MAX. Typical values are at T A = +25 C.) (Notes, 2) PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS C IOVCC = 5pF, Figure 2.5 I/O _ Rise Time t RVCC C IOVCC = 2pF, Figure 3 C IOVCC = 4pF, Figure 4 C IOVCC = 5pF, Figure 2.5 I/O _ Fall Time t FVCC C IOVCC = 2pF, Figure 3 C IOVCC = 4pF, Figure 4 I/O _ One- S hot Outp ut Im p ed ance 8.5 Ω I/O _ Rise Time t RVL C IOVL = 5pF, Figure ns I/O _ Fall Time t FVL C IOVL = 5pF, Figure ns I/O _ One- S hot Outp ut Im p ed ance 2.5 Ω Propagation Delay, Driving I/O _ I/O VL-VCC C IOVCC = 5pF, Figure 6.5 ns Propagation Delay, Driving I/O _ I/O VCC-VL C IOVL = 5pF, Figure 2 6 ns Part-to-Part Skew ( N ote 3) t PPSKEW C IOVCC = 5pF, C IOVL = 5pF, = 2.5V, =.8V Propagation Delay from I/O _ to I/O _ after Enable Propagation Delay from I/O _ to I/O _ after Enable Maximum Data Rate Note : must be less than or equal to -.4V during normal operation. However, can be greater than during startup and shutdown conditions. Note 2: All units are % production tested at T A = +25 C. Limits over the operating temperature range are guaranteed by design and not production tested. Note 3: Not production tested. Guaranteed by design. ns ns 4 ns t -VCC C IOVCC = 5pF, Figure 3 ns t -VL C IOVL = 5pF, Figure 4 ns C IOVCC = 5p F, C IOVL = 5p F, >.8V C IOVCC = 5p F, C IOVL = 5p F, >.2V 8 Mbps 4

5 +.2V to +3.6V,.µA, Mbps, Typical Operating Characteristics (Data rate = Mbps, = 3.3V, =.8V, T A = +25 C, unless otherwise noted.) VL SUPPLY CURRT (ma) VCC SUPPLY CURRT (ma) SUPPLY CURRT vs. SUPPLY VOLTAGE.2 DRIVING I/O _ =.8V C IOVCC = 5pF SUPPLY VOLTAGE (V) SUPPLY CURRT vs. SUPPLY VOLTAGE 5 DRIVING I/O _ =.2V C IOVCC = 5pF SUPPLY VOLTAGE (V) MAX33 toc MAX33 toc4 VL SUPPLY CURRT (ma) VL SUPPLY CURRT (ma) SUPPLY CURRT vs. SUPPLY VOLTAGE DRIVING I/O _. =.2V C IOVCC = 5pF SUPPLY VOLTAGE (V) SUPPLY CURRT vs. TEMPERATURE 2.4 DRIVING I/O _ C IOVL = 5pF TEMPERATURE ( C) MAX33 toc2 MAX33 toc5 VCC SUPPLY CURRT (ma) VCC SUPPLY CURRT (ma) SUPPLY CURRT vs. SUPPLY VOLTAGE 5 DRIVING I/O _ =.8V C IOVCC = 5pF SUPPLY VOLTAGE (V) SUPPLY CURRT vs. TEMPERATURE DRIVING I/O _ C IOVL = 5pF TEMPERATURE ( C) MAX33 toc3 MAX33 toc6 MAX33/MAX34/MAX323 VL SUPPLY CURRT (ma) SUPPLY CURRT vs. CAPACITIVE LOAD ON I/O _ MAX33 toc7 VCC SUPPLY CURRT (ma) SUPPLY CURRT vs. CAPACITIVE LOAD ON I/O _ MAX33 toc8 RISE/FALL TIME (ns) RISE/FALL TIME vs. CAPACITIVE LOAD ON I/O _ t RISE t FALL MAX33 toc9 DRIVING I/O _ DRIVING I/O _ DRIVING I/O _ CAPACITIVE LOAD (pf) CAPACITIVE LOAD (pf) CAPACITIVE LOAD (pf) 5

6 +.2V to +3.6V,.µA, Mbps, MAX33/MAX34/MAX323 Typical Operating Characteristics (continued) (Data rate = Mbps, = 3.3V, =.8V, T A = +25 C, unless otherwise noted.) RISE/FALL TIME (ns) t-vcc (ns) RISE/FALL TIME vs. CAPACITIVE LOAD ON I/O _ t RISE t FALL.2 DRIVING I/O _ CAPACITIVE LOAD (pf) t -VCC vs. TEMPERATURE (C IOVCC = 5pF) MAX33 toc MAX33 toc3 PROPAGATION DELAY (ns) t-vl (ns) PROPAGATION DELAY vs. CAPACITIVE LOAD ON I/O _ DRIVING I/O _ t PHL t PLH CAPACITIVE LOAD (pf) t -VL vs. TEMPERATURE (C IOVL = 5pF) MAX33 toc MAX33 toc4 PROPAGATION DELAY (ns) PROPAGATION DELAY vs. CAPACITIVE LOAD ON I/O _ DRIVING I/O _ t PLH t PHL CAPACITIVE LOAD (pf) TYPICAL I/O _ DRIVING (C IOVCC = 4pF) MAX33 toc5 MAX33 toc2 2V/div 2V/div TEMPERATURE ( C) TEMPERATURE ( C) 4ns/div TYPICAL I/O _ DRIVING (C IOVL = 5pF) MAX33 toc6 TYPICAL I/O _ DRIVING ( =.65V, =.2V, C IOVCC = 4pF) MAX33 toc7 TYPICAL I/O _ DRIVING ( =.65V, =.2V, C IOVL = 5pF) MAX33 toc8 2V/div V/div V/div 2V/div V/div V/div 4ns/div 4ns/div 4ns/div 6

7 +.2V to +3.6V,.µA, Mbps, PIN MAX323 MAX33 MAX34 TSSOP 4 x 3 UCSP SC7 3 x 2 UCSP SOT23 3 x 3 UCSP Pin Description MAX33/MAX34/ MAX323 (Bidirectional Devices) NAME FUNCTION A 4 B2 7 A2 I/O Input/Output, Referenced to 2 B2 6 A3 I/O 2 Input/Output 2, Referenced to 3 A2 5 B 8 A Input Voltage, +.2V -.4V. Bypass to GND with a.µf capacitor. 4 N.C. No Connection 5 B3 I/O 3 Input/Output 3, Referenced to 6 A3 I/O 4 Input/Output 4, Referenced to 7 A4 6 B3 5 B 8 Active-High Enable Input. If is pulled low, all inputs/outputs are in tristate. Drive high ( ) for normal operation. Active-Low Enable Input. If is pulled high ( ), all inputs/ outputs are in tri-state. Drive low for normal operation (MAX323 TSSOP package only). 9 B4 I/O 4 Input/Output 4, Referenced to C4 I/O 3 Input/Output 3, Referenced to C3 2 A3 4 B3 GND Ground 2 C2 A C Input Voltage, +.65V +3.6V. Bypass to GND with a.µf capacitor. 3 C 3 C3 I/O 2 Input/Output 2, Referenced to 4 B 3 A2 2 C2 I/O Input/Output, Referenced to MAX33/MAX34/MAX323 7

8 +.2V to +3.6V,.µA, Mbps, MAX33/MAX34/MAX323 MAX33 I/O _ SOURCE Figure. Driving I/O _ Test Circuit and Timing MAX33 I/O _ C IOVCC VCC Test Circuits/Timing Diagrams t RISE/FALL 3ns I/O _ 9% 5% % I/O VL-VCC I/O VL-VCC I/O _ 9% 5% % t FVCC t RVCC t RISE/FALL 3ns I/O _ 9% 5% % I/O VCC-VL I/O VCC-VL I/O _ C IOVL_ I/O _ I/O _ 9% SOURCE 5% % t FVL t RVL Figure 2. Driving I/O _ Test Circuit and Timing 8

9 +.2V to +3.6V,.µA, Mbps, Test Circuits/Timing Diagrams (continued) I/O _ MAX33 t' -VCC SOURCE I/O _ I/O _ I/O _ MΩ C IOVCC I/O _ / 2 MAX33 MΩ t" -VCC SOURCE I/O _ I/O _ I/O _ C IOVCC / 2 t -VCC IS WHICH EVER IS LARGER BETWE t' -VCC AND t" -VCC. Figure 3. Propagation Delay from I/O _ to I/O _ After MAX33 t' -VL MAX33/MAX34/MAX323 SOURCE kω C IOVL I/O _ I/O _ I/O _ I/O _ / 2 MAX33 t" -VL SOURCE kω I/O _ C IOVL I/O _ I/O _ I/O _ / 2 t -VCC IS WHICH EVER IS LARGER BETWE t' -VCC AND t" -VCC. Figure 4. Propagation Delay from I/O _ to I/O _ After 9

10 +.2V to +3.6V,.µA, Mbps, MAX33/MAX34/MAX323 Detailed Description The MAX33/MAX34/MAX323 logic-level translators provide the level shifting necessary to allow Mbps data transfer in a multivoltage system. Externally applied voltages, and, set the logic levels on either side of the device. Logic signals present on the side of the device appear as a highervoltage logic signal on the side of the device, and vice-versa. The MAX33/MAX34/MAX323 bidirectional level translators allow data translation in either direction ( ) on any single data line. The MAX33/MAX34/MAX323 accept from +.2V to ( -.4V) and operate with from +.65V to +3.6V, making them ideal for data transfer between low-voltage ASICs/PLDs and higher voltage systems. When in tri-state mode, the MAX33/MAX34/ MAX323 reduce the supply current to.3µa, and the supply current to.µa. These devices operate at a guaranteed data rate of Mbps for >.8V. Level Translation For proper operation, ensure that +.65V +3.6V, and +.2V -.4V. During power-up sequencing, does not damage the device. During power-supply sequencing, when is floating and is powering up, up to 4mA current can be sourced to each load on the side, without the device latching up. The maximum data rate depends heavily on the load capacitance (see the Typical Operating Characteristics Rise/Fall Time graph), output impedance of the driver, and the operating voltage range (Table ). Input Driver Requirements The MAX33/MAX34/MAX323 architecture is based on a one-shot accelerator output stage (see Figure 5). Accelerator output stages are in tri-state mode except when there is a transition on any of the translators on the input side, either I/O _ or I/O _. A short pulse is then generated during which the accelerator output stages become active and charge/discharge the capacitances at the I/Os. Due to the architecture, both sides become active during the oneshot pulse. This can lead to some current feeding into the external source that is driving the translator. However, this behavior simply helps to speed up the transition on the driven side. For proper operation, the driver has to meet the following conditions: less than 25Ω output impedance and greater than 2mA peak output current capability. Table. Data Rate (V) GUARANTEED DATA RATE (Mbps) < I/O I/O _ TO I/O _ PATH P ONE-SHOT 4kΩ I/O N ONE-SHOT 5Ω P ONE-SHOT N ONE-SHOT I/O _ TO I/O _ PATH Figure 5. Simplified Functional Diagram (One I/O Line)

11 +.2V to +3.6V,.µA, Mbps, Figure 6 shows a graph of typical input current versus input voltage. Output Load Requirements The MAX33/MAX34/MAX323 I/O are designed to drive CMOS inputs. Do not load the I/O lines with a resistive load less than 25kΩ. Also, do not place an RC circuit at the input of these devices to slow down the edges. If a slower rise/fall time is required, refer to the MAX3E/MAX3E logic-level-translators data sheet. For I 2 C level translation, refer to the MAX3372E- MAX3379E/MAX339E MAX3393E data sheet. Enable Inputs The MAX33 single-, the MAX34 dual- and the MAX323 (UCSP package) quad-level translators feature an input. The MAX323 (TSSOP package) quad-level translator features both and inputs (see Table 2 for operating mode). Note that the MAX323 (TSSOP package) has internal pullup and pulldown circuitry on and, respectively. If left unconnected, is pulled up to and is pulled down to GND. V TH_IN / R IN * I IN V IN Table 2. MAX323 (TSSOP Package) Operating Mode O PER A T IN G M OD E Both I/O _ and I/O _ are in tri-state. Normal operation. Both I/O _ and I/O _ are in tri-state. Both I/O _ and I/O _ are in tri-state. Applications Information Power-Supply Decoupling To reduce ripple and the chance of introducing data errors, bypass and to ground with a.µf ceramic capacitor. Place all capacitors as close to the power-supply inputs as possible. Unidirectional vs. Bidirectional Level Translator The MAX33/MAX34/MAX323 bidirectional translators can operate as a unidirectional device to translate signals without inversion. These devices provide the smallest solution (UCSP package) for unidirectional level translation without inversion. UCSP Applications Information For the latest application details on UCSP construction, dimensions, tape carrier information, PC board techniques, bump-pad layout, and recommended reflow temperature profiles, as well as the latest information on reliability testing results, go to Maxim s web site at to find the Application Note: UCSP A Wafer-Level Chip-Scale Package. MAX33/MAX34/MAX323 V TH_IN -(V S - V TH_IN ) / R IN * V S WHERE V S = OR *R IN = 4kΩ WH DRIVING SIDE; R IN = 5Ω WH DRIVING SIDE. Figure 6. Typical I IN vs. V IN

12 +.2V to +3.6V,.µA, Mbps, MAX33/MAX34/MAX323 TOP VIEW TOP VIEW I/O I/O 2 GND I/O I/O 2 N.C. I/O 3 I/O MAX34 SOT23 MAX323 TSSOP I/O I/O 2 I/O I/O 2 GND I/O 3 I/O 4 MAX323 Pin Configurations (continued) A B C A B C 2 3 I/O MAX34 I/O I/O 2 GND I/O 2 UCSP (BUMPS ON BOTTOM OF DIE) I/O I/O I/O 2 I/O 2 I/O 4 I/O 3 I/O 4 GND I/O 3 UCSP (BUMPS ON BOTTOM OF DIE) Ordering Information/Selector Guide (continued) PART TEMP RANGE PIN-PACKAGE PACKAGE CODE TOP MARK NUMBER OF TRANSLATORS Number of TRANSLATORS MAX33EBT-T -4 C to +85 C 3 x 2 UCSP-6 B6- ADF MAX34EKA -4 C to +85 C 8 SOT23 AEKB 2 2 MAX34EBL-T -4 C to +85 C 3 x 3 UCSP-9 B9-2 A 2 2 MAX323EUD -4 C to +85 C 4 TSSOP 4 4 MAX323EBC-T -4 C to +85 C 4 x 3 UCSP-2 B2- ABW 4 4 TRANSISTOR COUNT: MAX33: 26 MAX34: 444 MAX323: 79 PROCESS: BiCMOS Chip Information 2

13 +.2V to +3.6V,.µA, Mbps, Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to SC7, 6L.EPS MAX33/MAX34/MAX323 PACKAGE OUTLINE, 6L SC C 3

14 +.2V to +3.6V,.µA, Mbps, MAX33/MAX34/MAX323 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to 6L, UCSP.EPS PACKAGE OUTLINE, 3x2 UCSP 2-97 G 4

15 +.2V to +3.6V,.µA, Mbps, Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to C L PIN I.D. DOT (SEE NOTE 6) A NOTE: A2 e D C L. ALL DIMSIONS ARE IN MILLIMETERS. 2. FOOT LGTH MEASURED FROM LEAD TIP TO UPPER RADIUS OF HEEL OF THE LEAD PARALLEL TO SEATING PLANE C. 3. PACKAGE OUTLINE EXCLUSIVE OF MOLD FLASH & METAL BURR. 4. PACKAGE OUTLINE INCLUSIVE OF SOLDER PLATING. 5. COPLANARITY 4 MILS. MAX. b C L 6. PIN I.D. DOT IS.3 MM ÿ MIN. LOCATED ABOVE PIN. 7. SOLDER THICKNESS MEASURED AT FLAT SECTION OF LEAD BETWE.8mm AND.5mm FROM LEAD TIP. 8. MEETS JEDEC MO78. e A E SEE DETAIL "A" C L C E SEATING PLANE C PROPRIETARY INFORMATION TITLE: APPROVAL SYMBOL A A A2 b C D E E L L2 e e L DETAIL "A" MIN MAX BSC..65 BSC..95 REF. 8 L2 DOCUMT CONTROL NO. GAUGE PLANE PACKAGE OUTLINE, SOT-23, 8L BODY 2-78 D REV. SOT23, 8L.EPS MAX33/MAX34/MAX323 5

16 +.2V to +3.6V,.µA, Mbps, MAX33/MAX34/MAX323 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to 9LUCSP, 3x3.EPS PACKAGE OUTLINE, 3x3 UCSP 2-93 I 6

17 +.2V to +3.6V,.µA, Mbps, Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to TSSOP4.4mm.EPS MAX33/MAX34/MAX323 7

18 +.2V to +3.6V,.µA, Mbps, MAX33/MAX34/MAX323 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to 2L, UCSP 4x3.EPS PACKAGE OUTLINE, 4x3 UCSP 2-4 F Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 Maxim Integrated Products, 2 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.