Low Voltage 1.15 V to 5.5 V, 8-Channel Bidirectional Logic Level Translator ADG3300

Transcription

1 Low Voltage.5 V to 5.5 V, 8-Channel Bidirectional Logic Level Translator ADG33 FEATURES Bidirectional level translation Operates from.5 V to 5.5 V Low quiescent current < µa No direction pin FUNCTIONAL BLOCK DIAGRAM A Y A Y APPLICATIONS A3 Y3 Low voltage ASIC level translation Smart card readers Cell phones and cell phone cradles Portable communications devices Telecommunications equipment Network switches and routers Storage systems (SAN/NAS) Computing/server applications GPS Portable POS systems Low cost serial interfaces A A5 A A7 A8 Y Y5 Y Y7 Y8 5- GERAL DESCRIPTION The ADG33 is a bidirectional logic level translator that contains eight bidirectional channels. It can be used in multivoltage digital system applications such as data transfer between a low voltage DSP/controller and a higher voltage device. The internal architecture allows the device to perform bidirectional logic level translation without an additional signal to set the direction of the translation. The voltage applied to VCCA sets the logic levels on the A side of the device, while VCCY sets the levels on the Y side. For proper operation, VCCA must always be less than VCCY. The VCCA-compatible logic signals applied to the A side of the device appear as VCCY-compatible levels on the Y side. Similarly, VCCY-compatible logic levels applied to the Y side of the device appear as VCCAcompatible logic levels on the A side. The enable pin provides three-state operation of the Y side pins. When the enable pin () is pulled low, the A to A8 pins are Figure. internally pulled down by kω resistors, while the Y terminals are in the high impedance state. The pin is referred to VCCA supply voltage and driven high for normal operation. The ADG33 is available in a compact -lead TSSOP package, and it is guaranteed to operate over the.5 V to 5.5 V supply voltage range and extended C to +85 C temperature range. PRODUCT HIGHLIGHTS. Bidirectional level translation.. Fully guaranteed over the.5 V to 5.5 V supply range. 3. No direction pin.. -lead TSSOP package. Rev. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 ADG33* PRODUCT PAGE QUICK LINKS Last Content Update: /3/7 COMPARABLE PARTS View a parametric search of comparable parts. EVALUATION KITS Evaluation Board for -Lead TSSOP Devices in the Switches and Multiplexers Portfolio DOCUMTATION Data Sheet ADG33: Low Voltage.5 V to 5.5 V, 8-Channel Bidirectional Logic Level Translator Data Sheet User Guides UG-3: Evaluation Board for -Lead TSSOP Devices in the Switches and Multiplexers Portfolio REFERCE MATERIALS Product Selection Guide Switches and Multiplexers Product Selection Guide DESIGN RESOURCES ADG33 Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints DISCUSSIONS View all ADG33 EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

3 ADG33 TABLE OF CONTTS Specifications... 3 Absolute Maximum Ratings... ESD Caution... Pin Configuration and Function Descriptions... 7 Typical Performance Characteristics... 8 Test Circuits... Terminology... Theory of Operation... 5 Level Translator Architecture... 5 Input Driving Requirements... 5 Output Load Requirements... 5 Enable Operation... 5 Power Supplies... 5 Data Rate... Applications... 7 Layout Guidelines... 7 Outline Dimensions... 8 Ordering Guide... 8 REVISION HISTORY /5 Revision : Initial Version Rev. Page of

4 SPECIFICATIONS VCCY =.5 V to 5.5 V, VCCA =.5 V to VCCY, = V. All specifications TMIN to TMAX, unless otherwise noted. ADG33 Table. Parameter Symbol Conditions Min Typ Max Unit LOGIC INPUTS/OUTPUTS A Side Input High Voltage 3 VIHA VCCA =.5 V VCCA.3 V VIHA VCCA =. V to 5.5 V VCCA. V Input Low Voltage 3 VILA. V Output High Voltage VOHA VY = VCCY, IOH = µa, Figure 7 VCCA. V Output Low Voltage VOLA VY = V, IOL = µa, Figure 7. V Three-State Pull-Down Resistance RA,HiZ =. 8. kω Y Side Input Low Voltage 3 VIHY VCCY. V Input High Voltage 3 VILY. V Output High Voltage VOHY VA = VCCA, IOH = µa, Figure 8 VCCY. V Output Low Voltage VOLY VA = V, IOL = µa, Figure 8. V Capacitance 3 CY f = MHz, =, Figure 3 pf Leakage Current ILY, HiZ VY = V/VCCY, =, Figure 9 ± µa Enable () Input High Voltage 3 VIH VCCA =.5 V VCCA.3 V VIH VCCA =. V to 5.5 V VCCA. V Input Low Voltage 3 VIL. V Leakage Current IL V = V/VCCA, VA = V, Figure 3 ± µa Capacitance 3 C 3 pf Enable Time 3 t RS = RT = 5 Ω, VA = V/VCCA (A Y),.8 µs Figure 3 SWITCHING CHARACTERISTICS V ±.3 V VCCA VCCY, VCCY = 5 V ±.5 V A Y Level Translation RS = RT = 5 Ω, CL = 5 pf, Figure 33 Propagation Delay tp, A-Y ns Rise Time tr, A-Y 3.5 ns Fall Time tf, A-Y 3.5 ns Maximum Data Rate DMAX, A-Y 5 Mbps Channel-to-Channel Skew tskew, A-Y ns Part-to-Part Skew tppskew, A-Y 3 ns Y A Level Translation RS = RT = 5 Ω, CL = 5 pf, Figure 3 Propagation Delay tp, Y-A 7 ns Rise Time tr, Y-A 3 ns Fall Time tf, Y-A 3 7 ns Maximum Data Rate DMAX, Y-A 5 Mbps Channel-to-Channel Skew tskew, Y-A 3.5 ns Part-to-Part Skew tppskew, Y-A ns.8 V ±.5 V VCCA VCCY, VCCY = 3.3 V ±.3 V A Y Translation RS = RT = 5 Ω, CL = 5 pf, Figure 33 Propagation Delay tp, A-Y 8 ns Rise Time tr, A-Y 5 ns Fall Time tf, A-Y 5 ns Maximum Data Rate DMAX, A-Y 5 Mbps Channel-to-Channel Skew tskew, A-Y ns Part-to-Part Skew tppskew, A-Y ns Rev. Page 3 of

5 ADG33 Parameter Symbol Conditions Min Typ Max Unit Y A Translation RS = RT = 5 Ω, CL = 5 pf, Figure 3 Propagation Delay tp, Y-A 5 8 ns Rise Time tr, Y-A 3.5 ns Fall Time tf, Y-A 3.5 ns Maximum Data Rate DMAX, Y-A 5 Mbps Channel-to-Channel Skew tskew, Y-A 3 ns Part-to-Part Skew tppskew, Y-A 3 ns.5 V to.3 V VCCA VCCY, VCCY = 3.3 V ±.3 V A Y Translation RS = RT = 5 Ω, CL = 5 pf, Figure 33 Propagation Delay tp, A-Y 9 8 ns Rise Time tr, A-Y 3 5 ns Fall Time tf, A-Y 5 ns Maximum Data Rate DMAX, A-Y Mbps Channel-to-Channel Skew tskew, A-Y 5 ns Part-to-Part Skew tppskew, A-Y ns Y A Translation RS = RT = 5 Ω, CL = 5 pf, Figure 3 Propagation Delay tp, Y-A 5 9 ns Rise Time tr, Y-A ns Fall Time tf, Y-A ns Maximum Data Rate DMAX, Y-A Mbps Channel-to-Channel Skew tskew, Y-A ns Part-to-Part Skew tppskew, Y-A ns.5 V to.3 V VCCA VCCY, VCCY =.8 V ±.3 V A Y Translation RS = RT = 5 Ω, CL = 5 pf, Figure 33 Propagation Delay tp, A-Y 5 ns Rise Time tr, A-Y 7 ns Fall Time tf, A-Y 3 5 ns Maximum Data Rate DMAX, A-Y 5 Mbps Channel-to-Channel Skew tskew, A-Y 5 ns Part-to-Part Skew tppskew, A-Y 5 ns Y A Translation RS = RT = 5 Ω, CL = 5 pf, Figure 3 Propagation Delay tp, Y-A 35 ns Rise Time tr, Y-A 5 ns Fall Time tf, Y-A.5.5 ns Maximum Data Rate DMAX, Y-A 5 Mbps Channel-to-Channel Skew tskew, Y-A 3.5 ns Part-to-Part Skew tppskew, Y-A 3.5 ns.5 V ±. V VCCA VCCY, VCCY = 3.3 V ±.3 V A Y Translation RS = RT = 5 Ω, CL = 5 pf, Figure 33 Propagation Delay tp, A-Y 7 ns Rise Time tr, A-Y.5 ns Fall Time tf, A-Y 5 ns Maximum Data Rate DMAX, A-Y Mbps Channel-to-Channel Skew tskew, A-Y.5 ns Part-to-Part Skew tppskew, A-Y ns Y A Translation RS = RT = 5 Ω, CL = 5 pf, Figure 3 Propagation Delay tp, Y-A 5 8 ns Rise Time tr, Y-A ns Fall Time tf, Y-A 3 5 ns Maximum Data Rate DMAX, Y-A Mbps Channel-to-Channel Skew tskew, Y-A 3 ns Part-to-Part Skew tppskew, Y-A 3 ns Rev. Page of

6 ADG33 Parameter Symbol Conditions Min Typ Max Unit POWER REQUIREMTS Power Supply Voltages VCCA VCCA VCCY V VCCY V Quiescent Power Supply Current ICCA VA = V/VCCA, VY = V/VCCY,.7 5 µa VCCA = VCCY = 5.5 V, = ICCY VA = V/VCCA, VY = V/VCCY,.7 5 µa VCCA = VCCY = 5.5 V, = Three-State Mode Power Supply Current IHiZA VCCA = VCCY = 5.5 V, =. 5 µa IHiZY VCCA = VCCY = 5.5 V, =. 5 µa Temperature range is a follows: B version: C to +85 C. All typical values are at TA = 5 C, unless otherwise noted. 3 Guaranteed by design; not subject to production test. Rev. Page 5 of

7 ADG33 ABSOLUTE MAXIMUM RATINGS TA = 5 C, unless otherwise noted. Table. Parameter Rating VCCA to.3 V to +7 V VCCY to VCCA to +7 V Digtal Inputs (A).3 V to (VCCA +.3 V) Digtal Inputs (Y).3 V to (VCCY +.3 V) to.3 V to +7 V Operating Temperature Range Industrial (B Version) C to +85 C Storage Temperature Range 5 C to +5 C Junction Temperature 5 C θja Thermal Impedance (-Layer Board) -Lead TSSOP 78 C/W Lead Temperature, Soldering ( sec) 3 C IR Reflow, Peak Temperature (< sec) C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. Page of

8 ADG33 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A Y 9 A A3 A 3 5 ADG33 TOP VIEW (Not to Scale) 8 7 Y Y3 Y A5 5 Y5 A 7 Y A7 8 3 Y7 A8 9 Y8 5- Figure. Pin Configuration Table 3. Pin Function Descriptions Pin. No. Mnemonic Description A Input/Output A. Referenced to VCCA. VCCA Power Supply Voltage Input for the A to A8 I/O pins (.5 V VCCA < VCCY). 3 A Input/Output A. Referenced to VCCA. A3 Input/Output A3. Referenced to VCCA. 5 A Input/Output A. Referenced to VCCA. A5 Input/Output A5. Referenced to VCCA. 7 A Input/Output A. Referenced to VCCA. 8 A7 Input/Output A7. Referenced to VCCA. 9 A8 Input/Output A8. Referenced to VCCA. Active High Enable Input. Ground. Y8 Input/Output Y8. Referenced to VCCY. 3 Y7 Input/Output Y7. Referenced to VCCY. Y Input/Output Y. Referenced to VCCY. 5 Y5 Input/Output Y5. Referenced to VCCY. Y Input/Output Y. Referenced to VCCY. 7 Y3 Input/Output Y3. Referenced to VCCY. 8 Y Input/Output Y. Referenced to VCCY. 9 VCCY Power Supply Voltage Input for the Y to Y8 I/O pins (.5 V VCCY 5.5 V). Y Input/Output Y. Referenced to VCCY. Rev. Page 7 of

9 ADG33 TYPICAL PERFORMANCE CHARACTERISTICS C L = 5pF = 3.3V, = 5V C L = 5pF I CCA (ma) =.8V, = 3.3V I CCY (ma).5..5 = 3.3V, = 5V =.8V, = 3.3V. =.V, =.8V DATA RATE (Mbps) 5-3 =.V, =.8V DATA RATE (Mbps) 5- Figure 3. ICCA vs. Data Rate (A Y Level Translation) Figure. ICCY vs. Data Rate (Y A Level Translation) I CCY (ma) C L = 5pF = 3.3V, = 5V =.8V, = 3.3V =.V, =.8V I CCY (ma) T A =5 C =.V =.8V Mbps Mbps 5Mbps Mbps DATA RATE (Mbps) Figure. ICCY vs. Data Rate (A Y Level Translation) Figure 7. ICCY vs. Capacitive Load at Pin Y for A Y (. V.8 V) Level Translation C L = 5pF = 3.3V, = 5V =.V =.8V I CCA (ma) DATA RATE (Mbps) =.8V, = 3.3V =.V, =.8V 5-5 I CCA (ma) Mbps Mbps 5Mbps Mbps Figure 5. ICCA vs. Data Rate (Y A Level Translation) Figure 8. ICCA vs. Capacitive Load at Pin A for Y A (.8 V. V) Level Translation Rev. Page 8 of

10 ADG =.8V = 3.3V 5Mbps 7 5 = 3.3V = 5V 5Mbps I CCY (ma) 5 3 5Mbps Mbps Mbps Mbps 5-9 I CCA (ma) 3 5Mbps Mbps Mbps Mbps 5- Figure 9. ICCY vs. Capacitive Load at Pin Y for A Y (.8 V 3.3 V) Level Translation Figure. ICCA vs. Capacitive Load at Pin A for Y A (5 V 3.3 V) Level Translation =.8V = 3.3V 9 8 DATA RATE = 5kbps =.V, =.8V I CCA (ma) Mbps 3Mbps RISE TIME (ns) 5 =.8V, = 3.3V.5 Mbps. Mbps.5 5Mbps = 3.3V, = 5V Figure. ICCA vs. Capacitive Load at Pin A for Y A (3.3 V.8 V) Level Translation Figure 3. Rise Time vs. Capacitive Load at Pin Y (A Y Level Translation) = 3.3V = 5V 5Mbps. 3.5 DATA RATE = 5kbps =.V, =.8V 3. I CCY (ma) 8 5Mbps Mbps Mbps Mbps 5- FALL TIME (ns) =.8V, = 3.3V = 3.3V, = 5V Figure. ICCY vs. Capacitive Load at Pin Y for A Y (3.3 V 5 V) Level Translation Figure. Fall Time vs. Capacitive Load at Pin Y (A Y Level Translation) Rev. Page 9 of

11 ADG33 RISE TIME (ns) DATA RATE = 5kbps =.V, =.8V =.8V, = 3.3V = 3.3V, = 5V 5-5 PROPAGATION DELAY (ns) 8 DATA RATE = 5kbps TA = 5 C =.V, =.8V =.8V, = 3.3V = 3.3V, = 5V 5-8 Figure 5. Rise Time vs. Capacitive Load at Pin A (Y A Level Translation) Figure 8. Propagation Delay (tphl) vs. Capacitive Load at Pin Y (A Y Level Translation). 3.5 DATA RATE = 5kbps 9 8 DATA RATE = 5kbps FALL TIME (ns) =.V, =.8V =.8V, = 3.3V = 3.3V, = 5V PROPAGATION DELAY (ns) =.8V, = 3.3V =.V, =.8V.5 = 3.3V, = 5V Figure. Fall Time vs. Capacitive Load at Pin A (Y A Level Translation) Figure 9. Propagation Delay (tplh) vs. Capacitive Load at Pin A (Y A Level Translation) 5-9 PROPAGATION DELAY (ns) 8 DATA RATE = 5kbps =.8V, = 3.3V =.V, =.8V = 3.3V, = 5V PROPAGATION DELAY (ns) DATA RATE = 5kbps =.8V, = 3.3V =.V, =.8V = 3.3V, = 5V Figure 7. Propagation Delay (tplh) vs. Capacitive Load at Pin Y (A Y Level Translation) Figure. Propagation Delay(tPHL) vs. Capacitive Load at Pin A (Y A Level Translation) Rev. Page of

12 ADG33 DATA RATE = 5Mbps C L = 5pF DATA RATE = 5Mbps C L = 5pF mv/div 5ns/DIV 5- mv/div 3ns/DIV 5- Figure. Eye Diagram at Y Output (. V to.8 V Level Translation, 5 Mbps) Figure. Eye Diagram at A Output (3.3 V to.8 V Level Translation, 5 Mbps) DATA RATE = 5Mbps C L = 5pF DATA RATE = 5Mbps CL = 5pF mv/div 5ns/DIV 5- V/DIV 3ns/DIV 5-5 Figure. Eye Diagram at A Output (.8 V to. V Level Translation, 5 Mbps) Figure 5. Eye Diagram at Y Output (3.3 V to 5 V Level Translation, 5 Mbps) DATA RATE = 5Mbps C L = 5pF DATA RATE = 5Mbps C L = 5pF 5mV/DIV 3ns/DIV 5-3 8mV/DIV 3ns/DIV 5- Figure 3. Eye Diagram at Y Output (.8 V to 3.3 V Level Translation, 5 Mbps) Figure. Eye Diagram at A Output (5 V to 3.3 V Level Translation, 5 Mbps) Rev. Page of

13 A ADG33 TEST CIRCUITS ADG33.µF.µF ADG33 A Y K.µF.µF K A Y I OH I OL K A Figure 7. VOH/VOL Voltages at Pin A Figure 3. Pin Leakage Current ADG33 ADG33.µF.µF K Y A Y K CAPACITANCE METER I OH I OL Figure 3.Capacitance at Pin Y Figure 8. VOH/VOL Voltages at Pin Y ADG33.µF.µF A Y A K 5-3 Figure 9. Three-State Leakage Current at Pin Y Rev. Page of

14 ADG33.µF + µf ADG33 +.µf µf MΩ SIGNAL SOURCE K V A A Y 5pF V Y K MΩ R S Z = 5Ω V 5Ω RT 5Ω V V A 9% V Y t V V V V V A t V V Y % NOTES. t IS WHICHEVER IS LARGER BETWE t AND t. Figure 3. Enable Time V V 5-3 SIGNAL SOURCE +.µf µf ADG33 R S 5Ω Z = 5Ω V A RT 5Ω Y A +.µf µf +.µf µf ADG33 SIGNAL SOURCE V Y 5pF V A 5pF Y A +.µf µf V Y R T 5Ω Z = 5Ω R S 5Ω V A V Y 5% 5% 9% 5% % V Y t P,A-Y t F,A-Y t P,A-Y t R,A-Y % 5% % V A t P,Y-A t F,Y-A t P,Y-A t R,Y-A 5-3 Figure 33. Switching Characteristics (A Y Level Translation) Figure 3. Switching Characteristics (Y A Level Translation) Rev. Page 3 of

15 ADG33 TERMINOLOGY Table. Symbol Description VIHA Logic input high voltage at Pins A to A8. VILA Logic input low voltage at Pins A to A8. VOHA Logic output high voltage at Pins A to A8. VOLA Logic output low voltage at Pins A to A8. RA,HiZ Pull-down resistance measured at Pins A to A8 when =. VIHY Logic input high voltage at Pins Y to Y8. VILY Logic input low voltage at Pins Y to Y8. VOHY Logic output high voltage at Pins Y to Y8. VOLY Logic output low voltage at Pins Y to Y8. CY Capacitance measured at Pins Y to Y8 ( = ). ILY, HiZ Leakage current at Pins Y to Y8 when = (high impedance state at Pins Y to Y8). VIH Logic input high voltage at the pin. VIL Logic input low voltage at the pin. C Capacitance measured at pin. IL Enable () pin leakage curent. t Three-state enable time for Pins Y to Y8. tp, A-Y Propagation delay when translating logic levels in the A Y direction. tr, A-Y Rise time when translating logic levels in the A Y direction. tf, A-Y Fall time when translating logic levels in the A Y direction. DMAX, A-Y Guaranteed data rate when translating logic levels in the A Y direction under the driving and loading conditions specified in Table. tskew, A-Y Difference between propagation delays on any two channels when translating logic levels in the A Y direction. tppskew, A-Y Difference in propagation delay between any one channel and the same channel on a different part (under the same driving/loading conditions) when translating logic levels in the A Y direction. tp, Y-A Propagation delay when translating logic levels in the Y A direction. tr, Y-A Rise time when translating logic levels in the Y A direction. tf, Y-A Fall time when translating logic levels in the Y A direction. DMAX, Y-A Guaranteed data rate when translating logic levels in the Y A direction under the driving and loading conditions specified in Table. tskew, Y-A Difference between propagation delays on any two channels when translating logic levels in the Y A direction. tppskew, Y-A Difference in propagation delay between any one channel and the same channel on a different part (under the same driving/loading conditions) when translating in the Y A direction. VCCA VCCA supply voltage. VCCY VCCY supply voltage. ICCA VCCA supply current. ICCY VCCY supply current. IHiZA VCCA supply current during three-state mode ( = ). IHiZY VCCY supply current during three-state mode ( = ). Rev. Page of

16 ADG33 THEORY OF OPERATION The ADG33 level translator allows the level shifting necessary for data transfer in a system where multiple supply voltages are used. The device requires two supplies, VCCA and VCCY (VCCA VCCY). These supplies set the logic levels on each side of the device. When driving the A pins, the device translates the VCCAcompatible logic levels to VCCY-compatible logic levels available at the Y pins. Similarly, since the device is capable of bidirectional translation, when driving the Y pins, the VCCY-compatible logic levels are translated to VCCA-compatible logic levels available at the A pins. When =, the A to A8 are internally pulled down with kω resistors while Y to Y8 pins are three-stated. When is driven high, the ADG33 goes into normal operation mode and performs level translation. LEVEL TRANSLATOR ARCHITECTURE The ADG33 consists of eight bidirectional channels. Each channel can translate logic levels in either the A Y or the Y A direction. It uses a one-shot accelerator architecture, which ensures excellent switching characteristics. Figure 35 shows a simplified block diagram of a bidirectional channel. INPUT DRIVING REQUIREMTS To ensure correct operation of the ADG33, the circuit that drives the input of an ADG33 channels should have an output impedance of less than or equal to 5 Ω and a minimum current driving capability of 3 ma. OUTPUT LOAD REQUIREMTS The ADG33 level translator is designed to drive CMOScompatible loads. If current driving capability is required, it is recommended to use buffers between the ADG33 outputs and the load. ABLE OPERATION The ADG33 provides three-state operation at the Y I/O pins by using the enable () pin as shown in Table 5. Table 5. Truth Table Y I/O Pins A I/O Pins Hi-Z kω pull-down to Normal operation Normal operation High impedance state. In normal operation, the ADG33 performs level translation. A T T kω U U kω P ONE-SHOT GERATOR N U U3 Figure 35. Simplified Block Diagram of an ADG33 Channel The logic level translation in the A Y direction is performed using a level translator (U) and an inverter (U), and the translation in the Y A direction is performed using the inverters U3 and U. The one-shot generator detects a rising or falling edge present on either the A side or the Y side of the channel. It sends a short pulse that turns on the PMOS transistors (T T) for a rising edge, or the NMOS transistors (T3 T) for a falling edge. This charges/discharges the capacitive load faster, which results in fast rise and fall times. T T3 Y 5-37 When =, the ADG33 enters into three-state mode. In this mode the current consumption from both the VCCA and VCCY supplies is reduced, allowing the user to save power, which is critical, especially for battery-operated systems. The input pin can be driven with either VCCA- or VCCY-compatible logic levels. POWER SUPPLIES For proper operation of the ADG33, the voltage applied to the VCCA must always be less than or equal to the voltage applied to VCCY. To meet this condition, the recommended power-up sequence is VCCY first and then VCCA. The ADG33 operates properly only after both supply voltages reach their nominal values. It is not recommended to use the part in a system where VCCA might be greater than VCCY during power-up due to a significant increase in the current taken from the VCCA supply. For optimum performance, the VCCA and VCCY pins should be decoupled to as close as possible to the device. The inputs of the unused channels (A or Y) should be tied to their corresponding VCC rail (VCCA or VCCY) or to. Rev. Page 5 of

17 ADG33 DATA RATE The maximum data rate at which the device is guaranteed to operate is a function of the VCCA and VCCY supply voltage combination and the load capacitance. It is given by the maximum frequency of a square wave that can be applied to the device, which meets the VOH and VOL levels at the output and does not exceed the maximum junction temperature (see Table ). Table shows the guaranteed data rates at which the ADG33 can operate in both directions (A Y and Y A level translation) for various VCCA and VCCY supply combinations. Table. Guaranteed Data Rate (Mbps) VCCA.8 V (.5 V to.95 V).5 V (.3 V to.7 V) VCCY 3.3 V (3. V to 3. V) 5 V (.5 V to 5.5 V). V (.5 V to.3 V) V (.5 V to.95 V) V (.3 V to.7 V) V (3. V to 3. V) V (.5 V to 5.5 V) The load capacitance used is 5 pf when translating in the A Y direction and 5 pf when translating in the Y A direction. Rev. Page of

18 ADG33 APPLICATIONS The ADG33 is designed for digital circuits that operate at different supply voltages; therefore, logic level translation is required. The lower voltage logic signals are connected to the A pins, and the higher voltage logic signals are connected to the Y pins. The ADG33 can provide level translation in both directions from A Y and Y A on all eight channels, eliminating the need for a level translator IC for each direction. The internal architecture allows the ADG33 to perform bidirectional level translation without an additional signal to set the direction of the translation. It also allows simultaneous data flow in both directions on the same part, for example, four channels translate in the A Y direction while the other four translate in the Y A direction. This simplifies the design by eliminating the timing requirements for the direction signal and reduces the number of ICs used for level translation. other devices without causing contention issues. Figure 37 shows an application where a 3.3 V microprocessor is connected to.8 V peripheral devices using the three-state feature. 3.3V I/O H Y A I/O L.8V MICROPROCESSOR/ I/O H MICROCONTROLLER/ I/O DSP H 5 I/O H CS I/O H I/O H 3 I/O H 7 I/O H 8 nf nf Y Y3 A3 ADG33 Y A Y5 Y Y7 Y8 A A5 A A7 A8 nf nf I/O L I/O L 3 I/O L I/O L 5 I/O L I/O L 7 I/O L 8 PERIPHERAL DEVICE Figure 3 shows an application where a.8 V microprocessor can read or write data to or from a 3.3 V peripheral device using an 8-bit bus. nf nf Y A Y A Y3 A3 ADG33 Y A Y5 A5 Y A Y7 A7 I/O L I/O L I/O L 3 I/O L I/O L 5 I/O L I/O L 7.8V PERIPHERAL DEVICE.8V I/O L A Y I/O H 3.3V Y8 A8 I/O L I/O L I/O L 3 A A3 Y Y3 I/O H I/O H 3 Figure V to 3.3 V Level Translation Circuit Using the Three-State Feature MICROPROCESSOR/ I/O L MICROCONTROLLER/ DSP I/O L 5 I/O L I/O L 7 I/O L 8 A Y ADG33 A5 A A7 A8 Y5 Y Y7 Y8 I/O H I/O H 5 I/O H I/O H 7 I/O H 8 Figure 3..8 V to 3.3 V 8-Bit Level Translation Circuit PERIPHERAL DEVICE When the application requires level translation between a microprocessor and multiple peripheral devices, the ADG33 Y I/O pins (Y to Y8) can be three-stated by setting =. This feature allows the ADG33 to share the data buses with 5-38 LAYOUT GUIDELINES As with any high speed digital IC, the printed circuit board layout is important in the overall circuit performance. Care should be taken to ensure proper power supply bypass and return paths for the high speed signals. Each VCC pin (VCCA and VCCY) should be bypassed using low effective series resistance (ESR) and effective series inductance (ESI) capacitors placed as close as possible to the VCCA and VCCY pins. The parasitic inductance of the high speed signal track might cause significant overshoot. This effect can be reduced by keeping the length of the tracks as short as possible. A solid copper plane for the return path () is also recommended. Rev. Page 7 of

19 ADG33 OUTLINE DIMSIONS BSC PIN.5.5 COPLANARITY..5 BSC.3.9. MAX SEATING PLANE.5 COMPLIANT TO JEDEC STANDARDS MO-53AC Figure 38. -Lead Thin Shrink Small Outline Package [TSSOP] (RU-) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option ADG33BRUZ C to +85 C TSSOP RU- ADG33BRUZ-REEL C to +85 C TSSOP RU- ADG33BRUZ-REEL7 C to +85 C TSSOP RU- Z = Pb-free part. Rev. Page 8 of

20 ADG33 NOTES Rev. Page 9 of

21 ADG33 NOTES 5 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D5 /5() Rev. Page of