Evaluating RISC-V Cores for PULP

Transcription

1 Evaluating RISC-V Cores for PULP An Open Parallel Ultra-Low-Power Platform 30 June 2015 Sven Stucki Antonio Pullini Michael Gautschi Frank K. Gürkaynak Andrea Marongiu Igor Loi Davide Rossi Prof. Luca Benini

2 Summary Background The group PULP platform Goals Our approach RISC-V on PULP Integrated Systems Laboratory 2

3 The Group of Prof. Luca Benini Approximately 40 people ETH Zürich Integrated Systems Laboratory (IIS) University of Bologna EEES Many involved in PULP Great experience in IC design More than 400 ICs, in-house ASIC tester Close Collaborations POLIMI (compiler support) CEA/LETI EPFL Integrated Systems Laboratory 3

4 Integrated 4 Systems Laboratory 4 Our Goal: Reach 1 GOPS/mW efficiency ops/j 1pJ/op 1GOPS/mW [RuchIBM11]

5 Energy Proportionality log(mw) 0,003GOPS/mW 30KW 0,03GOPS/mW 1GOPS/mW log(gops) Integrated Systems Laboratory 5

6 PULP An open research platform Goals: Reach 1 GOPS/mW efficiency Scalable hardware: Achieve energy proportionality Research on: Efficient cores, platform innovations Technology options Software support Integrated Systems Laboratory 6

7 Our Approach: PULP Exploit parallelism Multiple small cores organized in a cluster Share memory within the cluster Simple but efficient processor cores Currently: OpenRISC with ISA extensions RISC-V Minion core in the work Hardware optimizations Near-threshold operation Dedicated accelerators Integrated Systems Laboratory 7

8 PULP Family of Chips Silicon proven in 28nm Several tape-outs in different technologies 180nm (IcySoC project, approximate computing) 130nm (Mixed-signal PULP: Vivo-SOC) 65nm (Student projects, demonstrators) 28nm (Flagship designs, technology options) Timeline: Integrated Systems Laboratory 8

9 RISC-V on PULP Replace OpenRISC with RISC-V core Motivation More active community Compressed instruction set Current status: Simple 4-stage (IF, ID, EX, WB) design Support for RV32IC mul instruction from M extension UMC65: 22 kge for t pd = 1.08V Privileged features: M-mode, Mbare memory Integrated Systems Laboratory 9

10 RVC: Big impact on code size Integrated Systems Laboratory 10

11 PULP Architecture Integrated Systems Laboratory 12

12 Tightly Coupled Data Memory (TCDM) Cluster-local data storage, explicitly managed Single-cycle access without contention Integrated Systems Laboratory 13

13 Instruction Cache Exploit parallelism: shared between cores Integrated Systems Laboratory 14

14 System on Chip Frequency-locked loop (FLL) Memory, (I/O) Peripherals, ROM, Integrated Systems Laboratory 15

15 Improved OpenRISC: OR10N Core OpenRISC core developed at IIS ISA extensions to improve efficiency Hardware Loops Pre-/Postincrement memory access Vectorial (packed SIMD) instructions Custom llvm compiler No changes to C code needed to use new instructions Debugging support Integrated Systems Laboratory 16

16 RISC-V on PULP: Future Work Tapeout in 4Q2015 GlobalFoundries 28nm Evaluate OR10N extensions for RV core Hardware loops: Smaller impact on RV Vectorial instructions We are open for suggestions / collaborations Integrated Systems Laboratory 17

17 QUESTIONS? Integrated Systems Laboratory 18

18 OR10N Extensions Performance Gain Integrated Systems Laboratory 19

19 OR10N Extensions Power Improvement Integrated Systems Laboratory 20

20 Near Threshold Operation More Efficient Higher energy efficiency Sub- Near- Super-Threshold Actual PULP Measurement Results Integrated Systems Laboratory 21

21 performance scalable by ~300x PULP v2: Best in Class power scalable by ~2000x PULP many operating points provided by VBB and VDD knobs 211 GOPS/W near-threshold MCUs commercial low-power MCUs multicore ULP platforms commercial ARM processors sub-threshold MCUs Integrated Systems Laboratory 22

22 performance scalable by ~300x PULP v2: Best in Class power scalable by ~2000x PULP near-threshold MCUs 211 GOPS/W multicore ULP platforms commercial ARM processors commercial low-power MCUs sub-threshold MCUs Integrated Systems Laboratory 23