INSTITUTO SUPERIOR TÉCNICO. Architectures for Embedded Computing

Transcription

1 UNIVERSIDADE TÉCNICA DE LISBOA INSTITUTO SUPERIOR TÉCNICO Departamento de Engenharia Informática for Embedded Computing MEIC-A, MEIC-T, MERC Lecture Slides Version English Lecture 22 Title: and Extended Summary: architectures - Application Specific Instruction-set Processors (ASIPs); extensions - Instruction Set Architecture (ISA) extensions. 2010/2011 Nuno.Roma@ist.utl.pt

2 for Embedded Computing and Extended Prof. Nuno Roma ACE 2010/11 - DEI-IST 1 / 54 Previous Class In the previous class... Microcontrollers Smart-Cards Prof. Nuno Roma ACE 2010/11 - DEI-IST 2 / 54

3 Road Map Prof. Nuno Roma ACE 2010/11 - DEI-IST 3 / 54 Summary Today: architectures: Application Specific Instruction-set Processors (ASIPs) extensions: Instruction Set Architecture (ISA) extensions Prof. Nuno Roma ACE 2010/11 - DEI-IST 4 / 54

4 and Extended architectures: Implemented by adapting already existing cores (Ex: Leon, MIPS, etc.); The main objective is to optimize a very specific application; Fulfilled through dedicated processors (ASIPs); Somewhat flexible, but not much! to architectures: Try to optimize a wider diversity of applications; Defined by the manufacturers when they plan a new architecture; Included, at production time, in the new processors; Implemented using Instruction Set Architecture (ISA) extensions; Little flexibility. Prof. Nuno Roma ACE 2010/11 - DEI-IST 5 / 54 Prof. Nuno Roma ACE 2010/11 - DEI-IST 6 / 54

5 Introduction Prof. Nuno Roma ACE 2010/11 - DEI-IST 7 / 54 Introduction Once upon a time... Prof. Nuno Roma ACE 2010/11 - DEI-IST 8 / 54

6 Introduction Data Encryption Standard (DES) Prof. Nuno Roma ACE 2010/11 - DEI-IST 9 / 54 Introduction The SW engineer very proudly presented Prof. Nuno Roma ACE 2010/11 - DEI-IST 10 / 54

7 Introduction The HW engineer laughed Prof. Nuno Roma ACE 2010/11 - DEI-IST 11 / 54 Introduction The HW engineer presented Prof. Nuno Roma ACE 2010/11 - DEI-IST 12 / 54

8 Introduction The SW engineer laughed Prof. Nuno Roma ACE 2010/11 - DEI-IST 13 / 54 Introduction Realizing that they each had something the other wanted Prof. Nuno Roma ACE 2010/11 - DEI-IST 14 / 54

9 Introduction They decided to work together Prof. Nuno Roma ACE 2010/11 - DEI-IST 15 / 54 Introduction and improved the SW solution by 70x Prof. Nuno Roma ACE 2010/11 - DEI-IST 16 / 54

10 Introduction When the boss asked how, the SW engineer said: Prof. Nuno Roma ACE 2010/11 - DEI-IST 17 / 54 Introduction and the HW engineer said: Prof. Nuno Roma ACE 2010/11 - DEI-IST 18 / 54

11 Introduction Together, they had the best of both world Prof. Nuno Roma ACE 2010/11 - DEI-IST 19 / 54 Introduction The boss was very happy Prof. Nuno Roma ACE 2010/11 - DEI-IST 20 / 54

12 Introduction And they worked together happily ever after Prof. Nuno Roma ACE 2010/11 - DEI-IST 21 / 54 Motivation Characteristics of embedded systems: The project is focused on cost minimization; Great production volumes; Rapid evolution of the supporting technology; Very short Time-to-Market. Objective - design architectures that offer: Support for several applications of the same type; Possibility to evolve together with the application; Design and implement in a very short period; Low cost. Prof. Nuno Roma ACE 2010/11 - DEI-IST 22 / 54

13 Motivation Two possible approaches: I - Programmed application using microprocessors, thus offering a great capacity to adapt to the target application: General Purpose Processors (GPPs); Digital Signal Processors (DSPs); Microcontrollers. Prof. Nuno Roma ACE 2010/11 - DEI-IST 23 / 54 Motivation Two possible approaches: II - systems specifically designed for the targeted application, by making use of dedicated integrated circuits - ASICs: Application Specific Integrated Circuits: The engineer fully designs and implements the circuit, targeting the intended application; The efficiency is maximized: Great design effort; Long design cycles; The solution is usually not flexible, offering a very limited capability to be re-used in other applications. Prof. Nuno Roma ACE 2010/11 - DEI-IST 24 / 54

14 Motivation Several systems have tried to incorporate the advantages of these two approaches, by combining the flexibility of a microprocessor with the efficiency of a high performance ASIC to execute the most complex tasks. ASIP: Application-Specific Instruction-set Processor Prof. Nuno Roma ACE 2010/11 - DEI-IST 25 / 54 Motivation Embedded systems: great variety of adopted solutions... Prof. Nuno Roma ACE 2010/11 - DEI-IST 26 / 54

15 What is an ASIP? ASIP: Application-Specific Instruction-set Processor Architecture particularly adapted for specific sets of applications (e.g.: audio, control, encryption, etc.) Characteristics: Greater development costs; Much greater performance, with lower energy consumption (more efficient) than general purpose processors; Much more flexible than ASICs. Prof. Nuno Roma ACE 2010/11 - DEI-IST 27 / 54 What is an ASIP? Comparison between: GPP vs. ASIP vs. ASIC: GPP ASIP ASIC Performance Low High Very High Flexibility Very High Good Low HW Design Effort None Big Very Big SW Design Effort Little Big None Energy Consumption High Medium Low Re-Usage Excellent Great Little Market Very Large Large Small Cost Medium (SW) High (SW+HW) Very High (HW) Prof. Nuno Roma ACE 2010/11 - DEI-IST 28 / 54

16 ASIP Design OBJECTIVE: Given a particular set of applications, conceive a micro-architecture that best adapts to such applications: Set of dedicated instructions (ISA extension); Design of dedicated functional units; It is necessary to re-compile the application SW by considering these extensions/optimizations, in order to take the maximum advantage of the ASIP. The processor micro-architecture is now a project parameter!!! Prof. Nuno Roma ACE 2010/11 - DEI-IST 29 / 54 ASIP Design Design phases of an ASIP: Prof. Nuno Roma ACE 2010/11 - DEI-IST 30 / 54

17 ASIP Design Design phases of an ASIP: I - Original application: The application is programmed in C/C++; Great amount of code; Only a small code section is responsible for most processing time. II - Software manipulation: Simulation, profiling and analysis of the original software execution; Identification of the most critical code segments. Prof. Nuno Roma ACE 2010/11 - DEI-IST 31 / 54 ASIP Design Design phases of an ASIP: III - Architecture adaptation: A GPP core (e.g.: RISC) is adopted as the base architecture; The original instruction set is extended with new dedicated instructions to increase the application performance and reduce the energy consumption; The new instructions are implemented with dedicated functional units and integrated in the original processor: Inclusion of the unit in the original datapath (implies some changes in the decoding unit); Inclusion of the unit as a co-processor (invocation with load/store instructions). Prof. Nuno Roma ACE 2010/11 - DEI-IST 32 / 54

18 ASIP Design Design phases of an ASIP: III - Architecture adaptation (cont.): The critical code sections are re-encoded and replaced by sections that are implemented using the new dedicated instructions; The compiler is adapted in order to support the extended set of instructions. IV - Evaluation of the new architecture: Performance analysis of the modified architecture: Execution cycles; Clock frequency; Energy consumption. Prof. Nuno Roma ACE 2010/11 - DEI-IST 33 / 54 Example of an ASIP AMEP: Adaptive H.264/AVC Motion Estimation Processor for Mobile and Battery Supplied Devices PC M U X 0 Σ 1 RAM (Firmware) M U X M U X Instruction Decoding R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31... Negative Zero SADU AGU M U X M U X... MB SA MEM MEM AGU ASR Σ SADU ALU M U X M U X... Opcode Mnemonic Instruction Category LD Memory data transfer opcode t J Control opcode cc - address 010 MOVR Register data transfer opcode Rd - Rs 011 MOVC Register data transfer opcode t Rd constant 100 SAD16 Graphics opcode - Rd Rs1 Rs2 101 DIV2 Arithmetic opcode - Rd Rs ADD Arithmetic opcode - Rd Rs1 Rs2 111 SUB Arithmetic opcode - Rd Rs1 Rs2 Prof. Nuno Roma ACE 2010/11 - DEI-IST 34 / 54

19 Example of an ASIP AMEP: Adaptive H.264/AVC Motion Estimation Processor for Mobile and Battery Supplied Devices Speed-up: 1,2 1 ARM ASIP MB proc time [ms] 0,8 0,6 0,4 0,2 0 Bream Carphone Foreman Mobile Table-Tennis Prof. Nuno Roma ACE 2010/11 - DEI-IST 35 / 54 Other ASIP examples Other application examples of ASIPs: Encryption / Decryption; Communications: Modulation; Networks; Signal processing: Fast Fourier Transform (FFT); Convolution; Video coding: Discrete Cosine Transform (DCT); Motion estimation; Entropy encoding (VLC, CABAC, etc.); etc., etc., etc.... Prof. Nuno Roma ACE 2010/11 - DEI-IST 36 / 54

20 Prof. Nuno Roma ACE 2010/11 - DEI-IST 37 / 54 Instruction Set Architecture Instruction Set Architecture (ISA): Interface between the hardware and the software; Specifies: Instructions; Addressing modes; Registers. CISC vs RISC: In the beginning... there was CISC: The low-level programming model (Assembly) used to be the most often adopted; Scarce memory space. After the introduction of RISCs, in the 1970 s: Simple instructions; Pipelining. Prof. Nuno Roma ACE 2010/11 - DEI-IST 38 / 54

21 ISA Objectives: Increase the processors performance and efficiency; Include new useful instructions for specific application domains; Optimize frequently used (semi-)complex operations; Solution: Single Instruction, Multiple Data (SIMD) Examples: Matrices manipulations; Image and video processing, etc. Prof. Nuno Roma ACE 2010/11 - DEI-IST 39 / 54 Single Instruction, Multiple Data (SIMD) The human perception limitations do not allow us to take full advantage of the huge precision levels offered by current processors (64-bits, 128-bits); To avoid wasting the computational resources offered by the ALUs (64-bits, 128-bits) whenever the processed data have lower dynamic range (8-bits, 16-bits), several ISA extensions have been proposed that allow the simultaneous processing of several lower-precision operands: Single-Instruction Multiple-Data (SIMD) Example: A0 A1 A2 A3 A4 A5 A6 A7 + B0 B1 B2 B3 B4 B5 B6 B7 = A0+B0 A1+B1 A2+B2 A3+B3 A4+B4 A5+B5 A6+B6 A7+B7 Prof. Nuno Roma ACE 2010/11 - DEI-IST 40 / 54

22 Single Instruction, Multiple Data (SIMD) Examples: Prof. Nuno Roma ACE 2010/11 - DEI-IST 41 / 54 MMX: Matrix Math Extentions Introduced by Intel, in 1997; Acceleration of multimedia applications; 8 new 64-bit SIMD registers: MM0 to MM7; Packed Data Types: Prof. Nuno Roma ACE 2010/11 - DEI-IST 42 / 54

23 MMX: Matrix Math Extentions Shares the same registers with the floating-point unit; 57 new SIMD instructions; Only operates with integers. Prof. Nuno Roma ACE 2010/11 - DEI-IST 43 / 54 MMX: Matrix Math Extentions Examples: PADD PMADDWD Prof. Nuno Roma ACE 2010/11 - DEI-IST 44 / 54

24 3DNow! Developed by AMD, in 1998; Emergence of 3D games; AMD K6 processor presented an unsatisfactory performance with floating-point operations; Objective: Expand MMX to floating-point operations; 3DNow! includes 21 new instructions: Floating-point and fixed-point SIMD operations; Switching between the MMX modes and floating-point; Data prefetching into L1 cache. Enhanced 3DNow!: 24 additional instructions. 3DNow! Professional: Merge between the 3DNow! extension and the Intel SSE extension. Prof. Nuno Roma ACE 2010/11 - DEI-IST 45 / 54 SSE: Streaming SIMD Developed by Intel, with the introduction of Pentium III, in 1997; Acceleration of 3D multimedia and floating-point applications; 8 new 128-bit registers (XMM0 to XMM7), independent of MMX registers; Floating-point Packed Data Types; 70 new instructions: Floating-point operations; Integer operations; Memory management. Prof. Nuno Roma ACE 2010/11 - DEI-IST 46 / 54

25 SSE2: Streaming SIMD Developed by Intel, with Pentium IV, in 2001; Acceleration of multimedia applications (3D graphics, video and audio encoding (MPEG)); Extension of MMX operations; Introduce XMM registers; Floating-point registers become exclusive to the FPU; 144 new instructions: Format conversion; Cache control; Example: CLFLUSH - flushes the addressed position from all levels of the cache hierarchy. Prof. Nuno Roma ACE 2010/11 - DEI-IST 47 / 54 (S)SSE3: Streaming SIMD Developed by Intel, in 2004; Incremental evolution, when compared with the SSE extension; 13 new instructions: Operations over complex numbers; Application: signal processing (FFT); Horizontal operations - act over the several packed elements of the same register; Application: vectorial processing; Thread optimization operations: Application: Hyper-Threading. SSSE3: Supplemental Streaming SIMD 16 new horizontal instructions. Prof. Nuno Roma ACE 2010/11 - DEI-IST 48 / 54

26 SSE4: Streaming SIMD Developed in 2006, with Intel Core e AMD K10 processors; 47 new instructions: Multimedia operations; Web servers operations; Text/string processing operations; Search operations; Data-mining operations; Compression operations; etc. Prof. Nuno Roma ACE 2010/11 - DEI-IST 49 / 54 SSE5: Streaming SIMD Proposed by AMD, available in 2011; 170 new instructions: 3-operand operations; Application: Video coding (DCT) and encryption (AES). Prof. Nuno Roma ACE 2010/11 - DEI-IST 50 / 54

27 AVX: Advanced Vector Proposed by Intel, available in 2011; End of the SSE extensions generation; Updates 200 instructions; Proposes 100 new instructions; 256-bits registers. Prof. Nuno Roma ACE 2010/11 - DEI-IST 51 / 54 Current Situation Very wide set of available instructions; Approximation to the old CISC architecture paradigm; Applications: Cryptography; Virtualization: Security; Memory protection; Video coding: Motion estimation; Discrete Cosine Transform (DCT); etc., etc., etc. Prof. Nuno Roma ACE 2010/11 - DEI-IST 52 / 54

28 Prof. Nuno Roma ACE 2010/11 - DEI-IST 53 / 54 Digital input/output: Memory mapped / Input & Output Pooling Interruptions Timers: Real-time clocks Watchdog timers Actuators and control signal generators: Pulse Width Modulators (PWM) Signal acquisition and conversion: Digital-to-Analog Converters (DAC) Analog-to-Digital Converters (ADC) Digital input and output Prof. Nuno Roma ACE 2010/11 - DEI-IST 54 / 54