Extending Fixed Subsystems at the TLM Level: Experiences from the FPGA World

Transcription

1 I N V E N T I V E Extending Fixed Subsystems at the TLM Level: Experiences from the FPGA World Frank Schirrmeister, Steve Brown, Larry Melling (Cadence) Dave Beal (Xilinx)

2 Agenda Virtual Platforms Xilinx Zynq Why TLM Extensibility Matters Example: Extending a Virtual Platform Example Results & Summary 2

3 Software Defines User Experiences Source: TI, Smart Technology Conference, San Francisco, 2011

4 Specific User Challenges System Development Suite How do I develop hardware aware software? How do I develop application software early? How do I integrate the SoC? How do I integrate IP and Blocks and Sub-systems? How do I do hardware/software validation in the system context?

5 What is a Virtual Platform? AKA: Virtual System Platform, Virtual Prototype, Virtual Target Is a fast functional model of an embedded platform (real or envisaged) Comprised of an instruction set simulator and models of a set of devices on the silicon or on the board Executes the same software binaries as the actual hardware Runs on traditional desktops, laptops or servers A Virtual Platform looks like real hardware to its OS and applications 5

6 Agenda Virtual Platforms Xilinx Zynq Why TLM Extensibility Matters Example: Extending a Virtual Platform Example Results & Summary 6

7 Xilinx Zynq Extensible Processing Platform 7

8 Typical SoC-based Product Development flow Start with an off-the-shelf reference design Software Port OS kernel and drivers Write some applications Hardware Design custom board Wait for custom hardware to appear Write custom device drivers Write platform-specific applications Integrate & Test

9 FPGA: Software Development Work-Flow An FPGA allows designers to include custom-silicon devices Design custom silicon IP within FPGA + Wait for FPGA programming to finish Write custom board-based device drivers Write some platform-specific applications Integrate & Test 9

10 Extending a FPGA-based Virtual Platform Extend with Real FPGA Hardware in the Loop Post-silicon FPGA code must be finished Requires host computer plug-in board Limitations on system stop & debug Breaks VP/HW binary compatibility Extend with VHDL or RTL Emulator or simulator Post-silicon FPGA code must be finished Moderate to very expensive Extend with Custom High Level Models Pre-silicon Requires model development Typically fastest schedule and least effort SystemC or C models can be used to generate the function in silicon 10

11 Zynq-7000 EPP Virtual Platform Zynq-7000 EPP Virtual Platform Memory Real-World Interfaces Processing System Peripherals UART USB I2C Ethernet CAN GPIO SDIO SPI Graphics/ Display Memory Controller Cortex -A9 MPCore M I O Programmable Logic PCIe The Zynq-7000 EPP Extensible Virtual Platform A fast instruction set simulator for the ARM Cortex -A9 MPCore processor ARM ISA, NEON SIMD, VFPv3, Thumb, Thumb2, Jazelle Correct register interfaces for all SoC devices Functionality modeled for Zynq EPP and on-board devices 11

12 Agenda Virtual Platforms Xilinx Zynq Why TLM Extensibility Matters Example: Extending a Virtual Platform Example Results & Summary 12

13 Average of Real Chip Project Examples Across 12 Projects Percentage of Project Effort Application Software Development (30% effort, 72% time) Specification Development RTL Development OS Support Utility Software Development (13%, 54%) Design Management (10%, 74%) RTL Verification to Netlist (21%, 55%) Netlist to Tapeout (9%, 56%) Post Silicon Validation Qualification of IP (11%,45%) Elapsed time as percentage of time from RTL Development to Tapeout 13 Source: IBS, Cadence

14 Average of Real Chip Project Examples Across 12 Projects Percentage of Project Effort Virtual Prototyping Specification Development RTL Development OS Support Utility Software Development (13%, 54%) FPGA Based Prototyping Design Management (10%, 74%) Application Software Development (30% effort, 72% time) RTL Simulation Emulation Acceleration RTL Verification to Netlist (21%, 55%) Netlist to Tapeout (9%, 56%) Post Silicon Validation Qualification of IP (11%,45%) Elapsed time as percentage of time from RTL Development to Tapeout Source: IBS, Cadence

15 Why TLM Extensibility Matters Zynq can be extended, customized by about 430K 5.2M custom gate equivalents RTL development takes significant time Verification takes even more effort & time TLM development effort lower, faster Software development can start months earlier, even for FPGA case improved productivity with improved debug efficiency 15

16 Agenda Virtual Platforms Xilinx Zynq Why TLM Extensibility Matters Example: Extending a Virtual Platform Example Results & Summary 16

17 Customizing the Zynq-7000 EPP Extensible Virtual Platform Start with the off-the-shelf virtual platform Zynq-7000 EPP Virtual Platform Memory Real-World Interfaces Processing System Memory Controller Programmable Logic Peripherals UART USB I2C Ethernet CAN GPIO SDIO SPI Cortex -A9 MPCore M I O PCIe Graphics/ Display 17 Page 17

18 Customizing the Zynq-7000 EPP Extensible Virtual Platform Customize to model your product design Zynq-7000 EPP Virtual Platform Real-World Interfaces Processing System Peripherals UART USB I2C Ethernet CAN GPIO SDIO SPI Graphics/ Display Memory Controller Cortex -A9 MPCore M I O Memory Custom C Model Custom TLM Model Programmable Logic Custom TLM Model Custom TLM Model Custom TLM Model Custom C Model PCIe Use System Creator to: Model devices or accelerators within the Zynq programmable logic, or discrete devices soldered onboard Develop models in C, C++ and SystemC SC Tools for Model Development: View static and dynamic model variables Log Virtual Platform activities SC Tools for simultaneous Model & Target Development: Display all model sub-component parameters -static and dynamic Correlate the executing Zynq LOC to the executing model LOC View model timing and transaction sequence information correlated to executing Zynq LOC 18 Page 18

19 Virtual Prototype Model Generation Modeling Time Spent on Functionality IP-reg.h C-API for firmware register access IP-XACT or RDL TLM Interface Generator IP-test.c Reg.txt Pin change & IP register read/write test software Register and IP function documentation Register Descriptions & Configuration Options IP.CC TLM 2.0 I/O, register definitions, and read/write functions IP.CC Func.CC RDL (manual or from Bitwise) IP-XACT * Register read/write functions { Functionality ( ); } * Pin change functions * Reset functions Generated TLM 2.0 software OR *.o Source functionality Binary models 19

20 Generated Model is Easily Customized 3 Primary Ways to Extend Output Add I/O Signals such as Interrupt sc_out<signal_t> irq; Implement Virtual Pre- and Post- Read and Write Methods as specified in RDF input Add additional SystemC constructs such as threads and methods 20

21 Agenda Virtual Platforms Xilinx Zynq Why TLM Extensibility Matters Example: Extending a Virtual Platform Example Results & Summary 21

22 DMI Configuration Example Direct Memory Interface (DMI) configuration error Linux boot is fine, but applications crash with strange symptoms Unless user stops in a debugger, DMI activity is invisible Making DMI more Visible 22

23 Virtual Platform Profiling Register Read/Write Profiling SystemC Activity Profiling Measuring time spent in b_transport 23

24 Transaction Level Breakpoints Breakpoint Conditions Examine transaction data 24

25 Summary Extensible Processing Platforms with fixed ARM based sub-system enable new types of applications Up to 5.2M in extensible logic (gate equivalents) RTL development delays start of SW development TLM Extensible Virtual Platform Delivers early SW development target Increases SW debug productivity Becomes frontend to verification and implementation flows 25

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