Applied mechanics and applied technology in fuel injection pump bench. Rotational speed measurement system design based on CPLD

Transcription

1 Advanced Materials Research Online: ISSN: , Vol. 910, pp doi: / Trans Tech Publications, Switzerland Applied mechanics and applied technology in fuel injection pump bench Rotational speed measurement system design based on CPLD JiChang Wang 1,a,HuanHuan Quan 2,b 1,2 Henan Polytechnic Institute, Nanyang ,China a wjc210@163.com, b @qq.com Keywords: VHDL, CPLD, Rotational speed measurement, the fuel injection pump test-bed Abstract. In the article, proposing one kind of design plan about rotational speed measurement system design based CPLD. Various modules design has completed according to EDA tools and VHDL hardware description language. The feasibility of the speed measurement system design was verified based on the experiment. At present, the system has been successfully application in the fuel injection pump test-bed. 0 Introduction The application object of the speed detection system is the fuel injection pump test-bed. The fuel injection pump test-bed is a special fuel injection pump technology maintenance equipment, mainly used for the calibration of motor vehicle fuel injection quantity, which prompts motor vehicle fuel injection system in the best state, with the application of electronic technology in the industry, promoting the development of fuel injection pump test bench industry. Traditional method which can measure the rotational speed of fuel injection pump test bench is based on single chip microcomputer system design, due to the MCU clock frequency and the limitation of some instruction operation, measurement speed is slow; the working frequency of universal counter can not be too high; PCB integration is not high, leading to large PCB area and signal line length, which are susceptible to external interference [1].In addition to signal acquisition, display and JTAG interface speed, all the rest of speed measuring system designed in this paper is in the CPLD chip, which has the advantages of high speed, high integration, high reliability. 1 Measurement principle Speed measuring principle are realized through the pulse count. As shown in figure 1: Needing to complete each module design in CPLD chip, the generation of control signals are realized through the clock divider design, the working process of the counter module is: when the rising edge effectively, counting module starts to measured signal. When a low level for electricity at ordinary times, the module output current count value, at the same time, the counter reset, waiting for the start of the count. Figure1.Count principle diagram All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications, (ID: , Pennsylvania State University, University Park, USA-09/05/16,17:19:41)

2 Advanced Materials Research Vol Hardware circuit design 2.1 CPLD main control chip This article adopts the EPM7128S series CPLD of Altera Corporation as the target of CPLD. The CPLD EPM7128 series of Altera Company is based on the structural system of the second generation of MAX block high-performance EEPROM structure of CPLD. It fully comply with the IEEE standard JTAG boundary scan, with 5 v ISP function; Pin with least 5 ns logic delay, counting the highest frequency is MHz; Pin can be configured to open drain output. EPM7128S inside have 128 macro cell, 8 logic array block and 2500 logic gate [2]. 2.2 Signal acquisition The use of photoelectric encoder the acquisition speed of EPC-755A signal, EPC-755A is a miniature photoelectric encoder produced by ENCODER PRODUCTS company, which has the advantages of light weight, small volume, collision resistance, easy installation, using metal structure to ensure reliable work for many years, with flexible mounting options. 2.3 Peripheral circuit design Peripheral circuit design as shown in figure 2: Figure 2.CPLD peripheral circuit diagram According to the national standard, the pump test-bed of maximum speed of 3500 r/min, display speed value need four eight digital tube. Choosing NPN output mode with a pull-up resistor as the EPC 755A photoelectric sensor output, the output signal and the CPLD chip is connected. 3 The software design and simulation Design for software, using a top-down modular design thought, which is beneficial to complete the design of each module in the CPLD chip. CPLD internal block diagram as shown in figure 3: Figure 3 CPLD internal block diagram Using VHDL language to describe speed measurement is the main task of the software design of hardware circuit, using EDA tool Quartus II for the design of VHDL to compile, adaptation, optimization, logic synthesis, automatically transform VHDL description into gate level circuit, and then complete the circuit analysis, error correction and verification, automatic layout, simulation, etc [3-4]. 3.1 Phase demodulation module Phase demodulation module is used to judge the spindle steering, and the simulation results are shown in figure 4:

3 318 Materials, Manufacturing Engineering and Information Technology Figure 4.The output signal timing diagram of the spindle rotates in the positive direction According to the simulation results,sig_a, sig_b two signals is used to determine the spindle, reverse. If the rising edge of the signal path ahead sig_b sig_a rising edge of the signal by 90 degrees, which means that the spindle clockwise. Using VHDL language, producing D flip-flop to achieve phase function inside the CPLD. 3.2 Counting Module Control signal is used to achieve the detection speed in Figure 5. signal, the simulation results are shown Figure 5.Speed measurement timing diagram The design of a 16 bit counter within the CPLD, when the control signal con_counter is high, the counter starts to count.when the control signal drops along comes, the test results will be stored in the corresponding register. 3.3 the overall functional simulation The modules are converted into component labeling, connecting each module through the signal line. Principle diagram as shown in figure 6: Figure 6.The overall functional simulation Designing wave file after compiling schematics, adaptation, optimization, logic synthesis. The input clock (in_clk) cycle is 10ns, periodic test signal (test_signal) is 5ns, and the count clock (counter_clk) is 16 x the input clock, counting time of 80ns, functional simulation waveforms shown in figure 7. Figure 7.Speed measurement and display timing simulation

4 Advanced Materials Research Vol According to the simulation charts, when the output is 16, the numbers 1 and 6 are in the digital tube display corresponding. Conversion of all numbers to eight bit binary numbers by decoding, and then, sending the binary number to out_duan signal, at the same time, the corresponding bit selection (out_wei) signal is effective. According to the simulation results, the theoretical analysis and simulation results are identical. 4 Conclusion This paper introduces the hardware and software of the speed measurement system based on CPLD, the design verified by simulation and field test is correct and feasible. The successful application of CPLD chip improve the system stability and anti-interference ability,and make up for the deficiency of the single chip microcomputer measuring system.at present, the speed detection system has been successful application on the fuel injection pump test bench. Reference [1] Shi Po,Lian Deyu. A precise frequency measurement instrument design[j].chinese Journal of Scientific Instrument,2006,27(6): [2] Zhou Ligong,Xia Yuwen.Integrated application technology of MCU and CPLD [M]. First edition.beijing: Beihang University press, [3] (Brazil) Pedroni, says v.a; Qiao Lu peak et al. VHDL digital circuit design tutorial [M]. Beijing:Publishing house of electronic industry, [4] JiFan Wang Xiaotao.VHDL application in the system design [J].Instruments technique and sensor,2003,(05):23-24.

5 Materials, Manufacturing Engineering and Information Technology / Applied Mechanics and Applied Technology in Fuel Injection Pump Bench Rotational Speed Measurement System Design Based on CPLD /