ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL. Fall 2017 Final Exam (6.00 to 8.30pm) Verilog SOLUTIONS

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1 ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL Fall 2017 Final Exam (6.00 to 8.30pm) Verilog SOLUTIONS Note: Closed book no notes or other material allowed apart from the one page of Verilog examples provided. No calculators or other electronic devices. No cell phones, calculators, or other electronic devices allowed Note: Unless otherwise stated all Verilog descriptions must be synthesizable. Note: Do not use the wildcard character (*) Note: No comments are required NAME: ECE574: Final Exam 1

Question 1 [15 marks]: The following assign statement describes combinational logic that takes in a set of five 8-bit inputs (a, b, c, d, and e) and carries out the operations to produce a 16-bit

2 Question 1 [15 marks]: The following assign statement describes combinational logic that takes in a set of five 8-bit inputs (a, b, c, d, and e) and carries out the operations to produce a 16-bit output (f). assign f = ((a b) + c) * (d & e); Assume that the four operations take the same amount of time to execute (and they can execute in one clock cycle). Write a synthesizable module description of a pipe-lined version to carry out the same operations so that new output (f) values can be generated for each new set of input values (a, b, c, d and e). How many flip-flops will be required to implement this pipe-lined version? 56 How many clock cycles will it take to produce a new output from a new set of inputs? 3 ECE574: Final Exam 2

3 Question 2 [5 marks]: Write a Verilog description of a 2-line to 4-line decoder with an enable input. The function table is: Inputs Outputs Enable Select G B A Y3 Y2 Y1 Y0 0 don t care don t care Write the Verilog module description of the decoder using a case statement The start of the module description is provided (modify as necessary): Example solution: module decoder( input g, input a, input b, output reg [3:0] y ); // need reg for y with always statement wire [1:0] sel; assign sel = {b,a}; // always with case example (g, sel) // need reg for y case ({g, sel}) 4: y = 4'b0001; // or 3 b100 5: y = 4'b0010; 6: y = 4'b0100; 7: y = 4'b1000; default: y = 4'b0000; endcase endmodule ECE574: Final Exam 3

4 Question 3 [20 marks]: An FPGA running off its own local 100MHz oscillator is connected to a device in another system with its own clock running asynchronously to the FPGA clock. The device generates a pulse ( pulse_long ) that it sends to the FPGA every 100Hz. The pulse is high for approximately 5us duration. a) Assume that part of the FPGA has a simple state machine that uses the pps_long signal to determine if it should go into one state or another. If the pps_long signal is not synchronized to the FPGA clock domain it is possible that the state machine could go into an incorrect state. Describe carefully how this is possible include a simple schematic of the state machine logic and a timing diagram as part of your description. b) Design a synthesizable module description of a synchronizer circuit in Verilog for the FPGA to generate a single 10ns pulse each time it detects the 100Hz pulse remember to take into account the possibility of metastability. Design the synchronizer so a flip-flop is produced for the 10ns pulse. The start of the module description is provided (modify as required): module top_level( input clk_fpga, // 100 MHz clock input pulse_long, // 5us long signal from device output pulse_short, // synchronized 10ns version of signal ); a) Schematic and timing is same as shown in class ECE574: Final Exam 4

5 ECE574: Final Exam 5

6 Question 4 [25 marks]: In Verilog, design a system that consists of: A four state state-machine controlling the loading and right shift of a 10-bit shift-register. The state machine waits in S0 until it receives an active high input start signal; It then goes from S0 to S1; In S1 it loads the 10-bit shift register with the value on a 10-bit data input; In S2 it sends a signal to start the shift register; It then waits in S3 until the shift register has completed shifting out the 10 bits. The state machine then returns to state S0 and waits for the cycle to repeat again. Notes: For the state machine design use a standard design approach with two always statements (one for the state memory and one for the next_state logic). Use concurrent assignment statements for outputs from the state machine. Assume an active high asynchronous reset and a positive edge triggered clk. Assume the start signal is high for no more than two clock cycles. Assume the shift register shifts right, and the shift output is connected to the least significant bit. Design the shift register as a separate module and then instantiate it at the top level. A simplified block diagram of the system is shown below. CLK RESET START DATA Shift_Register Module SHIFT State Machine How many flip-flops will be required to implement this system (briefly explain why)? 2 or 4 for state machine + 10 for shift register + 4 for counter = 16 or 18 The start of the top-level module description is provided: module sm_shift( input reset, input clk, input start, // start the operation input [9:0] data, // data to load into shift register output shift // output of shift register ) ECE574: Final Exam 6

7 Shift register code (could also write as two separate always statements) ECE574: Final Exam 7

8 ECE574: Final Exam 8

Question 5 [10 marks]: Write a Verilog synthesizable description of a circuit with the inputs and outputs as shown in the block diagram below (the bus ports are all 16-bits in size): OE A_BUS B_BUS

9 Question 5 [10 marks]: Write a Verilog synthesizable description of a circuit with the inputs and outputs as shown in the block diagram below (the bus ports are all 16-bits in size): OE A_BUS B_BUS LOAD C_BUS When the output enable OE signal is high then the B_BUS bidirectional port should have the value of the A_BUS input port. When the OE signal is low then the B_BUS port should go to tri-state. On a rising edge of the load signal the value on the B_BUS should be loaded into 16 flip-flops. The output of the flip-flops should be connected to the output port C_BUS. ECE574: Final Exam 9

10 Question 6 [15 marks]: Write a complete Verilog description of a test bench to verify that a combinational circuit works correctly. The combinational circuit has a three-bit input called sel and a two-bit output called y. You need to test for each possible input/output combination. A test vector file (called output_vec.txt ) is used to store just the expected two-bit y output values (shown as Y output in the table below) for each of the eight-possible input combinations (from 000, 001, to 111 ): Sel input Y output [2:0] [1:0] IMPORTANT: a) Place the expected Y outputs in an array by loading the array from the output_vec.txt file. b) Use a FOR.. loop to cycle though all of the possible input combinations and check the corresponding output. c) Use a clock signal to help synchronize the testing. d) The test bench should output an error message if any errors are found, with information on simulation time, and the actual versus expected value of y. Partial description of synthesizable combinational circuit module (you do NOT need to write the synthesis description of the combinational circuit): module comb ( input [2:0] sel, output [1:0] y ); ECE574: Final Exam 10

11 Example solution: ECE574: Final Exam 11

Question 7 [10 marks]: Add additional Verilog statements to the shift register module model description below so it has timing checks and delays.

12 Question 7 [10 marks]: Add additional Verilog statements to the shift register module model description below so it has timing checks and delays. Use the following timing values: (50ns) minimum period for signal clk (10ns) minimum time abcd must be valid before positive edge of clk (2ns) minimum time abcd must be valid after positive edge of clk (30ns) minimum time reset signal must be high If any of these timing requirements are violated issue an appropriate warning message. IMPORTANT: use timing check tasks for the period, setup and hold times but do NOT use a timing check task to verify the minimum reset pulse width instead write your own Verilog code to check this timing value. Also, add to the model the following delay: The q output changes 15ns after reset is active. Note: You do not need to write out the module description again, instead carefully show where the additional statements or changes need to go. ECE574: Final Exam 12

13 Example solution: ECE574: Final Exam 13

14 ECE574: Final Exam 14

Note: Closed book no notes or other material allowed, no calculators or other electronic devices.

ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL Fall 2017 Exam Review Note: Closed book no notes or other material allowed, no calculators or other electronic devices. One page