USE isplsi 2032E FOR NEW DESIGNS

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1 isplsi 202/A In-System Programmable High Density PLD Features ENHANCEMENTS isplsi 202A is Fully Form and Function Compatible to the isplsi 202, with Identical Timing Specifcations and Packaging isplsi 202A is Built on an Advanced 0. Micron E 2 CMOS Technology HIGH DENSITY PROGRAMMABLE LOGIC 00 PLD Gates 2 I/O Pins, Two Dedicated Inputs 2 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic HIGH PERFORMANCE E 2 CMOS TECHNOLOGY fmax 80 MHz Maximum Operating Frequency tpd.0 ns Propagation Delay TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable Non-Volatile 0% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power IN-SYSTEM PROGRAMMABLE In-System Programmable (ISP ) V Only Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality Reprogram Soldered Devices for Faster Prototyping OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS Complete Programmable Device Can Combine Glue Logic and Structured Designs Enhanced Pin Locking Capability Three Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Programmable Output Slew Rate Control to Minimize Switching Noise Flexible Pin Placement Optimized Global Routing Pool Provides Global Interconnectivity Functional Block Diagram Description Global Routing Pool (GRP) The isplsi 202 and 202A are High Density Programmable Logic Devices. The devices contain 2 Registers, 2 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The isplsi 202 and 202A feature V insystem programmability and in-system diagnostic capabilities. The isplsi 202 and 202A offer nonvolatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on these devices is the Generic Logic Block (GLB). The GLBs are labeled A0, A.. A7 (Figure ). There are a total of eight GLBs in the isplsi 202 and 202A devices. Each GLB is made up of four macrocells. Each GLB has 8 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Input Bus Output Routing Pool (ORP) A0 A A2 A GLB Logic Array D Q D Q D Q D Q A7 A6 A A4 Output Routing Pool (ORP) Input Bus 09Bisp/2000 Copyright 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., Northeast Moore Ct., Hillsboro, Oregon 9724, U.S.A. January 2002 Tel. (0) ; -800-LATTICE; FAX (0) ; 202_

2 Functional Block Diagram Figure. isplsi 202/A Functional Block Diagram GOE 0 I/O 0 I/O I/O 2 I/O I/O 4 I/O I/O 6 I/O 7 I/O 8 I/O 9 I/O I/O I/O 2 I/O I/O 4 I/O SDI/IN 0 SDO/IN MODE ispen Input Bus Output Routing Pool (ORP) A0 A A2 A Notes: *Y and RESET are multiplexed on the same pin Global Routing Pool (GRP) The devices also have 2 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, output or bi-directional I/O pin with -state control. The signal levels are TTL compatible voltages and the output drivers can source 4 ma or sink 8 ma. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Eight GLBs, 2 I/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (Figure ). The outputs of the eight GLBs are connected to a set of 2 universal I/O cells by the ORP. Each isplsi 202 and 202A device contains one Megablock. Y0 Y*/RESET SCLK/Y2 A7 A6 A A4 CLK 0 CLK CLK 2 Output Routing Pool (ORP) Input Bus I/O I/O 0 I/O 29 I/O 28 I/O 27 I/O 26 I/O 2 I/O 24 I/O 2 I/O 22 I/O 2 I/O 20 I/O 9 I/O 8 I/O 7 I/O 6 09B()isp/2000 GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the isplsi 202 and 202A devices are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the 2

3 Absolute Maximum Ratings Supply Voltage V cc to +7.0V Input Voltage Applied to V CC +.0V Off-State Output Voltage Applied to V CC +.0V Storage Temperature to 0 C Case Temp. with Power Applied... - to 2 C Max. Junction Temp. (T J ) with Power Applied... 0 C. Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Condition VCC VIL VIH SYMBOL Supply Voltage Input Low Voltage Input High Voltage Capacitance (T A 2 C, f.0 MHz) C C SYMBOL PARAMETER Dedicated Input Capacitance PARAMETER Commercial Industrial T A 0 C to + 70 C T A -40 C to + 8 C TYPICAL 6 UNITS MIN. MAX. UNITS V 4.. V Table 2-000/ V cc + I/O Capacitance 7 pf V.0V, V 2.0V 2 CC I/O C Clock Capacitance pf V.0V, V 2.0V CC Y Data Retention Specifications Data Retention Erase/Reprogram Cycles PARAMETER pf V V TEST CONDITIONS V.0V, V 2.0V MINIMUM MAXIMUM UNITS CC IN Table /202 Years Cycles Table A-isp

4 Switching Test Conditions Input Pulse Levels GND to.0v Input Rise and Fall Time -, -0, -80. ns % to 90% -80, - ns Input Timing Reference Levels.V Output Timing Reference Levels.V Output Load See Figure 2 -state levels are measured 0.V from steady-state active level. Output Load Conditions (see Figure 2) DC Electrical Characteristics Table 2-000/202 TEST CONDITION R R2 CL A 470Ω 90Ω pf B Active High 90Ω pf Active Low 470Ω 90Ω pf C Active High to Z at V OH-0.V 90Ω pf Active Low to Z at V +0.V 470Ω 90Ω pf SYMBOL VOL VOH IIL IIH IIL-isp IIL-PU IOS 2, 4 ICC OL PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current ispen Input Low Leakage Current I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current Table A Figure 2. Test Load Device Output Over Recommended Operating Conditions I OL 8 ma I -4 ma OH 0V V V (Max.) IN IL.V V V IN 0V V IN VIL 0V V IN VIL V V, V 0.V CC OUT V IL 0.0V, V IH.0V f MHz TOGGLE + V R R2 CL* *CL includes Test Fixture and Probe Capacitance.. One output at a time for a maximum duration of one second. V OUT 0.V was selected to avoid test problems by tester ground degradation. Characterized but not 0% tested. 2. Measured using two 6-bit counters.. Typical values are at V CC V and T A 2 C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I. CC CC Test Point 02A CONDITION MIN. TYP. MAX. UNITS Comm. Industrial -80, -0 Others V V µa µa µa µa ma 60 ma ma ma Table /202 4

5 External Timing Parameters Over Recommended Operating Conditions PARAMETER 4 TEST COND. # 2 DESCRIPTION -80 MIN. MAX. -0 MIN. MAX. - MIN. MAX. UNITS tpd A Data Prop. Delay, 4PT Bypass, ORP Bypass ns tpd2 A 2 Data Prop. Delay ns fmax A Clk Frequency with Internal Feedback MHz fmax (Ext.) 4 Clk Frequency with Ext. Feedback ( tsu2 + tco) 2 0 MHz fmax (Tog.) Clk Frequency, Max. Toggle MHz tsu 6 GLB Reg Setup Time before Clk, 4 PT Bypass ns tco A 7 GLB Reg. Clk to Output Delay, ORP Bypass ns th 8 GLB Reg. Hold Time after Clk, 4 PT Bypass ns tsu2 9 GLB Reg. Setup Time before Clk ns tco2 GLB Reg. Clk to Output Delay ns th2 GLB Reg. Hold Time after Clk ns tr A 2 Ext. Reset Pin to Output Delay ns trw Ext. Reset Pulse Duration ns tptoeen B 4 Input to Output Enable ns tptoedis C Input to Output Disable ns tgoeen B 6 Global OE Output Enable ns tgoedis C 7 Global OE Output Disable ns twh 8 Ext. Synchronous Clk Pulse Duration, High ns twl 9 Ext. Synchronous Clk Pulse Duration, Low ns. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details.. Standard 6-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. Table 2-000B-80/202

6 External Timing Parameters PARAMETER 4 TEST COND. # 2 Over Recommended Operating Conditions DESCRIPTION - MIN. MAX. UNITS tpd A Data Propagation Delay, 4PT Bypass, ORP Bypass.0.0 ns tpd2 A 2 Data Propagation Delay.0 8. ns fmax A Clock Frequency with Internal Feedback.0 MHz fmax (Ext.) 4 Clock Frequency with External Feedback ( tsu2 + tco) MHz fmax (Tog.) Clock Frequency, Max. Toggle MHz tsu 6 GLB Reg. Setup Time before Clock, 4 PT Bypass. 7. ns tco A 7 GLB Reg. Clock to Output Delay, ORP Bypass. 8.0 ns th 8 GLB Reg. Hold Time after Clock, 4 PT Bypass ns tsu2 9 GLB Reg. Setup Time before Clock ns tco2 GLB Reg. Clock to Output Delay ns th2 GLB Reg. Hold Time after Clock ns tr A 2 Ext. Reset Pin to Output Delay. 9. ns trw Ext. Reset Pulse Duration 6..0 ns tptoeen B 4 Input to Output Enable ns tptoedis C Input to Output Disable ns tgoeen B 6 Global OE Output Enable ns tgoedis C 7 Global OE Output Disable ns twh 8 External Synchronous Clock Pulse Duration, High ns twl 9 External Synchronous Clock Pulse Duration, Low ns. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details.. Standard 6-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. Table 2-000B-/ MIN. MAX. 6

7 Internal Timing Parameters Over Recommended Operating Conditions PARAMETER # 2 DESCRIPTION MIN. MAX. MIN. MAX. MIN. MAX. UNITS Inputs tio 20 Input Buffer Delay ns tdin 2 Dedicated Input Delay ns GRP tgrp 22 GRP Delay ns GLB t4ptbpc 2 4 Product Term Bypass Path Delay (Combinatorial) ns t4ptbpr 24 4 Product Term Bypass Path Delay (Registered)...6 ns tptxor 2 Product Term/XOR Path Delay ns t20ptxor Product Term/XOR Path Delay ns txoradj 27 XOR Adjacent Path Delay ns tgbp 28 GLB Register Bypass Delay ns tgsu 29 GLB Register Setup Time before Clock ns tgh 0 GLB Register Hold Time after Clock ns tgco GLB Register Clock to Output Delay ns tgro 2 GLB Register Reset to Output Delay.0.2. ns tptre GLB Product Term Reset to Register Delay ns tptoe 4 GLB Product Term Output Enable to I/O Cell Delay ns tptck GLB Product Term Clock Delay ns ORP torp 6 ORP Delay ns torpbp 7 ORP Bypass Delay ns Outputs tob 8 Output Buffer Delay.2..2 ns tsl 9 Output Slew Limited Delay Adder ns toen 40 I/O Cell OE to Output Enabled ns todis 4 I/O Cell OE to Output Disabled ns tgoe 42 Global Output Enable ns Clocks tgy0 4 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns tgy/2 44 Clock Delay, Y or Y2 to Global GLB Clock Line ns Global Reset tgr 4 Global Reset to GLB ns. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.. The XOR adjacent path can only be used by hard macros. Table 2-006C-80/202 7

8 Internal Timing Parameters Over Recommended Operating Conditions PARAMETER # 2 DESCRIPTION MIN. MAX. MIN. MAX. UNITS Inputs tio 20 Input Buffer Delay ns tdin 2 Dedicated Input Delay ns GRP tgrp 22 GRP Delay ns GLB t4ptbpc 2 4 Product Term Bypass Path Delay (Combinatorial) ns t4ptbpr 24 4 Product Term Bypass Path Delay (Registered) ns tptxor 2 Product Term/XOR Path Delay ns t20ptxor Product Term/XOR Path Delay ns txoradj 27 XOR Adjacent Path Delay 7..2 ns tgbp 28 GLB Register Bypass Delay ns tgsu 29 GLB Register Setup Time befor Clock ns tgh 0 GLB Register Hold Time after Clock ns tgco GLB Register Clock to Output Delay ns tgro 2 GLB Register Reset to Output Delay ns tptre GLB Product Term Reset to Register Delay ns tptoe 4 GLB Product Term Output Enable to I/O Cell Delay ns tptck GLB Product Term Clock Delay ns ORP torp 6 ORP Delay. 2. ns torpbp 7 ORP Bypass Delay ns Outputs tob 8 Output Buffer Delay ns tsl 9 Output Slew Limited Delay Adder.0.0 ns toen 40 I/O Cell OE to Output Enabled ns todis 4 I/O Cell OE to Output Disabled ns tgoe 42 Global Output Enable.0.6 ns Clocks tgy0 4 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns tgy/2 44 Clock Delay, Y or Y2 to Global GLB Clock Line ns Global Reset tgr 4 Global Reset to GLB ns. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.. The XOR adjacent path can only be used by hard macros. Table 2-006C-/202 8

9 isplsi 202/A Timing Model I/O Cell GRP GLB ORP I/O Cell Feedback Ded. In #2 Comb 4 PT Bypass #2 I/O Pin (Input) Reset Y0,,2 GOE 0 I/O Delay GRP Reg 4 PT Bypass GLB Reg Bypass ORP Bypass #20 #22 #24 #28 #4 #4, 44 #42 20 PT XOR Delays #2, 26, 27 Control RE PTs OE #, 4, CK Derivations of tsu, th and tco from the Product Term Clock tsu Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20+ #22+ #26) + (#29) - (#20+ #22+ #) 2. ns ( ) + (0.) - ( ) th. ns Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20+ #22+ #) + (#0) - (#20+ #22+ #26) ( ) + (.8) - ( ) GLB Reg Delay D Q RST #29, 0,, 2 tco Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20+ #22+ #) + (#) + (#6 + #8) 7.7 ns ( ) + (0.7) + ( ) Note: Calculations are based upon timing specifications for the isplsi 202/A-80L Table /202 I/O Pin (Output) #7 ORP Delay #6 #8, 9 #40, 4 049/2000 9

10 Power Consumption Power consumption in the isplsi 202 and 202A devices depends on two primary factors: the speed at which the device is operating and the number of Product Terms used. Figure 4 shows the relationship between power and operating speed. Figure 4. Typical Device Power Consumption vs fmax ICC (ma) isplsi 202/A (-0, -80) isplsi 202/A (-80, -, -) fmax (MHz) Notes: Configuration of Two 6-bit Counters Typical Current at V, 2 C ICC can be estimated for the isplsi 202/A using the following equation: For 202/A -0, -80: ICC(mA) 0 + (# of PTs * 0.46) + (# of nets * Max freq * 0.02) For 202/A -, -, -80: ICC(mA) 2 + (# of PTs * 0.0) + (# of nets * Max freq * 0.02) Where: # of PTs Number of Product Terms used in design # of nets Number of Signals used in device Max freq Highest Clock Frequency to the device (in MHz) The ICC estimate is based on typical conditions (VCC.0V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 027A/202A

11 Pin Description NAME I/O 0 - I/O I/O 4 - I/O 7 I/O 8 - I/O I/O 2 - I/O I/O 6 - I/O 9 I/O 20 - I/O 2 I/O 24 - I/O 27 I/O 28 - I/O GOE 0 Y0 RESET/Y ispen SDI/IN 0 2 MODE SDO/IN 2 SCLK/Y2 2 GND VCC NC 44-PIN PLCC PIN NUMBERS, 9, 2, 29, 7, 4,, 7, , 20, 26, 0, 8, 42, 4, 8,, 2 2, 4 7, 2, 27,, 9, 4,, 9, 8, 22, 28, 2, 40, 44, 6, 44-PIN TQFP PIN NUMBERS 9,, 9, 2,, 4,, 7, 9 6, 28 8, 42 6, 0. NC pins are not to be connected to any active signals, VCC or GND. 2. Pins have dual function capability , 4, 20, 24, 2, 6, 42, 2,,, 2, 2,, 7, 4,, 2, 6, 22, 26, 4, 8, 44, 4 48-PIN TQFP PIN NUMBERS 9, 4, 20, 2,, 8, 44,, ,, 2, 26, 4, 9, 4, 2,, 6, 22, 27,, 40, 46,, 2, 24, 6, 48 DESCRIPTION Input/Output Pins These are the general purpose I/O pins used by the logic array. Global Output Enable input pin. Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device. This pin performs two functions: - Dedicated clock input. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. - Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Input Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK controls become active. Input This pin performs two functions. When ispen is logic low, it functions as an input pin to load programming data into the device. SDI/IN0 also is used as one of the two control pins for the isp state machine. When ispen is high, it functions as a dedicated input pin. Input When in ISP Mode, controls operation of ISP state machine. Output/Input This pin performs two functions. When ispen is logic low, it functions as an output pin to read serial shift register data. When ispen is high, it functions as a dedicated input pin. Input This pin performs two functions. When ispen is logic low, it functions as a clock pin for the Serial Shift Register. When ispen is high, it functions as a dedicated clock input. This clock input is brought into the Clock Distribution Network and can be routed to any GLB and/or I/O cell on the device. Ground (GND) V CC No Connect. Table A-08isp/202, 7, 2, 28, 7, 4, 47, 4

12 Pin Configuration isplsi 202/A Pinout Diagram I/O 28 I/O 29 I/O 0 I/O Y0 VCC ispen SDI/IN 0 I/O 0 I/O I/O I/O 27 isplsi 202/A Pinout Diagram 6 I/O 26 I/O 2 4 I/O 24 GOE 0 GND I/O 2 I/O 22 I/O 2 I/O 20 I/O isplsi 202/A Top View I/O I/O 4 I/O I/O 6 I/O 7 GND SDO/IN I/O 8 I/O 9 I/O I/O. Pins have dual function capability. I/O 28 I/O 29 I/O 0 I/O Y0 VCC ispen SDI/IN 0 I/O 0 I/O I/O I/O 27 I/O 26 I/O 2 I/O 24 GOE 0 GND I/O 2 I/O 22 I/O 2 I/O 20 I/O isplsi 202/A Top View I/O 8 I/O 7 I/O 6 MODE RESET/Y VCC SCLK/Y2 I/O I/O 4 I/O I/O B/202/A I/O 8 I/O 7 I/O 6 MODE RESET/Y VCC SCLK/Y2 I/O I/O 4 I/O I/O 2 I/O I/O 4 I/O I/O 6 I/O 7 GND SDO/IN I/O 8 I/O 9 I/O I/O 08/202/A. Pins have dual function capability. 2

13 Pin Configuration isplsi 202/A Pinout Diagram I/O 28 I/O 29 2 I/O 0 I/O 4 Y0 VCC 6 ispen 7 2SDI/IN 0 8 I/O 0 9 I/O I/O 2 NC 2 NC I/O 27 I/O 26 I/O 2 I/O 24 GOE 0 GND I/O 2 I/O 22 I/O 2 I/O 20 I/O isplsi 202/A Top View I/O I/O 4 I/O I/O 6 I/O 7 GND 2SDO/IN I/O 8 I/O 9 I/O I/O NC I/O 8 I/O 7 I/O 6 MODE RESET/Y 2 VCC SCLK/Y2 2 I/O I/O 4 I/O I/O NC. NC pins are not to be connected to any active signal, Vcc or GND. 2. Pins have dual function capability. -202/A

14 Part Number Description isplsi XXXX XXX X XXX X Device Family Device Number A Speed MHz fmax 0 4 MHz fmax 7 MHz fmax MHz fmax 80 MHz fmax isplsi 202/A Ordering Information FAMILY f max (MHz) t pd (ns) isplsi FAMILY f max (MHz) t pd (ns) isplsi COMMERCIAL INDUSTRIAL ORDERING NUMBER ORDERING NUMBER Grade Blank Commercial I Industrial Package J PLCC T44 TQFP T48 TQFP Power L Low 022A/202 PACKAGE isplsi 202A-80LJ isplsi 202A-80LT isplsi 202A-80LT48 4. isplsi 202A-0LJ44 4. isplsi 202A-0LT44 4. isplsi 202A-0LT isplsi 202A-LJ isplsi 202A-LT isplsi 202A-LT48 isplsi 202A-LJ44 isplsi 202A-LT44 isplsi 202A-LT48 isplsi 202A-80LJ44 isplsi 202A-80LT44 isplsi 202A-80LT48 Table 2-004A/202A PACKAGE isplsi 202A-80LJ44I isplsi 202A-80LT44I isplsi 202A-80LT48I Table 2-004B/202A 4

15 FAMILY isplsi f max (MHz) t pd (ns) FAMILY f max (MHz) t pd (ns) isplsi COMMERCIAL INDUSTRIAL ORDERING NUMBER isplsi LJ isplsi LT44 isplsi LT48 isplsi 202-0LJ isplsi 202-0LT44 isplsi 202-0LT48 isplsi 202-LJ isplsi 202-LT44 isplsi 202-LT48 isplsi 202-LJ isplsi 202-LT44 isplsi 202-LT48 isplsi LJ isplsi LT44 isplsi LT48 ORDERING NUMBER PACKAGE Table 2-004A/202 PACKAGE isplsi LJI isplsi LT44I isplsi LT48I Table 2-004C/202

USE isplsi 2032E FOR NEW DESIGNS

USE isplsi 2032E FOR NEW DESIGNS Lead- Free Package Options Available! isplsi 2032/A In-System Programmable High Density PLD Features ENHANCEMENTS isplsi 2032A is Fully Form and Function Compatible to the isplsi 2032, with Identical Timing