All Devices Discontinued!

Transcription

1 GAL 6LVC/D Device Datasheet June All Devices Discontinued! Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number Product Status Reference PCN GAL6LVC-7LJ GAL6LVC-7LJN PCN#6-7 GAL6LVC GAL6LVC-LJ GAL6LVC-LJN GAL6LVC-5LJ Discontinued GAL6LVC-5LJN PCN#9- GAL6LVD-3LJ GAL6LVD GAL6LVD-3LJN GAL6LVD-5LJ GAL6LVD-5LJN 5555 N.E. Moore Ct. Hillsboro, Oregon Phone (53) 6- FAX (53) nternet:

2 Lead-Free Package Options Available! GAL6LV Low Voltage E CMOS PLD Generic Array Logic Features Functional Block Diagram HGH PERFORMANCE E CMOS TECHNOLOGY 3.5 ns Maximum Propagation Delay Fmax = 5 MHz.5 ns Maximum from Clock nput to Data Output UltraMOS Advanced CMOS Technology 3.3V LOW VOLTAGE 6V ARCHTECTURE JEDEC-Compatible 3.3V nterface Standard 5V Compatible nputs /O nterfaces with Standard 5V TTL Devices (GAL6LVC) ACTVE PULL-UPS ON ALL PNS (GAL6LVD Only) E CELL TECHNOLOGY Reconfigurable Logic Reprogrammable Cells % Tested/% Yields High Speed Electrical Erasure (<ms) Year Data Retention EGHT OUTPUT LOGC MACROCELLS Maximum Flexibility for Complex Logic Designs Programmable Output Polarity PRELOAD AND POWER-ON RESET OF ALL REGSTERS % Functional Testability APPLCATONS NCLUDE: Glue Logic for 3.3V Systems DMA Control State Machine Control High Speed Graphics Processing Standard Logic Speed Upgrade ELECTRONC SGNATURE FOR DENTFCATON LEAD-FREE PACKAGE OPTONS Description The GAL6LVD, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL6LVC can interface with both 3.3V and 5V signal levels. The GAL6LV is manufactured using Lattice Semiconductor's advanced 3.3V E CMOS process, which combines CMOS with Electrically Erasable (E ) floating gate technology. High speed erase times (<ms) allow the devices to be reprogrammed quickly and efficiently. The 3.3V GAL6LV uses the same industry standard 6V architecture as its 5V counterpart and supports all architectural features such as combinatorial or registered macrocell operations. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers % field programmability and functionality of all GAL products. n addition, erase/write cycles and data retention in excess of years are specified. /CLK PROGRAMMABLE AND-ARRAY (64 X 3) Pin Configuration 4 6 PLCC /CLK Vcc GAL6LV Top View GND /OE CLK OE /OE Copyright 4 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTCE SEMCONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 974, U.S.A. August 4 Tel. (53) 6-; --LATTCE; FAX (53) 6-556; 6lv_5

3 Specifications GAL6LV GAL6LV Ordering nformation Conventional Packaging Commercial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # Lead-Free Packaging Commercial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # Part Number Description GAL6LVD GAL6LVC L = Low Power Device Name Speed (ns) Power _ XXXXXXXX XX X XX X Package GAL6LVD-3LJ -Lead PLCC GAL6LVD-5LJ -Lead PLCC GAL6LVC-7LJ -Lead PLCC GAL6LVC-LJ -Lead PLCC 5 65 GAL6LVC-5LJ -Lead PLCC Package GAL6LVD-3LJN Lead-Free -Lead PLCC GAL6LVD-5LJN Lead-Free -Lead PLCC GAL6LVC-7LJN Lead-Free -Lead PLCC GAL6LVC-LJN Lead-Free -Lead PLCC 5 65 GAL6LVC-5LJN Lead-Free -Lead PLCC. Discontinued per PCN #6-7. Contact Rochester Electronics for available inventory. Grade Package Blank = Commercial J = PLCC JN = Lead-free PLCC

4 Specifications GAL6LV Output Logic Macrocell () The following discussion pertains to configuring the output logic macrocell. t should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user. There are three global configuration modes possible: simple, complex, and registered. Details of each of these modes are illustrated in the following pages. Two global bits, SYN and AC, control the mode configuration for all macrocells. The XOR bit of each macrocell controls the polarity of the output in any of the three modes, while the AC bit of each of the macrocells controls the input/output configuration. These two global and 6 individual architecture bits define all possible configurations in a GAL6LV. The information given on these architecture bits is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits. The following is a list of the PAL architectures that the GAL6LV can emulate. t also shows the mode under which the GAL6LV emulates the PAL architecture. Compiler Support for Software compilers support the three different global modes as different device types. These device types are listed in the table below. Most compilers have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. The different device types listed in the table can be used to override the automatic device selection by the software. For further details, refer to the compiler software manuals. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. n registered mode pin and pin are permanently configured PAL Architectures Emulated by GAL6LV 6R 6R6 6R4 6RP 6RP6 6RP4 6L 6H 6P L L6 4L4 6L H H6 4H4 6H P P6 4P4 6P GAL6LV Global Mode Registered Registered Registered Registered Registered Registered Complex Complex Complex as clock and output enable, respectively. These pins cannot be configured as dedicated inputs in the registered mode. n complex mode pin and pin become dedicated inputs and use the feedback paths of pin 9 and pin respectively. Because of this feedback path usage, pin 9 and pin do not have the feedback option in this mode. n simple mode all feedback paths of the output pins are routed via the adjacent pins. n doing so, the two inner most pins ( pins 5 and 6) will not have the feedback option as these pins are always configured as dedicated combinatorial output. Registered Complex Auto Mode Select ABEL P6VR P6VC P6VAS P6V CUPL G6VMS G6VMA G6VAS G6V LOG/iC GAL6V_R GAL6V_C7 GAL6V_C GAL6V OrCAD-PLD "Registered" "Complex" "" GAL6VA PLDesigner P6VR P6VC P6VC P6VA TANGO-PLD G6VR G6VC G6VAS 3 G6V ) Used with Configuration keyword. ) Prior to Version. support. 3) Supported on Version. or later. 3

5 Specifications GAL6LV Registered Mode n the Registered mode, macrocells are configured as dedicated registered outputs or as /O functions. Dedicated input or output functions can be implemented as subsets of the /O function. Architecture configurations available in this mode are similar to the common 6R and 6RP4 devices with various permutations of polarity, /O and register placement. All registered macrocells share common clock and output enable control pins. Any macrocell can be configured as registered or / O. Up to eight registers or up to eight /Os are possible in this mode. OE CLK XOR D Q Q Registered outputs have eight product terms per output. /Os have seven product terms per output. The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are shown on the logic diagram on the following page. Registered Configuration for Registered Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this output configuration. - Pin controls common CLK for the registered outputs. - Pin controls common OE for the registered outputs. - Pin & Pin are permanently configured as CLK & OE for registered output configuration. Combinatorial Configuration for Registered Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this output configuration. - Pin & Pin are permanently configured as CLK & OE for registered output configuration. XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 4

6 Specifications GAL6LV Registered Mode Logic Diagram PLCC Package Pinout PTD 9 XOR-4 AC- XOR-49 AC- XOR-5 AC- XOR-5 AC-3 XOR-5 AC-4 XOR-53 AC-5 XOR-54 AC-6 XOR-55 AC-7 OE SYN-9 AC-93 5

7 Specifications GAL6LV Complex Mode n the Complex mode, macrocells are configured as output only or /O functions. Up to six /Os are possible in this mode. Dedicated inputs or outputs can be implemented as subsets of the /O function. The two outer most macrocells (pins & 9) do not have input capability. Designs requiring eight /Os can be implemented in the Registered mode. Architecture configurations available in this mode are similar to the common 6L and 6P devices with programmable polarity in each macrocell. XOR All macrocells have seven product terms per output. One product term is used for programmable output enable control. Pins and are always available as data inputs into the AND array. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page. Combinatorial /O Configuration for Complex Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC=. - Pin 3 through Pin are configured to this function. Combinatorial Output Configuration for Complex Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC=. - Pin and Pin 9 are configured to this function. XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. 6

8 Specifications GAL6LV 7 PLCC Package Pinout PTD SYN-9 AC-93 XOR-55 AC-7 XOR-54 AC-6 XOR-53 AC-5 XOR-5 AC-4 XOR-5 AC-3 XOR-5 AC- XOR-49 AC- XOR-4 AC Complex Mode Logic Diagram

9 Specifications GAL6LV Mode n the mode, macrocells are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. Architecture configurations available in this mode are similar to the common L and P6 devices with many permutations of generic output polarity or input choices. All outputs in the simple mode have a maximum of eight product terms that can control the logic. n addition, each output has programmable polarity. XOR XOR Vcc Vcc Pins and are always available as data inputs into the AND array. The center two macrocells (pins 5 & 6) cannot be used as input or /O pins, and are only available as dedicated outputs. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram. Combinatorial Output with Feedback Configuration for Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this configuration. - All except pins 5 & 6 can be configured to this function. Combinatorial Output Configuration for Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this configuration. - Pins 5 & 6 are permanently configured to this function. Dedicated nput Configuration for Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this configuration. - All except pins 5 & 6 can be configured to this function. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

10 Specifications GAL6LV 9 PLCC Package Pinout PTD 9 XOR-4 AC- XOR-49 AC- XOR-5 AC- XOR-5 AC-3 XOR-5 AC-4 XOR-53 AC-5 XOR-54 AC-6 XOR-55 AC-7 SYN-9 AC Mode Logic Diagram

11 Specifications GAL6LVD Absolute Maximum Ratings () Recommended Operating Conditions Supply voltage V CC....5 to +4.6V nput voltage applied....5 to +5.6V /O voltage applied....5 to +4.6V Off-state output voltage applied....5 to +4.6V Storage Temperature to 5 C Ambient Temperature with Power Applied to 5 C.Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Electrical Characteristics Commercial Devices: Ambient Temperature (T A )... to 75 C Supply voltage (V CC ) with Respect to Ground to +3.6V SYMBOL PARAMETER CONDTON MN. TYP. 3 MAX. UNTS VL nput Low Voltage Vss.3. V VH nput High Voltage. 5.5 V /O High Voltage. Vcc+.5 V L nput or /O Low Leakage Current V VN VL (MAX.) μa H nput or /O High Leakage Current (Vcc-.)V VN VCC μa nput High Leakage Current Vcc VN 5.5V μa /O High Leakage Current Vcc VN 4.6V ma VOL Output Low Voltage OL = MAX. Vin = VL or VH.4 V OL = 5μA Vin = VL or VH. V VOH Output High Voltage OH = MAX. Vin = VL or VH.4 V OH = -μa Vin = VL or VH Vcc-.V V OL Low Level Output Current ma OH High Level Output Current ma OS Output Short Circuit Current VCC = 3.3V VOUT =.5V T A = 5 C 5 ma COMMERCAL CC Operating Power VL = V VH = 3.V Unused nputs at VL 45 7 ma Supply Current Over Recommended Operating Conditions (Unless Otherwise Specified) ftoggle = MHz Outputs Open ) The leakage current is due to the internal pull-up resistor on all pins. See nput Buffer section for more information. ) One output at a time for a maximum duration of one second. Vout =.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not % tested. 3) Typical values are at Vcc = 3.3V and TA = 5 C

12 Specifications GAL6LVD AC Switching Characteristics PARAMETER TEST COND. DESCRPTON Over Recommended Operating Conditions -3 MN. MAX. tpd A nput or /O to Combinational Output ns tco A Clock to Output Delay.5 3 ns tcf 3 Clock to Feedback Delay ns tsu Setup Time, nput or Feedback before Clock 3 4 ns th Hold Time, nput or Feedback after Clock ns A Maximum Clock Frequency with 4. MHz External Feedback, /(tsu + tco) fmax 4 A Maximum Clock Frequency with 66 MHz nternal Feedback, /(tsu + tcf) A Maximum Clock Frequency with 5 66 MHz No Feedback twh 4 Clock Pulse Duration, High 3 ns twl 4 Clock Pulse Duration, Low 3 ns ten B nput or /O to Output Enabled ns B OE to Output Enabled ns tdis C nput or /O to Output Disabled ns C OE to Output Disabled ns ) Refer to Switching Test Conditions section. ) Minimum values for tpd and tco are not % tested but established by characterization. 3) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 4) Refer to fmax Descriptions section. Characterized but not % tested. COM Capacitance (T A = 5 C, f =. MHz) SYMBOL PARAMETER TYPCAL UNTS TEST CONDTONS C nput Capacitance 5 pf V CC = 3.3V, V = V C /O /O Capacitance 5 pf V CC = 3.3V, V /O = V MN. COM -5 MAX. UNTS

13 Specifications GAL6LVC Absolute Maximum Ratings () Recommended Operating Conditions Supply voltage V CC....5 to +5.6V nput voltage applied....5 to +5.6V Off-state output voltage applied....5 to +5.6V Storage Temperature to 5 C Ambient Temperature with Power Applied to 5 C.Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Electrical Characteristics Commercial Devices: Ambient Temperature (T A )... to 75 C Supply voltage (V CC ) with Respect to Ground to +3.6V SYMBOL PARAMETER CONDTON MN. TYP. MAX. UNTS VL nput Low Voltage Vss.5. V VH nput High Voltage. 5.5 V L nput or /O Low Leakage Current V VN VL (MAX.) - μa H nput or /O High Leakage Current (VCC -.)V VN VCC μa VCC VN 5.5V 3 ma VOL Output Low Voltage OL = MAX. Vin = VL or VH.4 V OL = 5 μa Vin = VL or VH. V VOH Output High Voltage OH = MAX. Vin = VL or VH.4 V OH = -5 μa Vin = VL or VH Vcc-.45 V OH = - μa Vin = VL or VH Vcc-. V OL Low Level Output Current ma OH High Level Output Current -4 ma OS Output Short Circuit Current VCC = 3.3V VOUT =.5V TA = 5 C - -6 ma COMMERCAL Over Recommended Operating Conditions (Unless Otherwise Specified) CC Operating Power VL =.V VH = 3.V ma Supply Current ftoggle = MHz Outputs Open ) One output at a time for a maximum duration of one second. Vout =.5V was selected to avoid test problems by tester ground degradation. Characterized but not % tested. ) Typical values are at Vcc = 3.3V and TA = 5 C

14 Specifications GAL6LVC AC Switching Characteristics PARAMETER TEST COND. Over Recommended Operating Conditions (Unless Otherwise Specified) DESCRPTON tpd A nput or /O to Combinational Output ns tco A Clock to Output Delay 5 7 ns tcf 3 Clock to Feedback Delay 4 5 ns tsu Setup Time, nput or Feedback before Clock 6 7 ns th Hold Time, nput or Feedback after Clock ns A Maximum Clock Frequency with MHz External Feedback, /(tsu + tco) fmax 4 A Maximum Clock Frequency with MHz nternal Feedback, /(tsu + tcf) A Maximum Clock Frequency with MHz No Feedback twh Clock Pulse Duration, High 5 6 ns twl Clock Pulse Duration, Low 5 6 ns ten B nput or /O to Output Enabled 9 5 ns B OE to Output Enabled 6 5 ns tdis C nput or /O to Output Disabled 9 5 ns C OE to Output Disabled 6 5 ns ) Refer to Switching Test Conditions section. ) Minimum values for tpd and tco are not % tested but established by characterization. 3) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 4) Refer to fmax Descriptions section. Characterized but not % tested. SYMBOL PARAMETER TYPCAL UNTS TEST CONDTONS C nput Capacitance pf V CC = 3.3V, V = V C /O /O Capacitance pf V CC = 3.3V, V /O = V MN. COM -7 MAX. MN. COM Capacitance (T A = 5 C, f =. MHz) - MAX. MN. COM -5 MAX. UNTS 3

15 Specifications GAL6LV Switching Waveforms NPUT or /O FEEDBACK VALD NPUT tsu th NPUT or /O FEEDBACK COMBNATONAL OUTPUT NPUT or /O FEEDBACK COMBNATONAL OUTPUT CLK Combinatorial Output tdis nput or /O to Output Enable/Disable twh /fmax (w/o fb) Clock Width VALD NPUT tpd twl ten CLK REGSTERED OUTPUT OE REGSTERED OUTPUT /fmax (external fdbk) Registered Output OE to Output Enable/Disable CLK REGSTERED FEEDBACK tdis tcf fmax with Feedback tco ten /fmax (internal fdbk) tsu 4

16 Specifications GAL6LV fmax Descriptions CLK LOGC ARRAY REGSTER CLK tsu fmax with External Feedback /(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. LOGC ARRAY tsu + th CLK REGSTER fmax with No Feedback Note: fmax with no feedback may be less than /(twh + twl). This is to allow for a clock duty cycle of other than 5%. tco LOGC ARRAY tcf tpd REGSTER fmax with nternal Feedback /(tsu+tcf) Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = /fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. 5

17 Specifications GAL6LV GAL6LVD: Switching Test Conditions nput Pulse Levels GND to 3.V nput Rise and Fall Times.5ns % 9% nput Timing Reference Levels.5V Output Timing Reference Levels.5V Output Load See Figure GAL6LVD Output Load Conditions (see figure) Test Condition R CL A 5Ω 35pF B High Z to Active High at.9v 5Ω 35pF High Z to Active Low at.v 5Ω 35pF C Active High to High Z at.9v 5Ω 35pF Active Low to High Z at.v 5Ω 35pF GAL6LVC: Switching Test Conditions nput Pulse Levels GND to 3.V nput Rise and Fall Times.5ns % 9% nput Timing Reference Levels.5V Output Timing Reference Levels.5V Output Load See Figure 3-state levels are measured.5v from steady-state active level. GAL6LVC Output Load Conditions (see figure) Test Condition R R CL A 36Ω 34Ω 35pF B Active High 36Ω 34Ω 35pF Active Low 36Ω 34Ω 35pF C Active High 36Ω 34Ω 5pF Active Low 36Ω 34Ω 5pF FROM OUTPUT (O/Q) UNDER TEST TEST PONT Z = 5Ω, CL = 35pF* *C L NCLUDES TEST FXTURE AND PROBE CAPACTANCE FROM OUTPUT (O/Q) UNDER TEST +3.3V R C * L +.45V TEST PONT *C L NCLUDES TEST FXTURE AND PROBE CAPACTANCE R R 6

18 Specifications GAL6LV Electronic Signature Output Register Preload An electronic signature is provided in every GAL6LV device. t contains 64 bits of reprogrammable memory that can contain user defined data. Some uses include user D codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. NOTE: The electronic signature is included in checksum calculations. Changing the electronic signature will alter the checksum. Security Cell A security cell is provided in the GAL6LV devices to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell. Latch-Up Protection GAL6LV devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias minimizes the potential of latch-up caused by negative input undershoots. Device Programming GAL devices are programmed using a Lattice Semiconductor-approved Logic Programmer, available from a number of manufacturers. Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because, in system operation, certain events occur that may throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. GAL6LV devices include circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. f necessary, approved GAL programmers capable of executing text vectors perform output register preload automatically. nput Buffers GAL6LV devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. The GAL6LVD input and /O pins have built-in active pull-ups. As a result, unused inputs and /O's will float to a TTL "high" (logical ""). Lattice Semiconductor recommends that all unused inputs and tri-stated /O pins be connected to another active input, V CC, or Ground. Doing this will tend to improve noise immunity and reduce CC for the device. nput Current (μa) Typical nput Pull-up Characteristic (GAL6LVD) nput Voltage (V)

19 Specifications GAL6LV Power-Up Reset Vcc Vcc (min.) tsu CLK NTERNAL REGSTER Q - OUTPUT FEEDBACK/EXTERNAL OUTPUT REGSTER Circuitry within the GAL6LV provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, μs MAX). As a result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. Because of the asynchronous nature of system power-up, some nput/output Equivalent Schematics PN PN Vcc ESD Protection Circuit ESD Protection Circuit Active Pull-up Circuit (GAL6LVD Only) Vref Vcc Vcc tpr twl nternal Register Reset to Logic "" Device Pin Reset to Logic "" conditions must be met to provide a valid power-up reset of the device. First, the VCC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements. Feedback Data Output Tri-State Control Active Pull-up Circuit (GAL6LVD Only) Vcc Vref PN PN Typ. Vref = Vcc Typ. Vref = Vcc Feedback (To nput Buffer) Typical nput Typical Output

20 Specifications GAL6LV GAL6LVD: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc Normalized Tpd Normalized Tpd. PT H->L.5 PT L->H Supply Voltage (V) Normalized Tpd vs Temp.3.. PT H->L PT L->H Temperature (deg. C) Delta Tpd (ns) Normalized Tco Normalized Tco.5 RSE Delta Tpd vs # of Outputs Switching Number of Outputs Switching Supply Voltage (V) Normalized Tco vs Temp RSE Temperature (deg. C) RSE Delta Tco (ns) Normalized Tsu Normalized Tsu Delta Tco vs # of Outputs Switching Delta Tpd (ns) Delta Tpd vs Output Loading RSE Delta Tco (ns) Number of Outputs Switching Supply Voltage (V) PT H->L PT L->H Normalized Tsu vs Temp PT H->L PT L->H RSE Delta Tco vs Output Loading Temperature (deg. C) RSE Output Loading (pf) Output Loading (pf) 9

21 Specifications GAL6LV GAL6LVD: Typical AC and DC Characteristic Diagrams Vol vs ol Voh vs oh Voh vs oh Delta cc (ma) Normalized cc Vol (V) ol (ma) Normalized cc vs Vcc Supply Voltage (V) Delta cc vs Vin ( input) Vin (V) Voh (V) Normalized cc ik (ma) oh(ma) Normalized cc vs Temp Temperature (deg. C) nput Clamp (Vik) Vik (V) Voh (V) Normalized cc oh(ma) Normalized cc vs Freq Frequency (MHz)

22 Specifications GAL6LV GAL6LVC: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc... Normalized Tpd Normalized Tpd PT H->L. PT L->H Supply Voltage (V) Normalized Tpd vs Temp.3.. PT H->L PT L->H Temperature (deg. C) Delta Tpd (ns) Delta Tpd (ns) Normalized Tco Normalized Tco RSE Delta Tpd vs # of Outputs Switching Number of Outputs Switching Supply Voltage (V) Normalized Tco vs Temp RSE Temperature (deg. C) RSE Delta Tpd vs Output Loading RSE Delta Tco (ns) Delta Tco (ns) Normalized Tsu Normalized Tsu Delta Tco vs # of Outputs Switching Number of Outputs Switching Output Loading (pf) Output Loading (pf) Supply Voltage (V) PT H->L PT L->H Normalized Tsu vs Temp PT H->L PT L->H RSE Delta Tco vs Output Loading 34 3 RSE Temperature (deg. C)

23 Specifications GAL6LV GAL6LVC: Typical AC and DC Characteristic Diagrams Vol vs ol Voh vs oh Voh vs oh 4 3 Normalized cc Vol (V) Delta cc (ma) ol (ma) Normalized cc vs Vcc Supply Voltage (V) Delta cc vs Vin ( input) Vin (V) Voh (V) Normalized cc ik (ma) oh (ma) Normalized cc vs Temp Temperature (deg. C) nput Clamp (Vik) Vik (V) Voh (V) Normalized cc oh (ma) Normalized cc vs Freq Frequency (MHz)