FAST CMOS OCTAL BUFFER/LINE DRIVER
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1 FAST CMOS OCTAL BUFFER/LINE DRIVER IDT54/74FCT244T/AT/CT FEATURES: Std., A, and C grades Low input and output leakage 1µA (max.) CMOS power levels True TTL input and output compatibility: VOH = 3. (typ.) VOL = 0. (typ.) High Drive outputs (-15mA IOH, 64mA IOL) Meets or exceeds JEDEC standard 18 specifications Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Power off disable outputs permit "live insertion" Available in the following packages: Industrial: SOIC, SSOP, QSOP, TSSOP Military: CERDIP, LCC DESCRIPTION: The IDT octal buffer/line driver is built using an advanced dual metal CMOS technology. The FCT244T is designed to be employed as a memory and address driver, clock driver, and bus-oriented transmitter/ receiver which provides improved board density. FUNCTIONAL BLOCK DIAGRAM OEA OEB DA0 OB0 DA1 OB1 DA2 OB2 DA3 OB3 OA0 DB0 OA1 DB1 OA2 DB2 OA3 DB3 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DECEMBER 2016 DSC-5586/5
2 PIN CONFIGURATION OEA DA0 OB0 DA1 OB1 DA2 OB2 DA3 OB3 GND VCC OEB OA0 DB0 OA1 DB1 OA2 DB2 OA3 DB3 INDEX DA1 OB1 DA2 OB2 DA3 OB0 DA0 OB3 GND OEA DB3 VCC OA3 OEB DB2 OA0 DB0 OA1 DB1 OA2 CERDIP/ SOIC/ SSOP/ QSOP/ TSSOP TOP VIEW LCC TOP VIEW ABSOLUTE MAXIMUM RATINGS (1) Symbol Description Max Unit VTERM (2) Terminal Voltage with Respect to GND 0.5 to +7 V VTERM (3) Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V TSTG Storage Temperature 65 to +150 C IOUT DC Output Current 60 to +120 ma 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. 3. Output and I/O terminals only. CAPACITANCE (TA = +25 C, F = 1.0MHz) Symbol Parameter (1) Conditions Typ. Max. Unit CIN Input Capacitance VIN = 6 10 pf COUT Output Capacitance VOUT = 8 12 pf PIN DESCRIPTION Pin Names Description OEA, OEB 3-State Output Enable Inputs (Active LOW) Dxx O x x NOTE: 1. H = HIGH Voltage Level X = Don t Care L = LOW Voltage Level Z = High Impedance Inputs Outputs FUNCTION TABLE (1) Inputs OEA OEB D Outputs L L L L L L H H H H X Z NOTE: 1. This parameter is measured at characterization but not tested. 2
3 DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = 40 C to +85 C, VCC = 5. ±5%; Military: TA = 55 C to +125 C, VCC = 5. ±10% Symbol Parameter Test Conditions (1) Min. Typ. (2) Max. Unit VIH Input HIGH Level Guaranteed Logic HIGH Level 2 V VIL Input LOW Level Guaranteed Logic LOW Level 0.8 V IIH Input HIGH Current (4) VCC = Max. VI = 2.7V ±1 µa IIL Input LOW Current (4) VCC = Max. VI = 0.5V ±1 µa IOZH High Impedance Output Current VCC = Max VO = 2.7V ±1 µa IOZL (3-State output pins) (4) VO = 0.5V ±1 II Input HIGH Current (4) VCC = Max., VI = VCC (Max.) ±1 µa VIK Clamp Diode Voltage VCC = Min, IIN = -18mA V VH Input Hysteresis 200 mv ICC Quiescent Power Supply Current VCC = Max., or VCC ma OUTPUT DRIVE CHARACTERISTICS Symbol Parameter Test Conditions (1) Min. Typ. (2) Max. Unit VOH Output HIGH Voltage VCC = Min IOH = 6mA MIL VIN = VIH or VIL IOH = 8mA IND V IOH = 12mA MIL 2 3 IOH = 15mA IND VOL Output LOW Voltage VCC = Min IOL = 48mA MIL V VIN = VIH or VIL IOL = 64mA IND IOS Short Circuit Current VCC = Max., VO = GND (3) ma 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5., +25 C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. The test limit for this parameter is ±5µA at TA = 55 C. 3
4 POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions (1) Min. Typ. (2) Max. Unit ΔICC Quiescent Power Supply Current VCC = Max ma TTL Inputs HIGH VIN = 3.4V (3) ICCD Dynamic Power Supply VCC = Max. VIN = VCC ma/ Current (4) Outputs Open MHz OEA = OEB = GND One Input Toggling 50% Duty Cycle IC Total Power Supply Current (6) VCC = Max. VIN = VCC ma Outputs Open fi = 10MHz 50% Duty Cycle VIN = 3.4V OEA = OEB = GND One Bit Toggling VCC = Max. VIN = VCC 3 6 (5) Outputs Open fi = 2.5MHz 50% Duty Cycle VIN = 3.4V 5 14 (5) OEA = OEB = GND Eight Bits Toggling 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5., +25 C ambient. 3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of ΔICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ΔICC DHNT + ICCD (fcp/2+ fini) ICC = Quiescent Current ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Output Frequency Ni = Number of Outputs at fi All currents are in milliamps and all frequencies are in megahertz. SWITCHING CHARACTERISTICS OVER OPERATING RANGE 54FCT244T 54/74FCT244AT 54/74FCT244CT Mil. Ind. Mil. Ind. Mil. Symbol Parameter Condition (1) Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max. Unit tplh Propagation Delay CL = 50pF ns tphl Dx to Ox RL = 500Ω tpzh Output Enable Time ns tpzl tphz Output Disable Time ns tplz 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 4
5 TEST CIRCUITS AND WAVEFORMS V CC 7. SWITCH POSITION Pulse Generator VIN R T D.U.T. VOUT 50pF C L 500W 500W Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Test Circuits for All Outputs DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tsu tsu trem th th Set-Up, Hold, and Release Times LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE tw Pulse Width SAME PHASE INPUT TRANSITION OUTPUT OPPOSITE PHASE INPUT TRANSITION tplh tplh Propagation Delay tphl tphl VOH VOL CONTROL INPUT OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH ENABLE tpzl SWITCH CLOSED tpzh SWITCH OPEN 3.5V tphz DISABLE tplz Enable and Disable Times V VOL VOH 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tf 2.5ns; tr 2.5ns. 5
6 ORDERING INFORMATION XX FCT Temp. Range XXXX Device Type XX Package X Process X X Blank 8 Tube Tape and Reel G Green Blank B Industrial MIL-STD-883, Class B SO PY Q PG Industrial Options Small Outline IC (PSG20) Shrink Small Outline Package (PYG20) Quarter-size Small Outline Package (PCG20) Thin Shrink Small Outline Package (PGG20) D L Military Options CERDIP (CD20) Leadless Chip Carrier (LC20) 244T 244AT 244CT Fast CMOS Octal Buffer/Line Driver C to +125 C 40 C to +85 C Datasheet Document History 09/29/2009 Pg. 6 Updated the ordering information by removing the "IDT" notation and non RoHS part. 12/12/2016 Pg. 6. Updated the ordering information by adding detailed package information and Tape & Reel. CORPORATE HEADQUARTERS for SALES: for Tech Support: 6024 Silver Creek Valley Road or logichelp@idt.com San Jose, CA fax:
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SEICONDUCTOR TECHNICAL DATA Ω The is designed for asynchronous communication between data buses. The device tramits data from the A bus to the B bus or from the B bus to the A bus depending upon the logic
SN54BCT760, SN74BCT760 OCTAL BUFFERS/DRIVERS WITH OPEN-COLLECTOR OUTPUTS
SNBCT0, SNBCT0 SCBS0B JULY REVISED NOVEMBER Open-Collector Version of BCT Open-Collector Outputs Drive Bus Lines or Buffer Memory Address Registers ESD Protection Exceeds 000 V Per MIL-STD-C Method 0 Packages
CMOS PARALLEL-TO-SERIAL FIFO 1,024 x 16
CMOS PARALLEL-TO-SERIAL FIFO IDT72125 FEATURES: 25ns parallel port access time, 35ns cycle time 50MHz serial shift frequency ide x16 organization offering easy expansion Low power consumption (50mA typical)
PAL22V10 Family, AmPAL22V10/A
FINAL COM L: -7//5 PAL22V Family, AmPAL22V/A 24-Pin TTL Versatile PAL Device Advanced Micro Devices DISTINCTIVE CHARACTERISTICS As fast as 7.5-ns propagation delay and 9 MHz fmax (external) Macrocells
3.3V CMOS Static RAM for Automotive Applications 4 Meg (256K x 16-Bit)
.V CMOS Static RAM for Automotive Applicatio Meg (25K x -Bit) IDTVYS IDTVYL Features 25K x advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise. Equal access and cycle
AT28C K (32K x 8) Paged CMOS E 2 PROM. Features. Description. Pin Configurations
AT28C256 Features Fast Read Access Time - 150 ns Automatic Page Write Operation Internal Address and Data Latches for 64-Bytes Internal Control Timer Fast Write Cycle Times Page Write Cycle Time: 3 ms
AT28C16. 16K (2K x 8) CMOS E 2 PROM. Features. Description. Pin Configurations
Features Fast Read Access Time - 150 ns Fast Byte Write - 200 µs or 1 ms Self-Timed Byte Write Cycle Internal Address and Data Latches Internal Control Timer Automatic Clear Before Write Direct Microprocessor
EFA PAEA WCLKB WENB1 WENB2 FFA WRITE CONTROL LOGIC WRITE POINTER RESET LOGIC RSB
3.3 VOLT DUAL CMOS SyncFIFO DUAL 256 X, DUAL 512 X, DUAL 1,24 X, DUAL 2,48 X, DUAL 4,6 X, DUAL 8,12 X LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 218 FEATURES: The IDT72V81 is
128Kx8 CMOS MONOLITHIC EEPROM SMD
128Kx8 CMOS MONOLITHIC EEPROM SMD 5962-96796 WME128K8-XXX FEATURES Read Access Times of 125, 140, 150, 200, 250, 300ns JEDEC Approved Packages 32 pin, Hermetic Ceramic, 0.600" DIP (Package 300) 32 lead,
IDT7134SA/LA. HIGH-SPEED 4K x 8 DUAL-PORT STATIC SRAM
Features High-speed access : 5/45//7 (max.) Industrial: / (max.) Commercial: 2//5/45//7 (max.) Low-power operation IDT714 Active: 7mW (typ.) Standby: 5mW (typ.) IDT714 Active: 7mW (typ.) Standby: 1mW (typ.)
HIGH-SPEED 4K x 8 FourPort TM STATIC RAM
Features High-speed access Commercial: // (max.) Industrial: (max.) ow-power operation IDT754 Active: 75mW (typ.) tandby: 7.5mW (typ.) IDT754 Active: 75mW (typ.) tandby: mw (typ.) True FourPort memory
CMOS SyncFIFO TM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18 INPUT REGISTER WRITE CONTROL LOGIC
CMOS SyncFIFO TM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18 IDT72205LB, IDT72215LB, IDT72225LB, IDT72235LB, IDT72245LB LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE
CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9
Integrated evice Technology, Inc. CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 124 X 9, 248 X 9 and 496 x 9 IT72421 IT7221 IT72211 IT72221 IT72231 IT72241 FEATURES: 64 x 9-bit organization (IT72421) 256 x 9-bit
DUAL TTL-to-DIFFERENTIAL PECL TRANSLATOR
DUAL TTL-to-DIFFERENTIAL PECL TRANSLATOR FEATURES DESCRIPTION 300ps typical propagation delay
AT29C K (32K x 8) 5-volt Only CMOS Flash Memory. Features. Description. Pin Configurations
Features Fast Read Access Time - 70 ns 5-Volt-Only Reprogramming Page Program Operation Single Cycle Reprogram (Erase and Program) Internal Address and Data Latches for 64-Bytes Internal Program Control
3.3 VOLT CMOS SyncBiFIFO TM 16,384 x 36 x 2 32,768 x 36 x 2 65,536 x 36 x 2. Mail 1. Register. RAM ARRAY 16,384 x 36 32,768 x 36 65,536 x 36
FEATURES Memory storage capacity: IDT72V3682 16,384 x 36 x 2 IDT72V3692 32,768 x 36 x 2 IDT72V36102 65,536 x 36 x 2 Supports clock frequencies up to 100MHz Fast access times of 6.5ns Free-running and may
BUS SWITCHES PROVIDE 5V AND 3V LOGIC CONVERSION WITH ZERO DELAY. Figure 1. 5V & 3V Logic Mixture in PC Design
BUS SWITCHES PROVIDE 5V AND 3V LOGIC CONVERSION WITH ZERO DELAY APPLICATION NOTE AN-11A ABSTRACT Battery operated computer systems, such as notebook computers, need support logic with a combination of
2.5 V/3.3 V, 1-Bit, 2-Port Level Translator Bus Switch in SOT-66 ADG3241
2. V/3.3 V, -Bit, 2-Port Level Translator Bus Switch in SOT-66 ADG324 FEATURES FUNCTIONAL BLOCK DIAGRAM 22 ps propagation delay through the switch A B 4. Ω switch connection between ports Data rate. Gbps
SN54F38, SN74F38 QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS
SNF, SN7F SDFS0A MARCH 7 REVISED OCTOBER Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 00-mil DIPs description These devices contain four
Rev. No. History Issue Date Remark
Preliminary 512K X 8 OTP CMOS EPROM Document Title 512K X 8 OTP CMOS EPROM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue June 17, 1998 Preliminary 1.0 Change CE from VIL to VIH
COM L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/20/25. Programmable AND Array (44 x 132) OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL
FINAL COM L: H-5/7//5/25, -/5/25 IND: H-/5/2/25 PALCE22V Family 24-Pin EE CMOS Versatile PAL Device DISTINCTIVE CHARACTERISTICS As fast as 5-ns propagation delay and 42.8 MHz fmax (external) Low-power
AT24C01A/02/04/08/16. 2-Wire Serial CMOS E 2 PROM. Features. Description. Pin Configurations. 1K (128 x 8) 2K (256 x 8) 4K (512 x 8) 8K (1024 x 8)
AT24C01A/02/04/08/16 Features Low Voltage and Standard Voltage Operation 5.0 (V CC = 4.5V to 5.5V) 2.7 (V CC = 2.7V to 5.5V) 2.5 (V CC = 2.5V to 5.5V) 1.8 (V CC = 1.8V to 5.5V) Internally Organized 128
ICS548A-03 LOW SKEW CLOCK INVERTER AND DIVIDER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS548A-03 Description The ICS548A-03 is a low cost, low skew, high-performance general purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-two.
2.5 V/3.3 V, 2-Bit Common Control Level Translator Bus Switch ADG3242
2.5 V/3.3 V, 2-Bit Common Control Level Translator Bus Switch ADG3242 FEATURES 225 ps propagation delay through the switch 4.5 Ω switch connection between ports Data rate 1.5 Gbps 2.5 V/3.3 V supply operation
DATASHEET HCS109MS. Features. Pinouts. Description. Ordering Information. Radiation Hardened Dual JK Flip Flop. FN2466 Rev 2.
DATASHEET HCS109MS Radiation Hardened Dual JK Flip Flop FN2466 Rev 2.00 Features 3 Micron Radiation Hardened SOS CMOS Total Dose 200K RAD (Si) SEP Effective LET No Upsets: >100 MEV-cm 2 /mg Single Event
74AC11139 DUAL 2-LINE DECODER/DEMULTIPLEXER
Designed Specifically for High-Speed Memory Decoders and Data Tramission Systems Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception Center-Pin V CC and GND Configuratio Minimize
MC1488, SN55188, SN75188 QUADRUPLE LINE DRIVERS
Meet or Exceed the Requirements of ANSI EIA/ TIA--E and ITU Recommendation V. Designed to Be Interchangeable With Motorola MC1 Current-Limited Output: ma Typical Power-Off Output Impedance: Ω Minimum Slew
2-Megabit (256K x 8) 5-volt Only CMOS Flash Memory AT29C020. Features. Description. Pin Configurations
Features Fast Read Access Time - 90 ns 5-Volt-Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 1024 Sectors (256 bytes/sector) Internal Address and Data Latches for
AS6C K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0 Rev. 1.1 Initial Issue Add package 48-ball 8mm 10mm TFBGA Revised ORDERING INFORMATION in page 11 Jan.09.2012 July.12.2013 0 FEATURES Fast access
ISSI IS25C02 IS25C04 2K-BIT/4K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM FEATURES DESCRIPTION. Advanced Information January 2005
2K-BIT/4K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM January 2005 FEATURES Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) Low power CMOS Active current less than 3.0
LP621024E-I Series 128K X 8 BIT CMOS SRAM. Document Title 128K X 8 BIT CMOS SRAM. Revision History. AMIC Technology, Corp.
128K X 8 BIT CMOS SRAM Document Title 128K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue January 14, 2008 Preliminary 1.0 Final version release September 21, 2010
8K X 8 BIT LOW POWER CMOS SRAM
February 2007 FEATURES Access time :55ns Low power consumption: Operation current : 15mA (TYP.), VCC = 3.0V Standby current : 1µ A (TYP.), VCC = 3.0V Wide range power supply : 2.7 ~ 5.5V Fully Compatible
description VCC 1PRE 1OC 1D1 1C 1Q1 1Q2 1Q3 1Q4 2Q1 2Q2 2Q3 2Q4 2C 2PRE 1D2 1D3 1D4 2D1 2D2 2D3 2D4 2OC GND 1PRE 1OC 1Q1 1D1 1Q2 1Q3 1Q4 1D2 1D3 1D4
3-tate Buffer-Type Outputs Drive Bus Lines Directly Bus-tructured Pinout AL873B is Alternative Version With Noninverting Outputs Package Optio Include Plastic mall Outline Packages, Both Plastic and Ceramic
NOT RECOMMENDED FOR NEW DESIGNS SINGLE SUPPLY QUAD PECL/TTL-TO-PECL
NOT RECOMMENDED FOR NEW DESIGNS Micrel, Inc. SINGLE SUPPLY QUAD PECL/TTL-TO-PECL FEATURES Quad PECL version of popular ECLinPS E Low skew Guaranteed skew spec TTL enable input Selectable TTL or PECL clock
24AA128/24LC128/24FC128
18K I C CMOS Serial EEPROM Device Selection Table Part Number Range Max. Clock Frequency Temp. Ranges Temperature ranges: - Industrial (I): -0 C to +8 C - Automotive (E): -0 C to +1 C A8 1.-.V 00 khz (1)
Am27C128. Advanced Micro Devices. 128 Kilobit (16,384 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM FINAL
FINAL 128 Kilobit (16,384 x 8-Bit) CMOS EPROM Advanced Micro Devices DISTINCTIVE CHARACTERISTICS Fast access time 45 ns Low power consumption 20 µa typical CMOS standby current JEDEC-approved pinout Single
ISSI IS23SC4418 IS23SC KBYTE EEPROM WITH WRITE PROTECT FUNCTION AND PROGRAMMABLE SECURITY CODE (PSC) IS23SC4418 IS23SC4428 FEATURES DESCRIPTION
1-KBYTE EEPROM WITH WRITE PROTECT FUNCTION AND PROGRAMMABLE SECURITY CODE (PSC) NOVEMBER 2001 FEATURES Standard CMOS process 1024 x 8 bits EEPROM organization Byte-wise addressing Byte-wise erase/write
ISSI Preliminary Information January 2006
2K-BIT/4K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM January 2006 FEATURES Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) Low-voltage Operation Vcc = 1.8V to 5.5V Low
Low Voltage 1.65 V to 3.6 V, Bidirectional Logic Level Translation, Bypass Switch ADG3233
Data Sheet Low Voltage. V to. V, Bidirectional Logic Level Translation, Bypass Switch ADG FEATURES Operates from. V to. V supply rails Bidirectional level translation, unidirectional signal path -lead
ATF16V8B. High Performance Flash PLD. Features. Block Diagram. Description. Pin Configurations
Features Industry Standard Architecture Emulates Many 20-Pin PALs Low Cost Easy-to-Use Software Tools High Speed Electrically Erasable Programmable Logic Devices 7.5 ns Maximum Pin-to-Pin Delay Several
IDTVP386. General Description. Features. Block Diagram DATASHEET ADVANCE INFORMATION 8/28-BIT LVDS RECEIVER FOR VIDEO
DATASHEET ADVANCE INFORMATION IDTVP386 General Description The VP386 is an ideal LVDS receiver that converts 4-pair LVDS data streams into parallel 28 bits of CMOS/TTL data with bandwidth up to 2.8 Gbps
AS6C6264 8K X 8 BIT LOW POWER CMOS SRAM REVISION HISTORY. Feb
REVISION HISTORY Revision Description Issue Date 1.0 Initial issue Feb 2007 2.0 Add-in industrial temperature option for 28-pin 600 July 2017 mil PDIP. Standby current(isb1) reduced to be 20uA for I-grade