GAL16V8. Specifications GAL16V8 PROGRAMMABLE AND-ARRAY (64 X 32) High Performance E 2 CMOS PLD Generic Array Logic DIP PLCC GAL 16V8 GAL16V8
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1 Specifications GALV GALV High Performance E CMOS PLD Generic Array Logic FEATURES FUNCTONAL BLOCK DAGRAM HGH PERFORMANCE E CMOS TECHNOLOGY 5 ns Maximum Propagation Delay Fmax = MHz ns Maximum from Clock nput to Data Output UltraMOS Advanced CMOS Technology /CLK CLK /O/Q 5% to 75% REDUCTON N POWER FROM BPOLAR 75mA Typ cc on Low Power Device 5mA Typ cc on Quarter Power Device /O/Q ACTVE PULL-UPS ON ALL PNS E CELL TECHNOLOGY Reconfigurable Logic Reprogrammable Cells % Tested/Guaranteed % Yields High Speed Electrical Erasure (<ms) Year Data Retention EGHT OUTPUT LOGC MACROCELLS Maximum Flexibility for Complex Logic Designs Programmable Output Polarity Also Emulates -pin PAL Devices with Full Function/Fuse Map/Parametric Compatibility PRELOAD AND POWER-ON RESET OF ALL REGSTERS % Functional Testability PROGRAMMABLE AND-ARRAY ( X 3) /O/Q /O/Q /O/Q /O/Q APPLCATONS NCLUDE: DMA Control State Machine Control High Speed Graphics Processing Standard Logic Speed Upgrade ELECTRONC SGNATURE FOR DENTFCATON OE /O/Q /O/Q /OE DESCRPTON PN CONFGURATON The GALVC, at 5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E ) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (<ms) allow the devices to be reprogrammed quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell () to be configured by the user. An important subset of the many architecture configurations possible with the GALV are the PAL architectures listed in the table of the macrocell description section. GALV devices are capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor guarantees % field programmability and functionality of all GAL products. n addition, erase/write cycles and data retention in excess of years are guaranteed. PLCC /CLK Vcc /O/Q GALV Top View 9 3 GND /OE /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /CLK GND 5 DP GAL V 5 Vcc /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /OE Copyright 99 Lattice Semiconductor Corporation. E CMOS, GAL, ispgal, ispls, pls, pds, Silicon Forest, UltraMOS, L with Lattice Semiconductor Corp. and L (Stylized) are registered trademarks of Lattice Semiconductor Corporation (LSC). The LSC Logo, Generic Array Logic, n-system Programmability, n-system Programmable, SP, ispate, ispcode, ispdownload, ispgds, ispstarter, ispstream, isptest, ispturbo, Latch-Lock, pds+, RFT, Total SP and Twin GLB are trademarks of Lattice Semiconductor Corporation. SP is a service mark of Lattice Semiconductor Corporation. All brand names or product names mentioned are trademarks or registered trademarks of their respective holders. LATTCE SEMCONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97, U.S.A. Tel. (53) -; --SP-PLDS; FAX (53) -337; Data Book 99 Data Book
2 Specifications GALV GALV ORDERNG NFORMATON Commercial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # GALVC-5LP 5 GALVC-5LJ -Pin Plastic DP -Lead PLCC Package GALVC-7LP -Pin Plastic DP 5 GALVC-7LJ -Lead PLCC 5 GALVB-7LP 5 GALVB-7LJ 7 5 GALVB-LP 5 GALVB-LJ 5 55 GALVB-5QP 55 GALVB-5QJ -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC 9 GALVB-5LP 9 GALVB-5LJ GALVB-5QP 55 GALVB-5QJ 9 GALVB-5LP 9 GALVB-5LJ -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC ndustrial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # GALVC-7LP 3 GALVC-7LJ 7 3 GALVB-LP 3 GALVB-LJ 5 3 GALVB-5LP 3 GALVB-5LJ 3 5 GALVB-QP 5 GALVB-QJ GALVB-5QP 5 GALVB-5QJ 3 GALVB-5LP 3 GALVB-5LJ -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC -Pin Plastic DP -Lead PLCC Package PART NUMBER DESCRPTON _ XXXXXXXX XX X X X GALVC GALVB Device Name Speed (ns) Grade Blank = Commercial = ndustrial L = Low Power Q = Quarter Power Power Package P = Plastic DP J = PLCC 3-99 Data Book
3 Specifications GALV OUTPUT LOGC MACROCELL () The following discussion pertains to configuring the output logic macrocell. t should be noted that actual implementation is accomplished by development software/hardware and is completely transparent to the user. There are three global configuration modes possible: simple, complex, and registered. Details of each of these modes are illustrated in the following pages. Two global bits, SYN and AC, control the mode configuration for all macrocells. The XOR bit of each macrocell controls the polarity of the output in any of the three modes, while the AC bit of each of the macrocells controls the input/output configuration. These two global and individual architecture bits define all possible configurations in a GALV. The information given on these architecture bits is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits. The following is a list of the PAL architectures that the GALV can emulate. t also shows the mode under which the GALV emulates the PAL architecture. PAL Architectures Emulated by GALV R R R RP RP RP L H P L L L L H H H H P P P P GALV Global Mode Registered Registered Registered Registered Registered Registered Complex Complex Complex COMPLER SUPPORT FOR Software compilers support the three different global modes as different device types. These device types are listed in the table below. Most compilers have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force the software to choose the complex mode. The software will choose the simple mode only when all outputs are dedicated combinatorial without OE control. The different device types listed in the table can be used to override the automatic device selection by the software. For further details, refer to the compiler software manuals. n registered mode pin and pin are permanently configured as clock and output enable, respectively. These pins cannot be configured as dedicated inputs in the registered mode. n complex mode pin and pin become dedicated inputs and use the feedback paths of pin 9 and pin respectively. Because of this feedback path usage, pin 9 and pin do not have the feedback option in this mode. n simple mode all feedback paths of the output pins are routed via the adjacent pins. n doing so, the two inner most pins ( pins 5 and ) will not have the feedback option as these pins are always configured as dedicated combinatorial output. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. Registered Complex Auto Mode Select ABEL PVR PVC PVAS PV CUPL GVMS GVMA GVAS GV LOG/iC GALV_R GALV_C7 GALV_C GALV OrCAD-PLD "Registered" "Complex" "" GALVA PLDesigner PVR PVC PVC PVA TANGO-PLD GVR GVC GVAS 3 GV ) Used with Configuration keyword. ) Prior to Version. support. 3) Supported on Version. or later Data Book
4 Specifications GALV REGSTERED MODE n the Registered mode, macrocells are configured as dedicated registered outputs or as /O functions. Architecture configurations available in this mode are similar to the common R and RP devices with various permutations of polarity, /O and register placement. All registered macrocells share common clock and output enable control pins. Any macrocell can be configured as registered or /O. Up to eight registers or up to eight /O's are possible in this mode. Dedicated input or output functions can be implemented as subsets of the /O function. Registered outputs have eight product terms per output. /O's have seven product terms per output. The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are shown on the logic diagram on the following page. CLK Registered Configuration for Registered Mode XOR D Q Q - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this output configuration. - Pin controls common CLK for the registered outputs. - Pin controls common OE for the registered outputs. - Pin & Pin are permanently configured as CLK & OE. OE Combinatorial Configuration for Registered Mode XOR - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this output configuration. - Pin & Pin are permanently configured as CLK & OE. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically Data Book
5 Specifications GALV REGSTERED MODE LOGC DAGRAM DP & PLCC Package Pinouts PTD 9 XOR- AC- 5 3 XOR-9 AC XOR-5 AC XOR-5 AC-3 5 XOR-5 AC- 7 5 XOR-53 AC XOR-5 AC XOR-55 AC-7 OE SYN-9 AC Data Book
6 Specifications GALV COMPLEX MODE n the Complex mode, macrocells are configured as output only or /O functions. Architecture configurations available in this mode are similar to the common L and P devices with programmable polarity in each macrocell. Up to six /O's are possible in this mode. Dedicated inputs or outputs can be implemented as subsets of the /O function. The two outer most macrocells (pins & 9) do not have input capability. Designs requiring eight /O's can be implemented in the Registered mode. All macrocells have seven product terms per output. One product term is used for programmable output enable control. Pins and are always available as data inputs into the AND array. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page. Combinatorial /O Configuration for Complex Mode XOR - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC=. - Pin 3 through Pin are configured to this function. Combinatorial Output Configuration for Complex Mode XOR - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC=. - Pin and Pin 9 are configured to this function. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically Data Book
7 Specifications GALV COMPLEX MODE LOGC DAGRAM DP & PLCC Package Pinouts PTD XOR- AC XOR-9 AC XOR-5 AC XOR-5 AC-3 XOR-5 AC XOR-53 AC XOR-5 AC XOR-55 AC-7 9 SYN-9 AC Data Book
8 Specifications GALV SMPLE MODE n the mode, macrocells are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. Architecture configurations available in this mode are similar to the common L and P devices with many permutations of generic output polarity or input choices. Pins and are always available as data inputs into the AND array. The center two macrocells (pins 5 & ) cannot be used as input or /O pins, and are only available as dedicated outputs. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram. All outputs in the simple mode have a maximum of eight product terms that can control the logic. n addition, each output has programmable polarity. Vcc Combinatorial Output with Feedback Configuration for Mode XOR - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this configuration. - All except pins 5 & can be configured to this function. XOR Vcc Combinatorial Output Configuration for Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this configuration. - Pins 5 & are permanently configured to this function. Dedicated nput Configuration for Mode - SYN=. - AC=. - XOR= defines Active Low Output. - XOR= defines Active High Output. - AC= defines this configuration. - All except pins 5 & can be configured to this function. Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically Data Book
9 Specifications GALV SMPLE MODE LOGC DAGRAM DP & PLCC Package Pinouts PTD XOR- AC XOR-9 AC XOR-5 AC XOR-5 AC-3 XOR-5 AC XOR-53 AC XOR-5 AC XOR-55 AC-7 9 SYN-9 AC Data Book
10 Specifications GALVC ABSOLUTE MAXMUM RATNGS () RECOMMENDED OPERATNG COND. Supply voltage V CC....5 to +7V nput voltage applied....5 to V CC +.V Off-state output voltage applied....5 to V CC +.V Storage Temperature... 5 to 5 C Ambient Temperature with Power Applied to 5 C.Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). Commercial Devices: Ambient Temperature (T A )... to 75 C Supply voltage (V CC ) with Respect to Ground to +5.5V ndustrial Devices: Ambient Temperature (T A )... to 5 C Supply voltage (V CC ) with Respect to Ground to +5.5V DC ELECTRCAL CHARACTERSTCS Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER CONDTON MN. TYP. 3 MAX. UNTS VL nput Low Voltage Vss.5. V VH nput High Voltage. Vcc+ V L nput or /O Low Leakage Current V VN VL (MAX.) µa H nput or /O High Leakage Current 3.5V VN VCC µa VOL Output Low Voltage OL = MAX. Vin = VL or VH.5 V VOH Output High Voltage OH = MAX. Vin = VL or VH. V OL Low Level Output Current ma OH High Level Output Current 3. ma OS Output Short Circuit Current VCC = 5V VOUT =.5V T A = 5 C 3 5 ma COMMERCAL CC Operating Power VL =.5V VH = 3.V L -5/ ma Supply Current ftoggle = 5MHz Outputs Open NDUSTRAL CC Operating Power VL =.5V VH = 3.V L ma Supply Current ftoggle = 5MHz Outputs Open ) The leakage current is due to the internal pull-up resistor on all pins. See nput Buffer section for more information. ) One output at a time for a maximum duration of one second. Vout =.5V was selected to avoid test problems caused by tester ground degradation. Guaranteed but not % tested. 3) Typical values are at Vcc = 5V and TA = 5 C Data Book
11 Specifications GALVC AC SWTCHNG CHARACTERSTCS Over Recommended Operating Conditions COM COM ND PARAMETER TEST DESCRPTON COND. MN. MAX. MN. MAX. MN. MAX. UNTS tpd A nput or /O to outputs switching ns Comb. Output output switching 7 ns tco A Clock to Output Delay 5 5 ns tcf Clock to Feedback Delay ns tsu Setup Time, nput or Feedback before Clock ns th Hold Time, nput or Feedback after Clock ns A Maximum Clock Frequency with MHz External Feedback, /(tsu + tco) fmax 3 A Maximum Clock Frequency with MHz nternal Feedback, /(tsu + tcf) A Maximum Clock Frequency with MHz No Feedback twh Clock Pulse Duration, High ns twl Clock Pulse Duration, Low ns ten B nput or /O to Output Enabled ns B OE to Output Enabled ns tdis C nput or /O to Output Disabled ns C OE to Output Disabled 5.5 ns ) Refer to Switching Test Conditions section. ) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 3) Refer to fmax Descriptions section. Characterized initially and after any design or process changes that may affect these parameters. CAPACTANCE (T A = 5 C, f =. MHz) SYMBOL PARAMETER MAXMUM* UNTS TEST CONDTONS C nput Capacitance pf V CC = 5.V, V =.V C /O /O Capacitance pf V CC = 5.V, V /O =.V *Guaranteed but not % tested Data Book
12 Specifications GALVB ABSOLUTE MAXMUM RATNGS () RECOMMENDED OPERATNG COND. Supply voltage V CC....5 to +7V nput voltage applied....5 to V CC +.V Off-state output voltage applied....5 to V CC +.V Storage Temperature... 5 to 5 C Ambient Temperature with Power Applied to 5 C.Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). Commercial Devices: Ambient Temperature (T A )... to 75 C Supply voltage (V CC ) with Respect to Ground to +5.5V ndustrial Devices: Ambient Temperature (T A )... to 5 C Supply voltage (V CC ) with Respect to Ground to +5.5V DC ELECTRCAL CHARACTERSTCS Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER CONDTON MN. TYP. 3 MAX. UNTS VL nput Low Voltage Vss.5. V VH nput High Voltage. Vcc+ V L nput or /O Low Leakage Current V VN VL (MAX.) µa H nput or /O High Leakage Current 3.5V VN VCC µa VOL Output Low Voltage OL = MAX. Vin = VL or VH.5 V VOH Output High Voltage OH = MAX. Vin = VL or VH. V OL Low Level Output Current ma OH High Level Output Current 3. ma OS Output Short Circuit Current VCC = 5V VOUT =.5V T A = 5 C 3 5 ma COMMERCAL CC Operating Power VL =.5V VH = 3.V L -7/ ma Supply Current ftoggle = 5MHz Outputs Open L -5/ ma NDUSTRAL Q -5/ ma CC Operating Power VL =.5V VH = 3.V L -/-5/ ma Supply Current ftoggle = 5MHz Outputs Open Q -/ ma ) The leakage current is due to the internal pull-up resistor on all pins. See nput Buffer section for more information. ) One output at a time for a maximum duration of one second. Vout =.5V was selected to avoid test problems caused by tester ground degradation. Guaranteed but not % tested. 3) Typical values are at Vcc = 5V and TA = 5 C Data Book
13 Specifications GALVB AC SWTCHNG CHARACTERSTCS PARAM. TEST COND. DESCRPTON Over Recommended Operating Conditions tpd A nput or /O to outputs switching ns Comb. Output output switching 7 ns tco A Clock to Output Delay 5 7 ns tcf Clock to Feedback Delay 3 9 ns tsu Setup Time, nput or Fdbk before Clk ns th Hold Time, nput or Fdbk after Clk ns A Maximum Clock Frequency with MHz External Feedback, /(tsu + tco) fmax 3 A Maximum Clock Frequency with MHz nternal Feedback, /(tsu + tcf) A Maximum Clock Frequency with MHz No Feedback twh Clock Pulse Duration, High 5 ns twl Clock Pulse Duration, Low 5 ns ten B nput or /O to Output Enabled ns B OE to Output Enabled 5 ns tdis C nput or /O to Output Disabled ns C OE to Output Disabled ns ) Refer to Switching Test Conditions section. ) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 3) Refer to fmax Descriptions section. CAPACTANCE (T A = 5 C, f =. MHz) COM COM / ND COM / ND ND COM / ND MN. MN. MAX. MN. MAX. MN. MAX. MN. SYMBOL PARAMETER MAXMUM* UNTS TEST CONDTONS C nput Capacitance pf V CC = 5.V, V =.V C /O /O Capacitance pf V CC = 5.V, V /O =.V *Guaranteed but not % tested. MAX. MAX. UNTS Data Book
14 Specifications GALV SWTCHNG WAVEFORMS NPUT or /O FEEDBACK VALD NPUT tsu th NPUT or /O FEEDBACK VALD NPUT CLK tco COMBNATONAL OUTPUT tpd REGSTERED OUTPUT /fmax (external fdbk) Combinatorial Output Registered Output NPUT or /O FEEDBACK OE tdis ten tdis ten COMBNATONAL OUTPUT REGSTERED OUTPUT nput or /O to Output Enable/Disable OE to Output Enable/Disable twh twl CLK CLK /fmax (w/o fb) Clock Width REGSTERED FEEDBACK /fmax (internal fdbk) tcf tsu fmax with Feedback Data Book
15 Specifications GALV fmax DESCRPTONS CLK LOGC ARRAY REGSTER CLK LOGC ARRAY tsu tco REGSTER fmax with External Feedback /(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. CLK tcf tpd LOGC ARRAY tsu + th REGSTER fmax with No Feedback Note: fmax with no feedback may be less than /(twh + twl). This is to allow for a clock duty cycle of other than 5%. SWTCHNG TEST CONDTONS fmax with nternal Feedback /(tsu+tcf) Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = /fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. +5V nput Pulse Levels GND to 3.V R nput Rise and GALVB 3ns % 9% Fall Times GALVC.5ns % 9% nput Timing Reference Levels.5V Output Timing Reference Levels.5V FROM OUTPUT (O/Q) UNDER TEST TEST PONT Output Load See Figure R C * L 3-state levels are measured.5v from steady-state active level. *C L NCLUDES TEST FXTURE AND PROBE CAPACTANCE GALVB Output Load Conditions (see figure) Test Condition R R CL A Ω 39Ω 5pF B Active High 39Ω 5pF Active Low Ω 39Ω 5pF C Active High 39Ω 5pF Active Low Ω 39Ω 5pF GALVC Output Load Conditions (see figure) Test Condition R R CL A Ω Ω 5pF B Active High Ω 5pF Active Low Ω Ω 5pF C Active High Ω 5pF Active Low Ω Ω 5pF Data Book
16 Specifications GALV ELECTRONC SGNATURE An electronic signature is provided in every GALV device. t contains bits of reprogrammable memory that can contain user defined data. Some uses include user D codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. NOTE: The electronic signature is included in checksum calculations. Changing the electronic signature will alter the checksum. SECURTY CELL A security cell is provided in the GALV devices to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell. LATCH-UP PROTECTON GALV devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias minimizes the potential of latch-up caused by negative input undershoots. Additionally, outputs are designed with n-channel pull-ups instead of the traditional p-channel pull-ups in order to eliminate latch-up due to output overshoots. OUTPUT REGSTER PRELOAD When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because, in system operation, certain events occur that may throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. GALV devices include circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. f necessary, approved GAL programmers capable of executing text vectors perform output register preload automatically. NPUT BUFFERS GALV devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. The GALV input and /O pins have built-in active pull-ups. As a result, unused inputs and /O's will float to a TTL "high" (logical ""). Lattice Semiconductor recommends that all unused inputs and tri-stated /O pins be connected to another active input, VCC, or Ground. Doing this will tend to improve noise immunity and reduce CC for the device. DEVCE PROGRAMMNG GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers. Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. nput Current (ua) - - Typical nput Pull-up Characteristic nput Voltage (Volts) 3-99 Data Book
17 Specifications GALV POWER-UP RESET Vcc Vcc (min.) tsu CLK twl NTERNAL REGSTER Q - OUTPUT tpr nternal Register Reset to Logic "" FEEDBACK/EXTERNAL OUTPUT REGSTER Device Pin Reset to Logic "" Circuitry within the GALV provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, µs MAX). As a result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. Because of the asynchronous nature of system power-up, some NPUT/OUTPUT EQUVALENT SCHEMATCS conditions must be met to guarantee a valid power-up reset of the device. First, the VCC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements. PN PN Feedback Active Pull-up Circuit Vcc Active Pull-up Circuit Vcc ESD Protection Circuit Vref Vcc Tri-State Control Vcc Vref PN Data Output PN ESD Protection Circuit Typ. Vref = 3.V Typ. Vref = 3.V Feedback (To nput Buffer) Typical nput Typical Output 3-99 Data Book
18 Specifications GALV GAL VC-5/-7: TYPCAL AC AND DC CHARACTERSTC DAGRAMS Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc... Normalized Tpd..9 Normalized Tco..9 RSE Normalized Tsu Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp.3.3. Normalized Tpd...9. Normalized Tco...9. RSE Normalized Tsu Delta Tpd vs # of Outputs Switching Delta Tco vs # of Outputs Switching Delta Tpd (ns) RSE Delta Tco (ns) RSE Number of Outputs Switching Number of Outputs Switching Delta Tpd vs Output Loading Delta Tco vs Output Loading Delta Tpd (ns) RSE Delta Tco (ns) RSE Output Loading (pf) Output Loading (pf) 3-99 Data Book
19 Specifications GALV GAL VC-5/-7: TYPCAL AC AND DC CHARACTERSTC DAGRAMS Vol vs ol Voh vs oh Voh vs oh Vol (V) Voh (V) 3 Voh (V) ol (ma) oh(ma) oh(ma) Normalized cc vs Vcc Normalized cc vs Temp Normalized cc vs Freq Normalized cc...9 Normalized cc...9 Normalized cc Frequency (MHz) Delta cc vs Vin ( input) nput Clamp (Vik) Delta cc (ma) Vin (V) ik (ma) Vik (V) Data Book
20 Specifications GALV GAL VB-7/-: TYPCAL AC AND DC CHARACTERSTC DAGRAMS Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc... Normalized Tpd..9 Normalized Tco..9 RSE Normalized Tsu Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp.3.3. Normalized Tpd...9. Normalized Tco...9. RSE Normalized Tsu Delta Tpd vs # of Outputs Switching Delta Tco vs # of Outputs Switching Delta Tpd (ns) RSE Delta Tco (ns) RSE Number of Outputs Switching Number of Outputs Switching Delta Tpd vs Output Loading Delta Tco vs Output Loading Delta Tpd (ns) RSE Delta Tco (ns) RSE Output Loading (pf) Output Loading (pf) 3-99 Data Book
21 Specifications GALV GAL VB-7/-: TYPCAL AC AND DC CHARACTERSTC DAGRAMS Vol vs ol Voh vs oh Voh vs oh Vol (V).5 Voh (V) 3 Voh (V) ol (ma) oh(ma) oh(ma) Normalized cc vs Vcc Normalized cc vs Temp Normalized cc vs Freq....3 Normalized cc...9 Normalized cc..9 Normalized cc Frequency (MHz) Delta cc vs Vin ( input) nput Clamp (Vik) Delta cc (ma) Vin (V) ik (ma) Vik (V) Data Book
22 Specifications GALV GAL VB-5/-5: TYPCAL AC AND DC CHARACTERSTC DAGRAMS Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc... Normalized Tpd..9 Normalized Tco..9 RSE Normalized Tsu Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp.3.3. Normalized Tpd...9. Normalized Tco...9. RSE Normalized Tsu Delta Tpd vs # of Outputs Switching Delta Tco vs # of Outputs Switching Delta Tpd (ns) RSE Delta Tco (ns) RSE Number of Outputs Switching Number of Outputs Switching Delta Tpd (ns) - Delta Tpd vs Output Loading RSE Output Loading (pf) Delta Tco (ns) - Delta Tco vs Output Loading RSE Output Loading (pf) 3-99 Data Book
23 Specifications GALV GAL VB-5/-5: TYPCAL AC AND DC CHARACTERSTC DAGRAMS Vol vs ol Voh vs oh Voh vs oh Vol (V) Voh (V) 3 Voh (V) ol (ma) oh(ma) oh(ma) Normalized cc vs Vcc Normalized cc vs Temp Normalized cc vs Freq.... Normalized cc...9 Normalized cc..9 Normalized cc Frequency (MHz) Delta cc vs Vin ( input) nput Clamp (Vik) Delta cc (ma) Vin (V) ik (ma) Vik (V) Data Book
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