Construction of a compact DAQ-system using DSP-based VME modules

Transcription

1 Abstract We have developed a DSP based data-acquisition syustem(daq) system, based on the DSP. The system utilizes VME boards with one or two s. Our intension was to consturct a compact DAQ framework which is adequate to a subdetector DAQ system in a detector complex for a large collider experiment. The system consists of five VME crates; one(control crate) is used for the local event builder as well as a run-controller, which is the master in the system, and others(fadc crate) for the readout from the several FADC modules. We install one board with one each in each FADC crate and two boards with two s each in the control crate. Data transfer between the control crate and each FADC crate is performed using the link with a transfer rate of about 0 MB/s, routed to the VME board front panel by the IO piggy pack module. In this paper, we report system design and development of the compact DAQ system using board and introduce an application example of this system to the BELLE SVD DAQ system. RT99 Santa-Fe, New-Mexico,USA June -,999

2 BELLE Detector measuement of e + (. GeV) e - ( GeV) collision to study CP violation in B-decay via reaction of Y(S) B0,B0 pair decays Life Time of B0 is about. ps Measurement of vertex positions is important e- e+ Silicon Vertex Detector(SVD) 90 si microstrips readout channels RT99 Santa-Fe, New-Mexico,USA June -,999

3 R=0mm Construction of a compact DAQ-system using DSP-based VME modules Mechanican Structure of BELLE Silicon Vertex Detector DSSD ladders Hybrid board VA chip Outer layer of the SVD Silicon detector Layer Layer Layer layer structure to form barrels around e+e- beam lines e- e+ R=0.mm R=.mm R=0.0mm d=.mm d=9.mm d=mm 0cm RT99 Santa-Fe, New-Mexico,USA June -,999

4 Local Control Crate Concept of BELLE SVD DAQ System VME connection Structure of the BELLE SVD DAQ CPU-V WS WS Preampilifier Chip(VA) (S&H, ch. mulx.single output) WS( board) with S WS with WS FADC Crates Link FADC Modules CDAQ FADCs(Halny) (Home made of Cracow Inst. of NP for SVD) CEBTX (CPU-V + CDAQ I/F) Detector Crate processors () Common operation in an FADC crate WS with SPARC CPU-V (UNIX) links BELLE Central DAQ (Global Mode) Each FADC crate connects to CDAQ independently Local Control Crate (Local Mode) Data of all four FADC crates are merged in the local crate WS with WS with RT99 Santa-Fe, New-Mexico,USA June -,999

5 Construction of a compact DAQ-system using DSP-based VME modules WS Board ( DSP VME cluster) ADSP0x ADSP0x IO-Pack IO-Pack ADSP0x IO-Pack ADSP0x IO-Pack ADSP0x x WS with s mounted installed in the Local Control Crate WS with mounted installed in each FADC crate as CORE processor RT99 Santa-Fe, New-Mexico,USA June -,999 Control Logic and Register Set FIFO up to K x VME Bus IO-Pack JTAG Connector Local Bus ADSP0x Bus ( bit data width ) IO-Pack Link Bus produced by Wiese GmbH, Germany. Up to six S can be mounted.. Each can work synchronously with bus or independently.. VME master/slave. VME DMA/BLK transfer. link with IO piggy pack(ws900). link = 0 MB/s(DMA & Sngl Word) WS with two s mounted amd one IO piggy pack on one of the Memory up to Mbyte Linkable expansion connectors for - 0 WS-Memory, DMA engines,... - VME P access - Customized Logic ALTERA MAX9000 CPLD ADSP0 for VME operation logic piggy pack WS900

6 Data & Control flow in the DAQ system Data flow in a Single FADC crate () WS Master to accumulate FADC data via VME BLK xfer. () CPU-V Master and WS Slave and CPU-V reads WS Memory, formats data and sends tocdaq via CEBTX(Global). () Timing of the Master switching is scanned by polling. (') WS setups link and send them via DMA mode(local) CEBTX (CPU-V + CDAQ I/F) CPU-V WS Local Control Crate WS WS FADC Crates Detector Link FADC Modules CDAQ Link buffers Force CPU-V Readout program SRAM On-board WS SRAM ( DSPs) DMA S-bus () ()... VME bus link Link buffers SRAM WS in FADC crate ( DSPs) On-board WS SRAM ( DSPs) Local control crate VME bus DMA FADC modules of FADC crate # FADC modules of FADC crate # Time... FADC modules of FADC crate # FADC modules of FADC crate # CEBRX CEBTX CPU-V board (Wiese WS) () (') Link FADCs Data Flow in the Local Control Crate in the local run mode RT99 Santa-Fe, New-Mexico,USA June -,999

7 Basic Performance Test VME transfer rates versus Data Transfer Length(Byte) WS VME capability Rate at KByte (MB/s) Overhead(us) Normal single word transfer. DMA single word transfer.. link Transfer(Nominal rate will be expected as 0 MB/s) Bandwidth(MB/s) Overhead(us) Normal transfer in core procs. Rate 9.9 Overhead DMA transfer Normal in Core Process 9.9. MB/s us.9 DMA Process. MB/s.9 us Speed (MB/s) 0 9 WS single word WS DMA single word CPU-V single word CPU-V DMA single word Length (byte) RT99 Santa-Fe, New-Mexico,USA June -,999

8 SYSTEM Test with Cosmic Ray We have made a special setup for the SVD to observe the cosmic rays after whole SVD barrel has been constructed but before we installed it to the BELLE. The main purpose of the test it to get rid off bugs hidden in the hardware/software of the readout system. The DAQ system are examined with the preformance and stability. For the sability test, we made a special program to check parity/checksums before the links. And no bit transfer failure has been observed in few days operation. Ethernet Special setup of SVD for Cosmic ray obervation test CPU-V CPU-V x FADC crates WS WS Halny FADC modules..... Halny FADC modules Link CPU-V WS Local Control Crate WS Control Signals Repeater System Repeater System Modules for timing control..... Cosmic ray Scintillation trigger counter Scintillation trigger counter DSSD Ladders SVD Cosmic-ray Event Display Numbers in the display means the pulse height in unit of 000 e- RT99 Santa-Fe, New-Mexico,USA June -,999

9 Summary We have constructed the DSP-based compact DAQ system. To minimize the processing time in the readout operation, we selected to use the WS(produced by Wiese GmbH, Germany) as a core processor module in the system. The VME performance of the WS was greater than that of a CPU-V(, which is almost identical as CPU-V as far as the VME processing ability is concerned). We could have fast enough VME transfer rate of. MB/s and. MB/s for single word and DMA singlw word, respectively. The link is an essential facility in the multi-mode DAQ system. We have observed the bandwidth of this link as 9.9 MB/s and. MB/s for single word and DMA transfer, respectively. In the system test with cosmic ray, we could observe and reconstruct cosmic ray tracks from hit position information. This means that we could collect whole data from each FADC crate synchronously. Through the system test for the SVD DAQ system, we can confirm that the DAQ system can give enough performance in the real DAQ system eventually if the SVD and its DAQ system are integrated in the BELLE frame work. RT99 Santa-Fe, New-Mexico,USA June -,999