Study, Implementation and Survey of Different VLSI Architectures for Multipliers

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1 Study, Implementation and Survey of Different VLSI Architectures for Multipliers Sonam Kandalgaonkar, Prof.K.R.Rasane Department of Electronics and Communication Engineering, VTU University KLE s College of Engineering and Technology, Belgaum , Karnataka, India sonamkandalgaonkar@yahoo.com kruparasane@hotmail.com Abstract Multiplication is the most useful operation required in many hardware computations. Efficient implementation of multipliers is required in many applications. This paper is a survey of different architectures for multipliers such as Array Multiplier using carry save concept, Wallace tree multiplier and Dadda multiplier. They were first implemented and tested on FPGA and later ported on to ASIC. Their performance were compared in terms of area, computational delay, gate count and power requirements using RTL complier in Cadence on 180nm, 90nm and 45 nm technologies. A floating point multiplier has been designed and simulated on Xilinx ISE tool. Keywords Array multiplier, Wallace multiplier, Dadda multiplier, Floating point multiplier, Verilog, RTL complier I. INTRODUCTION With the increased growth of multimedia and digital signal processing applications, the demand for designing high performance systems is becoming the main objective. The basic building block of arithmetic circuits in digital signal processing systems is adders, multipliers and registers. Among all these components multiplier is the most area, time and power consuming components. Multipliers are not only the basic building components but also bottleneck in terms of performance. The performance mainly depends on the execution of large number of multiplications [1]. Multiplication makes use of addition to produce a product P from a multiplicand X and a multiplier Y such that: P = X*Y Multiplication involves basically three separate steps as listed below Partial product generation (PP)-utilizes a collection of gates to generate partial product bits (a i b i ). Partial product reduction-utilizes an adder (counter) to generate sum and carry vectors. Final carry propagate addition-adds the sum and carries vectors to produce output [1]. For VLSI implementation, array multipliers and tree based multipliers are very well know and often used. For tree based multiplier such as Wallace and Dadda multiplier are focused on decreasing the depth of partial product processing. The speed of multiplication operation is increased by these two schemes [3]. The paper is organised as follows: In section II, array multiplier is briefly reviewed. The architecture, implementation is also discussed. Section III and section IV deals with study and implementation of Wallace multiplier and Dadda multiplier, section V deals with introduction to floating point multipliers. In section VI and section VII simulation and comparison results are presented and in section VIII, summary is concluded. II. ARRAY BASED MULTIPLIER An array multiplier is the simple architecture and most suitable for VLSI implementation, it also provides high degree of regularity. It s a multiplication method in which an array of identical cells generates new partial product and accumulation is done at same time [4] [1]. In multiplication, adders are utilized to reduce the execution time. However the main source of delay in adders is consumed through the carry. Therefore many designers have concentrated in reducing the total execution time that is involved in summing carry. Since multiplication not only involves two operands, but many of them it is very important to organise the hardware to mitigate the carry path or chain. Therefore many implementations consider adders according to two principles [1]. They are Carry Save Addition (CSA)-idea of utilizing addition without carries connected in series but just to count. Carry Propagate Addition (CPA)-idea of utilizing addition with carries connected in series to produce a result in either conventional or redundant notation. The implementation of symmetric array multiplier using two unsigned numbers a5a4a3a2a1a0 and b5b4b3b2b1b0 [1] is as shown in Fig1. Adders A0-F0 may be eliminated, which then eliminates A1-F1 leaving asymmetric CSA array of 30 adders [2]. An n-bit multiplier has a delay proportional to the n plus the delay of CPA (adders A6-F6) as shown in Fig 1[2]. There are two items to attack the performance of the multipliers: the number of partial products and the addition of partial products. IJCSIET-ISSUE2-VOLUME2-SERIES3 Page 1

2 Fig1: Symmetric array multiplier for 6X6 bit III.WALLACE TREE MULTIPLIER To reduce the delay of array multiplier, tree multipliers are often employed. Tree multipliers use the idea of reduction to reduce the partial products enough to use with Carry Propagate Adder (CPA) [1]. The main objective is to reduce the partial product using carry save concept. Each partial product is reorganised so that it can achieve an efficient reduction array. The Wallace tree has basically three steps: Multiply (i.e. AND) each bit of one of the argument by the other bit yielding n 2 results. Reduce the partial products to two by layers of full adders and half adders. Group the wires into two numbers and add them in a conventional adder. The second phase is as follows. As long as there are two or three wires with same weight it adds the following layer. Take any three wires of same weight and input them as a full adder, the result will be an output wire of same weight and an output wire with a higher weight for each three input wires. If there are two wires of same weight left, then input them into half adder. If there is one wire left, connect it to the next layer [3]. For Wallace tree multiplier we work forward from the multiplier inputs compressing the number of signals to be added at each stage [2]. Fig 2 shows the Wallace tree multiplier [2].Thus we can view Full Adder (FA) as 3:2 compressor or (3, 2) counter-its counts the number of 1 s on the inputs and Half Adder (HA) as (2, 2) counter. To add p5 in figure 4 we must add 6 summands (S05, S14, S23, S32, S41, S50) and 4 carries from p4 column. We add these in stages1-7,compressing from 6:3:2:2:3:1:1.notice that we wait until stage 5 to add the last carry from column p4 and this means we can expand the number of signals between stage 3 and 5.the maximum delay through the CSA array is 6 adder delay to this we must add the delay of 4-bit CPA. Fig2: Wallace tree multiplier for 6X6 bit IV.DADDA TREE MULTIPLIER Dadda multiplier is similar to Wallace tree but it is faster and smaller then Wallace tree multiplier. The dadda has same steps as Wallace. Dadda multiplier does as few reductions as possible. Because of this Dadda multiplier [7] has less expensive reduction phase, but the numbers may be few bits longer thus requiring slightly bigger adders. In Dadda multiplier we work from the final product for a 6bit multiplier. Fig 3 shows the implementation of Dadda multiplier [2], here we require 3 stages. Fig 3 shows Dadda multiplier, where carry save adder requires 20 adders (cells 1-20) and Ripple carry adder (RCA,cells 21-30).The overall speed implementation of this multiplier is same as Wallace multiplier and speed can be increased by using a fast CPA [2]. Fig 3: Dadda tree multiplier for 6X6 bit IJCSIET-ISSUE2-VOLUME2-SERIES3 Page 2

3 V.FLOATING POINT MULTIPLIER All the above mentioned multipliers are applicable for unsigned multipliers only. So floating point is taken into account to extend it for both signed and unsigned real numbers. In computing Floating point describes a method of representing real numbers in a way that can support a large number of values. The typical number that can be represented in the form: Significant digits X base exponent The term floating point can be refers to a fact that the radix point can be placed anywhere relative to the significant digits of the number. The floating point can consists of The digit string is referred as significand, coefficient and or less often the mantissa. The length of the significand determines the precision to which numbers can be represented. The radix point position is assumed to be somewhere within the significand of then just after or just before the most significant digits, or to the right of the rightmost. The exponent is also referred as the characteristic or scale which modifies the magnitude of the number. Fig5: Simulation result for 6X6 bit Wallace multiplier Fig6: Simulation result for 6X6 bit Dadda multiplier VI. XILINX SIMULATION RESULTS The design entry for array multipliers, Wallace tree multipliers, Dadda multiplier of 6bit by 6bit and floating point multiplier are modelled in verilog structural HDL are then simulated on Xilinx ISE 9.2i.The target FPGA is xc3s50a - 5tz144 with speed grade -5. The results for the simulation are shown in Fig 4, Fig5, Fig6, and Fig7 respectively. Fig7: Simulation result for Floating point multiplier VII.COMPARISON RESULTS Fig4: Simulation results for 6X6 bit array multiplier All the above multiplier are modelled using verilog HDL and then area, delay and power are calculated using RTL complier in Cadence for 180nm,90nm and 45nm technology libraries. Table 1 shows the comparison of array multiplier using carry save concept. From the table we can see that the gate count required for array is total of 78 cells with 36 FA and the CPA of 6bit.Table 2 shows the comparison of Wallace multiplier, from the table we see that it requires a total of 66 cells with 20 FA, 6FA and CPA -4 bit for the last stage. Table 3 shows the comparison of Dadda multiplier, here it requires a total of 66 cells with 16FA, 4HAand 10bit RCA for the last output stage. We observe the comparison is made in terms of area, power and delay for all three multipliers IJCSIET-ISSUE2-VOLUME2-SERIES3 Page 3

4 TECH LIB :45nm :90nm :180nm AREA(um2) POWER(nw) DELAY(ps) AREA (um2) POWER(nw) DELAY(ps) AREA(um2) POWER(nw) DELAY(ps) Cells CPA(6 BIT) Table1: Comparison for 6x6 bit array multiplier TECH LIB :45nm :90nm :180nm AREA(um2) POWER(nw) DELAY(ps) AREA(um2) POWER(nw) DELAY(ps) AREA(um2) POWER(nw) DEALY(ps) CELLS CPA-4BIT Table2: Comparison for 6x6 bit Wallace tree multiplier TECH LIB :45nm :90nm :180nm AREA(um2) POWER(nw) DELAY(ps) AREA(um2) POWER(nw) DELAY(ps) AREA(um2) POWER(nw) DELAY(ps) CELLS RCA- 10BIT Table3: Comparison for 6x6 bit Dadda tree multiplier VII. CONCLUSIONS The array multiplier is simple architecture, it provides minimum complexity and easily scalable. It also has regular structured layout and it is easy to route and place but the disadvantage is that there are more number of gates which results in large chip area and high power consumption.in Wallace tree multiplier it provides minimum propagation delay and Dadda multiplier reduces the core area and provides less power consumption. The overall speed of Dadda implementation is same as Wallace tree implementation. The Dadda multiplier is usually faster and smaller then Wallace tree and array multiplier [2]. From the observation of comparison table 3 above, we see that Dadda multiplier occupies less area, has less delay and less power consumption with respect to array multiplier and Wallace multiplier. For real numbers representation floating point multiplier has been designed and simulated using Xilinx ISE 9.2i. REFERENCES [1] James E.Stine, Digital Computer Arithmetic Datapath Design using Verilog HDL, 1 edition, Springer 2003, chapter no 4, page number (55-71) soft copy. [2] Michael John Sebastian Smith, Application Specific Integrated Circuits, Pearson Education-2003, chapter 2, section 2.3.4, page number ( ) soft copy. [3] Chris Y.H Lee, Lo Hai Hiung, Sean W.F.Lee, Nor Hisham, A Performance Comparison Study on Multiplier Designs, Department of IJCSIET-ISSUE2-VOLUME2-SERIES3 Page 4

5 Electrical and Electronic Engineering, Universiti Teknologi Petronas, Tronoh, Malaysia-June [4] Guoping Wang, The Efficient Implementation of an Array Multiplier, Indiana University Purdue University, Fort Wayne, May [5] Muhammad H.Rais, FPGA Design and Implementation of Fixed Width Standard and Truncated 6X6 Bit Multiplication: A Comparative Study [6] Prvinkumar Parate, Prafulla S.Patil and Dr (Mrs) S.subbaramn, ASIC Implementation of 4 Bit Multipliers, July 2008 [7] B. Ramkumar, V.Sreedeep, and Harish M.Kittur, A Design Technique for Faster Dadda Multiplier. IJCSIET-ISSUE2-VOLUME2-SERIES3 Page 5