DESIGN AND IMPLEMENTATION OF ADDER ARCHITECTURES AND ANALYSIS OF PERFORMANCE METRICS

Transcription

1 International Journal of Electronics and Communication Engineering and Technology (IJECET) Volume 8, Issue 5, September-October 2017, pp. 1 6, Article ID: IJECET_08_05_001 Available online at ISSN Print: and ISSN Online: IAEME Publication DESIGN AND IMPLEMENTATION OF ARCHITECTURES AND ANALYSIS OF PERFORMANCE METRICS Dr. G.S. Sunitha Professor & Head, Department of Electronics and Communication Engineering, Bapuji Institute of Engineering and Technology, Davanagere, India Rakesh H.M Assistant Professor, Department of Electronics and Communication Engineering, K.L.E Institute of Technology, Hubballi, India ABSTRACT s are one of the most widely used digital circuits in integrated circuit design. With the advances in technology, researchers are trying to design adders which offer either high speed, low power consumption, less area or the combination of them. In this paper the implementation of an ancient Vedic adder for 32bit size is proposed. The Vedic adder (VA) shows the improved speed performance with less time delay. The existing adders such as Ripple Carry (RCA), Carry Look Ahead (CLA), Carry Select (CSA) and Carry Skip (CKA) are implemented for 32 bit size. s are coded in Verilog HDL with XILNX software 14.3 on Spartan 3 kit using Chip Scope Pro analyzer. Further the performance metrics of adders such as area and delay are determined and compared. Keywords: Ripple Carry, Carry Look Ahead, Carry Select and Carry Skip, Vedic adder. Cite this Article: Dr. G.S. Sunitha, Rakesh H.M, Design and Implementation of Architectures and Analysis of Performance Metrics. International Journal of Electronics and Communication Engineering and Technology, 8(5), 2017, pp INTRODUCTION An adder is a digital circuit that performs addition of numbers. s have become a critical hardware unit for the efficient implementation of arithmetic unit. In many arithmetic applications adders are used not only in the arithmetic logic unit, but also in other parts of processor. Addition operation can also be used in complement operations, encoding and decoding. All complex adder architectures are constructed from its basic building blocks such as Half (HA) and Full (FA).Here an attempt has been made to design and simulate different types of adders such as Ripple Carry, Carry Look Ahead, 1 editor@iaeme.com

2 Design and Implementation of Architectures and Analysis of Performance Metrics Carry Select and Carry Skip using Verilog language and Xilinx ISE Further the performance metrics of adders such as area and delay are determined and compared. 2. RIPPLE A ripple carry adder is a logic circuit in which the carry-out of each full adder is the carry in of the succeeding next most significant full adder. In a ripple carry adder the sum and carry out bits of any half adder stage is not valid until the carry in of that stage occurs. The final result of the ripple carry adder is valid only after the joint propagations delays of all full adder circuits inside it. Multiple full adder circuits can be cascaded in parallel to add an N-bit number. For an N- bit parallel adder, there must be N number of full adder circuits.the advantage of ripple carry adder is simple logic and low cost. The disadvantage is it is slower and consumes more power. Propagation delay of ripple-carry parallel adders is proportional to the number of bits it handles. Maximum Delay is given by ((N-1) 2+3)t (1) where N is the number of bits and t is the time taken. Circuit diagram of a 4-bit ripple carry adder is shown in fig.1 below. A3 B3 A2 B2 A1 B1 A0 B0 V C3 C2 C1 C4 C0 S3 S2 S1 S0 Figure 1 4 Bit Ripple Carry. 3. LOOK AHEAD In ripple-carry adder, the limiting factor is the time it takes to propagate the carry. The carry look-ahead adder solves this problem by calculating the carry signals in advance, based on the input signals. The result is a reduced carry propagation time. The advantage is it is faster i.e speed due to computing carry bit i without waiting for carry bit (i-1).like ripple carry adder we need not wait for the propagation of carries to get the sum. The disadvantage is that the carry logic block gets very complicated for more than 4 bits. For that reason carry look-ahead adder are usually implemented as 4 bit modules and are used in a hierarchical structure to realize adders that have multiples of 4 bits. Circuit diagram of a 4-bit carry look ahead adder is shown in fig.2 below. The propagate P and generate G in a full-adder, is given as: P i = A i B i carry generate (2) G i = A i B i carry propagate (3) The expressions for the output sum and the carryout are given by S i = P i C i-1 (4) C i+1 = G i + P i C i (5) The group propagate (PG) and group generate (GG) for a 4bit Carry Look Ahead adder are 2 editor@iaeme.com

3 Dr. G.S. Sunitha, Rakesh H.M PG=P 0.P 1. P 2. P 3 (6) GG=G 3 +G 2.P 3 +G 1. P 3.P 2 +G 0.P 3. P 2.P 1 (7) Figure 2 4 Bit Carry Look Ahead. 4. SELECT Fig.3 shows the basic building block of a carry-select adder, where the block size is 4. Two 4- bit ripple carry adders are multiplexed together, where the resulting carry and sum bits are selected by the carry-in. Since one ripple carry adder assumes a carry-in of 0, and the other assumes a carry-in of 1, selecting which adder had the correct assumption via the actual carryin yields the desired result. Carry select adder is faster; being able to calculate all the input bits simultaneously. CSA is used in many data-processing processors to perform fast arithmetic functions. Figure 3 4 bit Carry Select 3 editor@iaeme.com

4 Design and Implementation of Architectures and Analysis of Performance Metrics 5. BYPASS A carry-bypass adder (also known as a carry-skip adder) is an adder that improves on the delay of ripple carry adder. The improvement of the worst-case delay is achieved by using several carry-skip adders to form a block-carry-skip adder. When all propagate-conditions are true(p=1) then the carry-in bit determines the carry-out bit and the carry bit for each block can now bypass over blocks with a group propagate signal(p) set to logic 1. Fig.4 shows the basic building block of a 4 bit carry-bypass adder. Figure 4 4 Bit Carry Bypass. 6. VEDIC The proposed Vedic adder shown in fig 5 uses two four bit ripple carry adders and an incremental adder. The Vedic adder is designed using the principles of Vedic mathematics. The incremental adder uses four half adders. The design shows improved performance in terms of delay. Figure 5 8 Bit Vedic. 4 editor@iaeme.com

5 Dr. G.S. Sunitha, Rakesh H.M 7. SYNTHESIS RESULTS s are coded in Verilog HDL with XILNX software 14.3 on Spartan 3 kit using Chip Scope Pro analyzer. The Synthesis of RCA, CLA, CSA, CKA and Vedic adder for 8 bit,16bit and 32 bit are carried out. The RTL schematic and synthesis result for Vedic adder are shown in fig 6 and fig 7. The synthesis results for 8bit,16bit and 32 bit Vedic adder in terms of LUTs, Slices and delay are shown in table 1 Table 1 Synthesis results Sl.No Size Design LUT s SLICES Delay(ns) 1 8bit Vedic adder bit Vedic adder bit Vedic adder Figure 6 RTL Schematic of 32 bit Vedic. Figure 7 Synthesis results of 32 bit Vedic. 5 editor@iaeme.com

6 Design and Implementation of Architectures and Analysis of Performance Metrics 8. COMPARISION RESULTS OF PROPOSED AND EXISTING S IN TERMS OF DELAY AND AREA The table2 and table3 shows trade off between delay, area and memory requirements for RCA, CLA, CSA, CKA for 32 bit size. The proposed Vedic adder shows improved performance in terms of delay when compared to existing adders like RCA, CLA, CSA, CKA. Table 2 Comparison Results Of Proposed And Existing s In Terms Of Delay And Area For 32 Bit Size Sl.No Size Design LUT s SLICES Delay(ns) 1 32bit Ripple Carry bit Carry Look Ahead 3 32bit Carry Select bit Carry Bypass bit Vedic adder Table 3 comparison results of proposed and existing adders in terms of memory requirements for 32 bit size. SL.NO SIZES Memory requirements(mb) RIPPLE LOOK AHEAD SELECT BYPASS VEDIC 1 32X CONCLUSIONS From implementation, simulation & comparative results, it is concluded that the delay parameter for Vedic adder is lesser when compared to RCA, CLA, CSA and CKA for 32bit lengths. Therefore it has been observed that Vedic adder is providing better results than conventional adders. 10. FUTURE SCOPE The work can be further extended by designing adders of higher bit lengths for arithmetic and logic unit of a computer. REFERENCES [1] Maroju SaiKumar, Dr.P. Samundiswary, Design and Performance Analysis of Various s using Verilog, International Journal of Computer Science and Mobile Computing, vol.2, pp ,september [2] SangeetaRani, Sachin Kumar, Simulation of Different bit Carry-Skip in Verilog, International Journal of Science and Research,vol3,June 2014 [3] Navjeet Singh and Ankesh N. Bhoi, Hybrid CMOS Logic To Implement High Speed and Low Power 4-Bit CLA, International Journal of Electronics and Communication Engineering and Technology, 7(5), 2016, pp [4] Mohammad Mahad and Manisha Waje, Implementation of Ripple Carry Using Advanced Multilayer Three Input XOR Gate (TIEO) Technique in QCA Technology. International Journal of Electronics and Communication Engineering and Technology, 8 (4), 2017, pp editor@iaeme.com