International Journal of Computer Trends and Technology (IJCTT) volume 17 Number 5 Nov 2014 LowPower32-Bit DADDA Multipleir

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1 LowPower32-Bit DADDA Multipleir K.N.V.S.Vijaya Lakshmi 1, D.R.Sandeep 2 1 PG Scholar& ECE Department&JNTU Kakinada University Sri Vasavi Engineering College, Tadepalligudem, Andhra Pradesh, India 2 AssosciateProfessor& ECE Department&JNTU Kakinada University Sri Vasavi Engineering College, Tadepalligudem, Andhra Pradesh, India Abstract Now a days, Low power applications play a crucial task in designing of VLSI based digital circuits. They demand to investigate different techniques to reduce power consumption in digital circuits while maintains computational throughput.low power VLSI design is asignificant research area for past decades since the increasing demands on portable devices. Many methods are implemented to reduce thepower dissipation.in a, most contribution of power consumption is due to generation and reduction of partial products.among s, DADDA shows enhanced performance in terms of power, area and delay than other s. DADDAimplementation can minimizes the number of adder stages required to perform the summation of partial products. Hence, in this paper, a new power aware VLSI design for 32 bit DADDA isimplemented in a schematic editor using tanner tool and its performance is compared with standard Keywords Low Power; DADDA ; VLSI I. INTRODUCTION Multiplications are expensive and slow operations. The performance of many computational problems often is dominating by the speed at which a multiplication operation can be executed; s are, in effect, complex adder arrays. The analysis of the gives us some further insight into how to optimize the performance of complex circuit topologies In Many digital systems s are the fundamental components and hence their power dissipation and speed are of primary concern.techniques for low power operation, which use the lowest possible supply voltage coupled with architectural, logic style, and circuit and technology optimizations. An architectural based scaling strategy is presented which indicates that the optimum voltage is much lower that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption. A. Multiplier: Definition A variety of computer arithmetic techniques can be used to implement a digital. Most techniques involve computing a set of partial products, and then summing the partial products together. Basically a binary is an electronic circuit used in digital electronics, such as a computer, to multiply two binary numbers. It is built using binary adders. Consider two unsigned numbers X and Y that are M and N bits wide, respectively. To introduce the multiplication operation, it is useful to express X and Y in the binary representation as X = Xi.2 i,y = Yj. 2 j with X i and Y j {0, 1}. The multiplication is then defined as follows: Z = X Y = Zk. 2 k = ( Xi. 2 i ). ( Yj. 2 j ) = ( Xi.Y j.2 i+j ) The simplest way to perform a multiplication is to use a single two-input adder. For inputs that are M and N bits wide, the multiplication takes M cycles, using an N-bit adder. This shift- and-add algorithm for multiplication adds together M partial products. Each partial product is generated by multiplying the multiplicand with a bit of the, which, essentially, is an AND operation, and by shifting the result on the basis of the bit s position. All the partial products are generated at the same time and organized in an array. A multi operand addition is applied to compute the final product. This approach is illustrated in Fig 1. Fig. 1 Binary Multiplication The resulting structure is called an array and combines the following three functions:partial-product generation, partial-product accumulation, andfinal addition. B. Partial product generation Partial products results from the logical AND of the multiplicand X with a bit Yi. Each row in the partial product array is either a copy of the multiplicand or a row of zeros. Careful optimization of the partial product generation can lead to some substantial delay and area reductions. In the case of a consisting of all ones, all the partial products are exists, while in the case of all zeros, there is none. These partial products are accumulated by using number of adders that will form an array, hence, the name array. An N x N array comprises N(N-2) full ISSN: Page 237

2 adders and N half adders in its implementations; the 2N bit Here, include an extra adder called a vector-merging product is available after a maximum of (N-1) sum delays and adder to generate the final result. The resulting is (N-1) carry delays. called a carry-save, because the carry bits are not immediately added, but rather are "saved" for the next adder stage. In the final stage, carries and sums are merged in a fast carry-propagate (e.g., carry-look ahead) adder stage. While this structure has a slightly increased area cost (one extra adder), it has the advantage that its worst case critical path is shorter and uniquely defined, as highlighted in Fig 4 and is expressed as Fig. 2 Partial Product Generation t mult =t and + (N-1)t carry +t merge still assuming that t add = t carry C. Partial product generation Array Multiplier The Simplest multiplication scheme is an array and a simple 8-bit array is shown in Fig 3. Fig. 3 8 Bit Array Multiplier For this array implementation, determination of propagation delay is not straightforward. Performance optimization requires that the critical timing path be identified first. This turns out to be nontrivial. In general, the propagation delay of an array can be expressed as t mult = [(M-1) +(N-2)]t carry + (N-1)t sum + t and, where t carry is the propagation delay between input and output carry, t sum is the delay between the input carry and sum bit of the full adder, and t and is the delay of the AND gate. Tree The partial-sum adders can also be rearranged in a treelike fashion, reducing both the critical path and the number of adder cells needed. Consider a simple example of four partial products, each of which is four bits wide, as shown in Fig 5(a). The number of full adders needed is reduced by observing that only column 3 in the array has to add four bits. All other columns are somewhat less complex and are illustrated in Fig 5(b), where the original matrix of partial products is reorganized into a tree shape to visually illustrate its varying depth. The challenge is to realize the complete matrix with a minimum depth and a minimum number of adder elements. Here, two types of operators namely 3-2 compressor (Full Adder) and 2-2 compressor (Half Adder) are used. Full adder is denoted by a circle covering three bits, whereas Half Adder is denoted by a circle covering two bits. Carry - save A more efficient realization can be obtained by noticing that the multiplication result does not change when the output carry bits are passed diagonally downwards instead of only to the right, as shown in Fig 4. Fig. 5 Wallace Tree Multiplier The tree realizes substantial hardware savings for larger s and the propagation delay is reduced as well. In fact, it can be shown that the propagation delay through the tree is equal to O (log3 / 2(A0)) - While substantially faster than the carry-save structure for large word lengths, the Wallace has the disadvantage of being very irregular, which complicates the task of coming up with an efficient layout.there is numerous other ways to accumulate the partial-product tree. A number of compression circuits have been proposed in the literature. Fig. 4 Carry Save Multiplier ISSN: Page 238

3 II. DADDA MULTIPLIER that there are only two outputs for any weight. Then, the In array multiplication scheme, the summation proceeds in second rule is above changes as follows a more regular, but slower manner, to obtain the summation of If there are 2 wires of the same weight left, and the the partial products. Using this scheme, only one row of bits in current number of output wires with that weight is equal the matrix is eliminated at stage of the to 1 or 2 (modulo 3), input them into a half adder. summation.daddaimplementation essentially reduces the Otherwise, pass them through to the next layer. number of adder stages needed to perform the summation of partial products. It can be achieved by using full and half adders to reduce the number of rows in the matrix number of bits at each summation stage. In this Dadda, the partial product matrix is formed in the first stage by N 2 AND stages and the partial product matrix is reduced to a height of two at final. In Dadda that reduce the number of rows as much as possible on each layer, this do as few reductions as possible. Because of this advantage, Dadda s have less expensive reduction phase. A. Proposed Work The Dadda is a hardware design, invented by computer scientist Luigi Dadda in It is slightly faster (for all operand sizes) and requires fewer gates (for all but the smallest operand sizes) than Proposed Dadda has 3 steps: 1. Perform Multiplication operation and get partial product matrix. 2. Reduce the number of partial products to two layers of full and half adders. 3. Group them in totwo numbers, and add them with a conventional adder. Dadda s can accomplish few reductions only over Wallace tree. Hence, Dadda s have less expensive reduction phase, but the numbers may be a few bits longer, hence requiresa few bigger adders. To achieve this, the structure of the second step is governed by slightly more complex rules than in the wallace s. The reduction rules are as follows: Take any 3 wires with the same weights and input them into a full adder. The result will be an output wire of the same weight and an output wire with a higher weight for each 3 input wires. If there are 2 wires of the same weight left, and the current number of output wires with that weight is equal to 2 (modulo 3), input them into a half adder. Otherwise, pass them through to the next layer. If there is just 1 wire left, connect it to the next layer. This step does only as many adds as necessary, so that the number of output weights stays close to a multiple of 3, which is the ideal number of weights when using full adders as (3, 2) counters. However, when a layer carries at most 3 input wires for any weight, that layer will be the last one. In this case, the Dadda tree will use half adder more aggressively to ensure B. Implementation The multiplication of an M-bit multiplicand by an N-bit yields an N by M matrix of partial products. The reduction of this partial product matrix through the parallel application of (3, 2) and (2, 2) counters results in a matrix with a height of two. Each (3, 2) counter (full adder) accepts three inputs from a given column and produces a sum bit which remains in that column and a carry bit which goes into the next more significant column. A (2, 2) counter (half adder) accepts two inputs from a column and produces a sum bit in the same column and a carry bit in the next more significant column. The implemented Dadda with the help of dot diagram is shown in Fig 3. (The notation is taken from in which the outputs from a full adder are joined by a solid line, and those from half adders are joined by a line with a dash through the center). ISSN: Page 239

4 C. Flow Chart START Input Data (Multiplicand & Multiplier) Partial Product Array (AND gates) Obtain 1 st reduction stage of 28-rows Obtain 2 nd reduction stage of 19-rows Obtain 3 rd reduction stage of 13-rows Obtain 4 th reduction stage of 9-rows Obtain 5 th reduction stage of 6-rows Obtain 6 th reduction stage of 4-rows Obtain 7 th reduction stage of 3-rows Fig. 6 Dot Diagram of Proposed Multiplier Obtain 8 th reduction stage of 2-rows The Dadda scheme minimizes the number of adder stages required to perform the summation of the partial products. This is achieved by using full and half adders to reduce the number of rows in the matrix of bits at each summation stage by a factor of 3/2. This results in a final matrix consisting of two rows of bits which must be summed using a multiple-bit adder (e.g. a ripple-carry or carry look-ahead adder). By way of contrast, in a popular multiplication scheme the array, the summation proceeds in a more regular, but slower manner, to obtaining the summation of the partial products.using this scheme only one row of bits in the matrix is eliminated at each stage of the summation. The process of Dadda multiplication is as follows:the entire 32 x 32 multiplication requires eight stages. Always the first stage is partial product stage, which is obtained by simple multiplication of multiplicand with. The proposed 32-bit requires eight reduction stages with intermediate matrix heights of 28, 19, 13, 9, 6, 4, 3 and finally2. In Dadda implementation, in general, the numberof full adders required is N 2-4N+3 and the number of half adders is always N-1. Final Addition Final Product Fig. 7 Flowchart of Implementation of Dadda Multiplier The number of reduction stages required to implement Dadda architecture for various number of bits is given in following table. TABLE I. NUMBER OF STAGES IN DADDA MULTIPLIER Number of Bits in Multiplier(N) Stages N N N N N N N N III. SCHMATIC EDITOR For this projectwe used TANNER software tools(t-spice) because this software designed to solve a wide variety of circuit problems. ISSN: Page 240

5 Inverter: Half Adder: Fig. 8 Schematic View of Inverter Fig8 shows the schematic implementation of the inverter. AND gate: Fig. 11 Schematic View of Half Adder Fig11 shows the schematic implementation of the Half Adder. Full Adder: Fig. 9 Schematic View of AND gate Fig9 shows the schematic implementation of the AND gate. OR gate: Fig. 12 Schematic View of Full Adder Fig12 shows the schematic implementation of the Full Adder. 8 x 8 Array : Fig. 10 Schematic View of OR gate Fig10 shows the schematic implementation of the OR gate. Fig. 13 Schematic View of 8 8 Array ISSN: Page 241

6 Fig13 shows the schematic implementation of the 8 8 Fig16 shows output waveforms correspond to the x 8 Array waveforms: 32 x 32 Array : Fig. 14 Waveforms of 8 8 Array Fig14 shows the output waveforms correspond to the x 16 Array : Fig. 17 Schematic View of Array Fig17 shows the schematic implementation of the x 32 Array waveforms: Fig. 15 Schematic View of Array Fig15 shows the schematic implementation of the x 16 Array waveforms: Fig. 18Waveforms of Array Fig18 shows the output waveforms correspond to the x 8 Dadda : Fig. 16Waveforms of Array Fig. 19 Schematic View of 8 8 Dadda ISSN: Page 242

7 Fig19 shows the schematic implementation of the 8 8 dadda. 8 x 8 Dadda waveforms: Fig. 20Waveforms of 8 8 Dadda Fig20 shows the output waveforms correspond to the 8 8 dadda. 16 x16 Dadda : Fig. 23 Schematic View of Dadda Fig23 shows the schematic implementation of the Dadda. 32 x 32 Dadda mutiplier waveforms: Fig. 24Waveforms of Dadda Fig24 shows the output waveforms correspond to the dadda. Fig. 21 Schematic View of Dadda Fig21 shows the schematic implementation of the dadda. 16 x 16 Dadda waveforms: IV. RESULTS A. Comparison between 8 x 8 Array and Dadda s TABLE II. COMPARISON BETWEEN 8 X 8 ARRAY AND DADDA MULTIPLIERS Parameter 8x 8 Array 8 x 8 dadda Power 2.33 x 10-3 watts 1.83 x 10-3 watts Hardware requirement Adders-56 (Full Adders-48 Half Adders-8) Adders-42 (Full Adders-35 Half Adders-7) Time(delay) seconds 33.61seconds Fig. 22Waveforms of Dadda Fig22 shows the output waveforms correspond to the 16 x 16 dadda. 32 x 32 Dadda : ISSN: Page 243

8 From the TABLE II the power consumed by 8 8 array is watts, where as in 8 8 Dadda is From thetable IV, power consumed in array watts. Hence 78.5% of power can be is 5.8 Watts, where as in the Dadda saved by Dadda architecture. Implementation of conventional 8 8 bit array requires 56adders (48 full adders and 8 half adders), where as the proposed 8 8 Dadda can be implemented by 42 adders (35 full adders and 7 half adders). Hence the Dadda architecture reduces 14 adders over array, and then it reduces the total switching activity. The time (delay) taken to complete the 8 8 multiplication operation using conventional array is seconds, where as in 8 8 Dadda, the time consumed is seconds. The Dadda architecture saves 32.11% of time than that of conventional B. Comparison between 16x 16 Array and Dadda s TABLE III. COMPARISON BETWEEN 16 X 16 ARRAY AND DADDA MULTIPLIER Parameter 16x 16 Array 16 x 16 dadda Power 3.76 x 10-3 watts 3.16 x 10-3 watts Hardware requirement Adders-240 (Full Adders-224 Half Adders-16) Adders-210 (Full Adders-195 Half Adders-15) Time(delay) seconds seconds From thetable III, power consumed in array is Watts, where as in the Dadda architecture is Watts. Hence 84% of power can be saved by Dadda architecture. Implementation of conventional bit array requires 240adders (224 full adders and 16 half adders), whereas the Dadda can be implemented by 210 adders (195 full adders and 15 half adders). Hence the Dadda architecture reduces 30 adders over array, and then it reduces the total switching activity. The time (delay) taken to complete the multiplication operation using conventional array is seconds, where as in Dadda, the time consumed is seconds. The Dadda architecture saves 61.18% of time than that of conventional C. Comparison between 32x 32 Array and Dadda s TABLE IV. Parameter Power Hardware requirement COMPARISON BETWEEN 32 X 32 ARRAY AND DADDA MULTIPIERS 32x 32 Array 5.8watts (5.8009e+000 watts) Adders-992 (Full Adders-960 Half Adders-32) 32 x 32 dadda 2.49watts ( e+000 watts) Adders-930 (Full Adders-899 Half Adders-31) Time(delay) seconds seconds architecture is 2.49 Watts. Hence59% of power can be saved by Dadda architecture. Implementation of conventional bit array requires 992adders (960 full adders and 32 half adders), whereas the Dadda can be implemented by 930 adders (899 full adders and 31 half adders). Hence the Dadda architecture reduces 62 adders over array, and then it reduces the total switching activity. The time (delay) taken to complete the multiplication operation using conventional array is seconds, where as in 32 32Dadda, the time consumed is seconds. The Dadda architecture saves 54.8% of time than that of conventional V. CONCLUSION & FUTURE SCOPE In this project, a proposed Dadda multiplication scheme is implemented for a 32 x 32 bit multiplication. With respect to the parameters power consumption, area estimate and hardware requirement, this Dadda multiplication technique is better than the conventional array multiplication schemes. From the results obtained by the Dadda multiplication scheme, this approach is further extended to perform themultiplication of higher bit 64-bit. The power consumption and area estimate are further reduced by implementing the final adder with look ahead carry generation logic (look ahead carry adder) REFERENCES [1] HENLIN, D.A., FERTSCH, M.T., MAZIN, M., and LEWIS, E.T.: A bit pipelined macrocell, IEEE, J. Solid-State Circuits, 1985, SC-20, pp [2] HATAMIAN, M., and CASH G L: A 70-MHz 8-bit 8-bit parallel pipelined in 2.5-µm CMOS IEEE J Solid-state circuits, 1986, SC-21, pp [3] SCHMITT-LANDSIEDEL, D., NOLL, T.G., KLAR, H., and ENDERS, G.: A pipelined 330 MHz. ESSCIRC 85, 11thEuropean Solid State Circuits Conf September [4] LEE, F S., KAELIN, G R., WELCH, B M., ZUCCA, R., SHEN, E., ASBECK, P., LEE, C.P., KIRKPATRICK, C. G., LONG, S.I., and EDEN R. C.: A High-Speed LSI GaAs 8 8 bit parallel, IEEE J. Solid state Circuits, 1982, SC 17, pp [5] YUNG, H.C., and ALLEN, C.R.: Part 1: VLSI implementation of an optimized hierarchical, IEE Proc. G, Electron. Circuits & Syst., 1984,131, (2), pp [6] DADDA, L.: Some Schemes for Parallel Multipliers, Alta Freq., 34, 1965, pp [7] L. DADDA, On Parallel Digital Multipliers, Alta Frequenza, vol. 45, pp , 1976 ISSN: Page 244