Camellia Getting Started with ARM922T

Transcription

1 A Hand-Out 1 Getting Started with ARM922T Las Palmas de G. C., Canary Islands Jul, 15 th, 2002 Reny / IUMA-ULPGC ARM922T Overview 2 Harvard Architecture (Data and instruction are located in different memories). Risc architecture: Load/Store. Simple Addressing modes. Op codes of fixed length to improve decode stage. Two different instruction sets: ARM instruction set (32 bits operation codes) Thumb instruction set (16 bits operation codes) Full access to Memory and Cache configuration.

2 A Hand-Out ARM922T Overview 3 2 ARM architecture has multiple variants. The main are: T variants: include the Thumb instruction set M variants: include instruction in order to obtain long results (64- bits long) from multiply 32-bits operands. E variants: include specific instruction for DSP purposes. ARM922T uses a T variant core. ARM922T Block Diagram 4

3 A Hand-Out ARM922T CP15 Coprocessor 5 3 These coprocessor controls some of the most importants features of ARM922T: Device identification and descripcion for the OS. TTB base addresses, lockdown and next victim. Domain access. MMU enable/disable. Little/Big Endian. Location of the exception vectors. ARM922T CP15 Coprocessor 6 Register the source of the last Data Abort and the MVA that generated it. Cache operations (Invalidate data, line fetch, line lockdown...) and cache enable/disable. Cache replacement: Round Robin Pseudo-random Fast Context Switch Extension Process Identifier (FCSE PID).

4 A Hand-Out ARM922T CP15 Coprocessor 7 4 Fast Context Switch Extension Process Identifier (FCSE PID). The Register 13 on the CP15 is R13 seen on block diagram Register 13 is used to change the addresses seen by MMUs and caches. This is useful to swap memory regions for different process without changing TLBs or caches. This make possible that different process have the same range of addresses even when no VA-PA translation is provided. ARM922T CP15 Coprocessor 8 The actions on this coprocessor are taken writing the suitable register. To load or write in the CP15 registres, the ARM9TDMI core uses the coprocessor instructions MRC and MCR respectively. (We will take a look to coprocessor instruction when we introduce the ARM9TDMI core). The CP15 registers are accesible only for privileged modes.

5 A Hand-Out ARM922T CP15 Coprocessor The visible registers in CP15 and their function are: 9 5 Register 1: controls system operation parameters including endianness, cache and MMU enable. Registers 2 and 3: configure and control MMU functions. Registers 5 and 6: provide MMU status information. Registers 7 and 9: used for cache maintenance operations. Register 8 and 10: used for MMU maintenance operations. Register 13: used for fast context switching (this one contents the FCSE PID). Register 15: used for test purposes. ARM922T CP14 Coprocessor 10 This coprocessor controls the debug communications channel. The debug communications channel makes possible the exchange of information between the core and an external debugger host. The communications channel consist on: 32-bits wide data read register. 32-bits wide data write register. 6-bits wide control register for handshaking between host and EmbeddedICE macrocell.

6 A Hand-Out ARM922T MMU 11 6 ARM922T has two MMUs (one for data and another for instruction) as a result of its Harvard architecture. There are three different kinds of addresses: Virtual Address (VA). Modified Virtual Address (MVA). Physical Address. MMU can be disabled through the CP15 coprocessor: If MMU is disabled Flat address mapping without check. ARM922T MMU 12 Cached MMU Memory System diagram Access Control Hardware Access bits, domains TLB Translation Table Walk Hardware ARM VA Cache and Write Buffer C,B bits Cache Line Fetch Hardware Main Memory MMU allows to set a region of memory as cacheable or buffered. PA

7 A Hand-Out ARM922T MMU ARM922T MMU supports memory access based on: Sections (1 Mb) Pages: Large Pages (64Kb) Small Pages (4Kb) Tiny Pages (1Kb) 13 7 The translation table has two levels: The first to address a section or point to the second level. The second to point to the different kind of pages. Whole TLB or its entries can be locked or invalidated by writing CP15 registers. ARM922T MMU Translating Pages Tables Structure: 14

8 A Hand-Out ARM922T MMU Domains The basic access control is made based on domains: A domain is a collection of sections, large pages and small pages There are 16 domains. Each domain has a two-bits field on domain access control register. Two kinds of domain access: Client Manager. Domains are referenced on the translation tables. ARM922T MMU-Access Permissions 16 MMU provides access permissions for sections. Permissions for pages can be achieved separately for each quarter of page (subpage) but tiny pages. The translation tables has the information related to permissions. This information has a different meaning when the processor is in privileged than in user mode. If a program is the manager of the domain to which section or page belongs, the permission are not checked.

9 A Hand-Out ARM922T Cache 17 9 Two different caches: one for instruction and one for data. 8K cache size. 8 word cache line size. Write-back or write-through can be choosen for each memory region. This information is kept in MMU tables. Round Robin or pseudo-random replacement strategy (CP15). The replacement is done on-read-miss. ARM922T Cache 18 CP15 Register 9 makes possible to change the pointer to the next victim and locks in the cache the lines before the pointer: It is required to locate lines to be locked in this way in the lowest part of the cache, so the pointer is fixed to an upper position. Locked Locked Next Victim Next Victim Next Victim Register 9 pointer PA TAG RAM prevents TBL faults in write-back operations.

10 A Hand-Out ARM922T Cache The caches are disabled after a reset. If MMU disabled: ICache: Consider all memory regions as cacheable. Permission are not considered. DCache: DON T ENABLE THE CACHE. The write-buffer and cache gets their configuration from MMU tables. ARM922T Cache Cache organization. 20

11 A Hand-Out ARM922T Cache DCache has 2 dirty bits per line to notify the needing of write-back. Write-back and write-through are possible for Dcache. The policy choosen is marked for each memory region on MMU tables: C B Write-through cache Write-back only cache Write-back/write-through cache 0 0 Uncached/unbuffered Uncached/unbuffered Uncached/unbuffered 0 1 Uncached/buffered Uncached/unbuffered Uncached/buffered 1 0 Cached/unbuffered UNPREDICTABLE Write-through Uncached/unbuffered 1 1 Cached/buffered Cached/buffered Write-back cached/buffered ARM922T Cache Coherency 22 Coherence between memory and both caches are carried by software. BE CAREFUL! DCache can be forced to write-back result of dirty data using clean operations (CP15). When using self-modifying code, be careful on what you have in ICache. Maybe you will have to invalidate ICache to force the refetch. Other devices can change memory, so make the memory regions used by them uncacheable and unbuffered.

12 A Hand-Out ARM922T AMBA AMBA is the Advanced Microcontroller Bus Architecture. Two distinct buses defined by AMBA specification: ASB or AHB APB ARM922T AMBA COMPONENTS 24 ASB: ASB Master ASB Slave ASB Decoder ASB Arbiter APB: APB Bridge APB Slave

13 A Hand-Out ARM922T AMBA - ASB Arbiter function: ARBITER You re the choosen one I wan t to make a transference MASTER 1 Transference SLAVE 1 SLAVE 2 I wan t to make a transference MASTER 2 SLAVE 3 MASTER 3 ARM922T AMBA - ASB 26 Three types of transfer: Non-sequential. Sequential. Address-only: No data transfer. Used for idle and bus master handover cycles. Slave responses: Done. Wait. Error. Retract. Last.

14 A Hand-Out ARM922T AMBA - ASB Non-sequential and secuential transfer: ARM922T AMBA - APB 28 Write transfer: Read Transfer:

15 A Hand-Out ARM922T AMBA - AHB AHB is the new generation of AMBA with opcional width extension. Is above APH (as ASB did). AHB has a central multiplexor: ARM922T AMBA - AHB 30 There are four transfer types: IDLE BUSY SEQUENTIAL NON-SEQUENTIAL

16 A Hand-Out ARM922T AMBA - AHB Transfer example: ARM922T AMBA - AHB 32 The Slave must respond with on of the following: OKAY ERROR RETRY SPLIT The difference between retry and split is that split makes the arbiter to select a new bus master.

17 A Hand-Out ARM922T AMBA - AHB Retry example: ARM922T AMBA - AHB 34 SPLIT EXAMPLE: Suppose burst transfer has been done between Master1 and Slave1: I ve come I have I ll back. the come bus control back! Arbiter I can Sorry, resume I can t transfer. go on transfer Now I got the control. Master1 Transfer Split response Slave1 I ve finished. Master2 Transfer Transfer Slave2

18 A Hand-Out ARM9TDMI Core Data types: Word (32 bits) Halfword (16bits) Byte Processor modes: Processor mode User FIQ IRQ Supervisor Abort Undefined System Description Normal program execution mode Supports a high speed data transfer or channel process Used for general-purpose interrupt handling A protected mode for the operating system Implements virtual memory and/or memory protection Supports software emulation of hardware coprocessors Run privileged operating system tasks ARM9TDMI Registers. There are 31 general purpose registers and 6 status register: User System Supervisor Abort Undefined Interrupt Fast Interrupt R0 R0 R0 R0 R0 R0 R0 R1 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R2 R3 R3 R3 R3 R3 R3 R3 R4 R4 R4 R4 R4 R4 R4 R5 R5 R5 R5 R5 R5 R5 R6 R6 R6 R6 R6 R6 R6 R7 R7 R7 R7 R7 R7 R7 R8 R8 R8 R8 R8 R8 R8_fiq R9 R9 R9 R9 R9 R9 R9_fiq R10 R10 R10 R10 R10 R10 R10_fiq R11 R11 R11 R11 R11 R11 R11_fiq R12 R12 R12 R12 R12 R12 R12_fiq R13 R13 R13_svc R13_abt R13_und R13_irq R13_fiq R14 R14 R14_svc R14_abt R14_und R14_irq R14_fiq PC PC PC PC PC PC PC 36 CPSR CPSR CPSR CPSR CPSR CPSR CPSR SPSR_svc SPSR_abt SPSR_und SPSR_irq SPSR_fiq

19 A Hand-Out ARM9TDMI Status Registers The CPSR and SPSR have the next format: 31 N 30 Z 29 C 28 V 27 Q 26 8 USO FUTURO 7 I 6 F 5 T 4 M(4) 3 M(3) 2 M(2) 1 M(1) 0 M(0) ARM9TDMI Exceptions 38 Exception type Reset Undefined instructions Software interrupt (SWI) Prefetch Abort Data Abort IRQ FIQ Mode Supervisor Undefined Supervisor Abort Abort IRQ FIQ Normal Address C C High Vector Address FFFF0000 FFFF0004 FFFF0008 FFFF000C FFFF0010 FFFF0018 FFFF001C

20 A Hand-Out ARM9TDMI Exceptions The exceptions priorities are: Priority Highest Lowest 6 Exception Reset Data Abort FIQ IRQ Prefetch Abort Undefined Instruction (SWI) ARM9TDMI Exceptions 40 Actions after an exception occurs: R14=return link (this address is different for each exception!!!) SPSR=CPSR CPSR[4:0]=exception mode number ARM mode Disable IRQ If Reset or FIQ the disable FIQ PC=exception vector address

21 A Hand-Out ARM9TDMI ARM Instruction Set Conditional execution of instructions: C Code int gcd(int a, int b) { while (a!=b) if (a>b) a= a-b; else b=b-a; return a; Assembly code gcd CMP R0,R1 ;compare a and b SUBGT R0, R0, R1 ;if (a>b) a=a-b SUBLT R1, R1, R0 ;if (b<a) b=b-a BNE gcd ;if (a!=b) then keep looping MOV PC,LR ;return to caller } ARM9TDMI ARM Instruction Set 42 Load/Store Addressing modes: The address is formed from: Base register Offset: Immediate Register Scaled Register: LDR R1, [R2, R3, LSL #3] The addressing modes are: Offset: LDRSB R1, [R0,#4] Pre-indexed: LDRH R1, [R0,#4]! Post-indexed: LDR R1, [R0], #4

22 A Hand-Out ARM9TDMI ARM Instruction Set Multiple Load/Store: Useful for moving memory blocks Four Addressing modes: Increment After Increment Before Decrement After Decrement Before The S bit =1 means: LDMs that load the PC: SPSR has to be restored. Other LDMs and all STMs: for privileged modes and banked register use the user mode register. ARM9TDMI ARM Instruction Set 44 In arithmetic and logic instructions S bit means: S=0: CPSR unchanged. S=1: If the destination is PC: CPSR replaced by SPSR. If the destination is not PC: CPSR updated. CMP, CMN, TST, TEQ has S bit fixed to 1. Semaphore instructions: SWP SWPB

23 A Hand-Out ARM9TDMI ARM Instruction Set Coprocessor instructions: The coprocessor instructions are: LDC: Load to Coprocessor. STC: Store from Coprocessor. MCR: Move to Coprocessor. MRC: Move from Coprocessor. CDP: Coprocessor Data Processing. The instruction has to indicate which coprocessor has to execute the instruction. If no coprocessor responds an undefined instruction exception is raised. ARM9TDMI ARM Instruction Set 46 Branch instructions: B: Branch. BL: Subroutine call: BX: Branch and change code type: Address LSB = 0: ARM code is coming. Address LSB = 1: Entering Thumb State.

24 A Hand-Out ARM9TDMI Thumb Instruction Set 16 bits op codes Shorter op codes, so shorter range for branch and inmediate data. More code density. Just few instructions can access High Registers (R8-R15). Thumb code can t support coprocessors. ARM922T Test and Debug Resources 48 ARM922T provides the following resources for testing and debugging ARM922T based systems: JTAG (Boundary Scan Test IEEE Std ). Trace Interface Port. TrackingICE. AMBA Test Interface.

25 A Hand-Out ARM922T Test and Debug Resources ARM922T has a JTAG Boundary Scan Test under IEEE Std specification. ARM922T has the following scan chains:. ARM922T Trace Interface Port: ETM9 50 ETM9 provides data and instruction trace, so is connected to ARM9 core. This is a powerful tool in validation for real-time systems!!! The ETM9 is controlled through a TAP through scan chain 6. Trace Debug Tools extension of ADS allows to create a debug program running on an external host.

26 A Hand-Out 26 ARM922T Trace Interface Port 51 This is the scheme to perform trace tracking: ARM922T Debug Mode 52 ARM922T get into the debug mode in three situations: Instruction fetch (breakpoint). EmbeddedICE Macrocell Data acces (watchpoint). Debug Request. The debug mode forces the core to isolate from memory system and ignore interruptions. Once in the debug mode it is possible to send the state of the core to a debug host through JTAG-style serial interface.

27 A Hand-Out ARM922T Debug Mode After examine the core or the external system, the program can resume normal program execution at the same point it was stopped. ARM922T EmbeddedICE Macrocell 54 It is internal to ARM9TDMI core. It is intended to help the external debugger. Allows to introduce hardware breakpoints and watchpoints. Allows stepping execution of core. Allows enter in debugger state as a result of a fetch to an exception vector. Communication with the external debugger through CP14.

28 A Hand-Out ARM922T TrackingICE Allows to connect the core to an external ARM9TDMI test chip which tracks our core through some ARM922T output signals. The ARM922T has to enter in the TrackingICE... BUT ARM922T TECHNICAL REFERENCE MANUAL DON T SAY HOW!!! ARM922T AMBA Test Interface 56 ARM922T provides an interface that acts as a slave to an AMBA tester. This is called SSM (Slave State Machine). There are 6 possible tests: Functional Test PA TAG RAM Instruction MMU test Data MMU test Instruction cache test Data cache test

29 A Hand-Out ARM922T AMBA Test Interface SSM is address mapped, so a change in the base address makes it enter/exit in a test mode: This is the right moment to introduce AMBA test philosophy. ARM922T AMBA Test Philosophy 58 Devices are tested in isolation, so no other device is connected to the bus:

30 A Hand-Out ARM922T AMBA Test Interface It is necessary to have a TIC bus master to convert the test vectors applied from outside into internal AMBA bus data: ARM922T AMBA Test Interface 60 Three control signal are dedicated signals for test purposes: It is possible to introduce burst vectors.

31 A Hand-Out ARM922T Available Software for developers ARM provides the ADS (ARM Development Suite). ADS is intended to develop and debug applications for the ARMfamily processors. ADS allows to use C, C++, EC++ or ARM assembly language. ADS includes: Command-line development tools. GUI development tools. Some interesting extensions are available. ARM922T ADS 62 Command-line development tools includes: armcc: C compiler. armcpp: C++ compiler. Tcc: C compiler to generate Thumb code. tcpp: C++ compiler to generate Thumb code. armasm: ARM and Thumb assembler. armlink: ARM linker. armsd: ARM and Thumb symbolic debugger.provides source level debugging for C or assembly languages programs.

32 A Hand-Out ARM922T ADS GUI development tools included are: AXD: The Window and Unix debugger for C and assembly language. CodeWarriorIDE: The project manager tool for Windows An important extension for ADS is Multi-Ice: Debug tool that provides an interface between WorkStation paralell port and JTAG port of the device. Supports ImbeddedICE Macrocell in order to perform core running program debug.