Agenda. ARM Core Data Flow Model Registers Program Status Register Pipeline Exceptions Core Extensions ARM Architecture Revision

Transcription

1 Agenda ARM Processor ARM Core Data Flow Model Registers Program Status Register Pipeline Exceptions Core Extensions ARM Architecture Revision ARM Core Data Flow Model Registers ARM has 37 registers which are 32-bits long Program counter : 1 CPSR : 1 SPSR : 5 General purpose registers : 30 The current processor mode governs which of several banks is accessible

2 ARM Register Set Program Status Register (PSR) CPSR holds the current status information SPSR preserves the CPSR during exceptions PSR : Condition Flags PSR : Processor States N : Negative result from ALU Z : Zero result from ALU C : ALU operation Carried out V : ALU operation overflowed Q : Overflow & Saturation ARMv5TEJ only Instruction Size Core instructions cpsr ARM Thumb Jazelle 32-bit 16-bit 8-bit T=0 J=0 T=1 J=0 Over 60% of Java : H/W The rest : S/W T=0, J=1

3 PSR : Interrupt Masks used to stop specific interrupt requests from interrupting the processor I = 1: Disables the IRQ F = 1: Disables the FIQ PSR : Processor Mode Mode Abbreviation Privileged Bits [4:0] Abort abt Yes Fast Interrupt fiq Yes Interrupt request irq Yes Supervisor svc Yes System sys Yes Undefined und Yes User usr No Pipeline The mechanism a RISC processor uses to execute instructions Exceptions Reset When power is applied Undefined instruction When the processor cannot decode an instruction Software interrupt When the processor meet an SWI instruction

4 Exceptions (Cont.) Prefetch abort When the processor attempts to fetch an instruction from an address without the correct access permission Data abort When an instruction attempts to access data memory without the correct access permissions Exceptions (Cont.) Interrupt request (IRQ) When an external hardware interrupts the normal execution flow of the processor Fast interrupt request (FIQ) When an hardware requiring faster response times interrupts the normal execution flow of the processor Exception vector table Exception Shorthand Vector address High address Reset RESET 0x xffff0000 Undefined instruction UNDEF 0x xffff0004 Software interrupt SWI 0x xffff0008 Prefetch abort PABT 0x c 0xffff000c Data abort DABT 0x xffff0010 Reserved - 0x xffff0014 Interrupt request IRQ 0x xffff0018 Exception handling When an exception occurs, Copies CPSR into SPSR_<mode> Sets appropriate CPSR bits Change to ARM state Change to exception mode Disable interrupts (if appropriate) Stores the return address in LR_<mode> Set PC to vector address Fast interrupt request FIQ 0x c 0xffff001c

5 Exception handling (Cont.) To return, Restore CPSR from SPSR_<mode> Restore PC from LR_<mode> Core Extensions Cache TCM (Tight Coupled Memory) Memory Management Hardware Non-protected Memory MPU (Memory Protection Unit) MMU (Memory Management Unit) Coprocessors Cache Improves the overall system performance TCM Improves deterministic real-time response < A simplified Von-Neumann architecture with cache > < A simplified Harvard architecture with TCMs >

6 Memory Management Hardware Non-protected memory Small embedded systems that require no protection from rouge application MPU Simple systems that uses a limited number of memory regions MMU More sophisticated platform operating systems that support multitasking Coprocessors Extends the processing features of a core by extending the instruction set or by providing configuration registers Vector Floating-Point (VFP) operations CP10/CP11 System Control Coprocessor CP15 Controls the cache, TCMs, MPU, MMU ARM Architecture Revision ARM {x}{y}{z}{t}{d}{m}{i}{e}{j}{f}{-s} ARM7/ARM9/ARM10/ARM11 ARM7TDMI/ARM720T/ARM7EJ-S ARM920T/ARM922T/ARM940T ARM926EJ-S/ARM946E-S/ARM966E-S ARM1020E/ARM1020E/ARM1022E ARM1136J-S/ARM1136JF-S ARM7 Von Neumann architecture Unified cache Both data and instructions use the same bus 3-stage pipeline ARMv4T Example ARM7TDMI ARM720T ARM7EJ-S

7 ARM7 (Cont.) ARM9 Harvard architecture Saperated Instruction memory interface Data memory interface 5 stage pipeline Example ARM920T/ARM922T ARM940T ARM946E-S/ARM966E-S ARM920EJ-S ARM9 (Cont.) ARM10 6 stage pipeline Vector Floating-Point Example ARM1020E Separate 32K D+I caches VFP/MMU Dual 64-bit bus interface ARM1026EJ-S Both MPU and MMU

8 ARM11 8-stage pipeline ARMv6 SIMD (Single Instruction Multiple Data) Example ARM1136J-S ARM1136JF-S StrongARM/Xscale Harvard architecture separate D+I caches 5-stage pipeline Not support the Thumb instruction set