Hercules ARM Cortex -R4 System Architecture. Memory Protection Unit (MPU)
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1 Hercules ARM Cortex -R4 System Architecture Memory Protection Unit (MPU)
2 Memory Protection Unit (MPU): Regions 8, 12, or 16 regions ARM Cortex-R5 has 16 regions ARM RM42 (Corona) has 8 regions All other Hercules ARM processors have 12 regions The region with highest region number has the highest priority. Overlay of regions is possible. Regions are defined based on the following: Base address Region size Sub-regions Region attributes Region access permissions NOTE: Before enabling the MPU, at least one region has to be defined. Otherwise the CPU can get into a state which can only be recovered by reset!
3 Memory Protection Unit: Memory map by region TMS570 Default Memory Map Region 12 Region1 Instruction Memory Type Data Memory Type Address Range Cache enabled Cache disabled Cache enabled Cache disabled Execute Never 0xFFFFFFFF 0xFFF xFFF7FFFF 0xFFF xFFA0FFFF 0xFFA xFF7FFFFF 0xFF xFEFFFFFF 0xFE xFDFFFFFF 0xFD x64FFFFFF 0x x1FFFFFFF 0x x17FFFFFF 0x x00FFFFFF 0x System Registers Peripheral Registers Coresight Debug Peripheral Memory Normal Normal Strongly Ordered Strongly Ordered Execute Never Normal Normal Strongly Ordered Strongly Ordered Execute Never Normal Normal Strongly Ordered Strongly Ordered Execute Never Normal Normal Strongly Ordered Strongly Ordered Execute Never CRC Normal Normal Strongly Ordered Strongly Ordered Execute Never HPI Normal Normal Strongly Ordered Strongly Ordered Execute Never External Memory Flash Swap esram Program Memory Normal, Cacheable, Non- Normal, Cacheable, Non- Normal, Cacheable, Non- Normal, Cacheable, Non- Normal, WBWA- Normal, WBWA- Normal, WBWA- Normal, WBWA- Cacheable, Cacheable, Cacheable, Cacheable, Execution Permitted Execution Permitted Execution Permitted Execution Permitted
4 Memory Protection Unit: Memory Attributes Strongly-ordered (so) and Device (dev): Explicit load/stores to strongly-ordered and device regions always produce the exact size and number of transactions. Accesses to strongly-ordered and device regions always appear in the order they are listed in the program. Strongly-ordered versus Device: Strongly-ordered access are ordered with respect to *all* other explicit load/stores. Device accesses are only ordered with respect to other device accesses. Normal (norm): Load/stores to normal memory regions may result in any size and number of transactions. For example: Two neighboring half-word stores might be merged into a single-word write. With respect to ordering, accesses to normal memory may be reordered. Examples: load-norm-a, load-dev-b, load-dev-c, load-norm-d could be performed as ADBC, or even DBCA; load-norm-a, load-so-b, load-so-c, load-norm-d must be performed as ABCD.
5 Memory Protection Unit: Memory Regions Base Address Defines start of memory address range Has to be multiple of region size (e.g. 256 byte region aligned on 256 byte boundary) Non-size aligned regions might result in unpredictable behavior Region size: From 32B up to 4GB Region attributes: Define access permissions for a region Memory type (strongly ordered, normal, device), non-shared Non-cachable Write-through cachable Write-back cachable
6 Memory Protection Unit: Overlapping Memory Regions & Sub-regions Overlapping regions: Higher-numbered region defines access permission. Provides more flexibility to protect memory which is not region-size aligned. Region2 Region 1 0x08001FFF user mode write access to 0x x x Region 1: User mode Read/Write Region 2: Privileged Write Data Abort Sub-regions: Each region can be split into 8 equal size, nonoverlapping sub-regions. Sub-regions can be enabled/disabled in the CP15 (MPU Region Size and Enable Register). Region sizes below 256 bytes do not support sub-regions. Region 1 Guard-Region 0x08005FFF 0x080043FF 0x write access to 0x Region 1: Has 8 sub-regions Sub-region 1 is disabled Data Abort
7 For more information SafeTI Web Page: Hercules Web Page: Data sheets Technical Reference Manual Application notes Software & tools downloads and updates Order evaluation and development kits Hercules Safety Microcontrollers Training Series training.ti.com/hercules Cortex-R Processor Architecture Peripherals Software Functional Safety For questions about this training, refer to the Engineer-2-Engineer Support Forum News and announcements Ask technical questions Search for technical content
8 TI Information Selective Disclosure
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