Machine-level Representation of Programs

Transcription

1 Machine-level Representation of Programs Jinkyu Jeong Computer Systems Laboratory Sungkyunkwan University SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong

2 Program? 짬뽕라면 준비시간 :10 분, 조리시간 :10 분 재료라면 1개, 스프 1봉지, 오징어 1/4마리, 호박 1/4개, 양파 1/2개, 양배추 1장, 당근 1/4개, 물 3컵 (600cc) Data 만드는법 1. 오징어는껍질을벗기고깨끗하게씻어칼집으로모양을낸다. 2. 호박, 양파, 양배추는모두채썬다. 3. 냄비에물 3컵을붓고끓인다. 4. 물이끓으면스프를넣고오징어와야채를넣어충분히맛이우러나도록 5분정도끓여준다. 5. 끓으면면을넣어익힌다. Instructions Source: SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong 2

3 Computer System CPU Processing unit Address Data Instruction Memory Storage unit Data movement Arithmetic & logical ops Control transfer Byte addressable array Code + data (user program, OS) Stack to support procedures SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong (jinkyu@skku.edu) 3

4 CPU Central Processing Unit PC (Program Counter) Address of next instruction Called EIP (IA-32) or RIP (x86-64) Register file Heavily used program data Condition codes Store status information about most recent arithmetic operation Used for conditional branching Cond. Codes PC ALU Register File SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong 4

5 Architecture the attributes of a system as seen by the programmer, i.e., the conceptual structure and functional behavior, as distinct from the organization of the data flow and controls, the logical design, and the physical implementation -- Amdahl, Blaauw, and Brooks, Architecture of the IBM System/360, IBM Journal of Research and Development, April The visible interface between software and hardware What the user (OS, compiler, ) needs to know to reason about how the machine behaves Abstracted from the details of how it may accomplish its task SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong (jinkyu@skku.edu) 5

6 ISA Instruction Set Architecture (ISA) An important part of Architecture Above: how to program machine Processors execute instructions in sequence Below: what needs to be built Use variety of tricks to make it run fast Instruction set Processor registers Memory addressing modes Data types and representations Application Program Compiler ISA OS CPU Design Circuit Design Chip Layout SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong 6

7 Intel Architecture Architecture Brand Name XScale (IXA) IA-32 Intel 64 (IA-32e, EM64T, x86-64) Itanium (IA-64) Microarchitecture Brand Name P5 P6 NetBurst Mobile Core Processor Brand Name Pentium Pentium MMX Pentium Pro Pentium II Pentium III Pentium 4 Pentium D Pentium M Core Duo/Solo Core 2 Quad/Duo/Solo Processor Code Name P5, P54C, P54CS P55C, Tillamook Pentium Pro Klamath, Deschutes Katmai, Coppermine, Tualatin Willamette, Northwood, Prescott, Cedar Mill Smithfield, Presler Banias, Dothan Yonah Conroe, Allendale, Wolfdale Merom, Penryn Kentsfield, Yorkfield SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong (jinkyu@skku.edu) 7

8 Recent Intel Microarchitectures Nehalem (2008): 45nm Incorporates the memory controller into the CPU Core i7, i5, i3 Sandy Bridge (2011): 32nm Ivy Bridge (2012): 22nm Haswell (2013): 22nm Broadwell (2014): 14nm Skylake (2015): 14nm Kaby Lake (2017): 14nm broken Tick-tock model SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong 8

9 Intel x86 Processors Evolutionary design Starting in 1978 with 8086 Added more features as time goes on Still support old features, although obsolete Totally dominate laptop/desktop/server market Complex Instruction Set Computer (CISC) Many different instructions with many different formats Hard to match performance of Reduced Instruction Set Computer (RISC) But Intel has done just that! In terms of speed. Less so for low power SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong 9

10 Intel x86 History Evolution with backward compatibility Year Name TRs Hz Note K 8M First 16-bit processor K 20M IA-32 : first 32-bit processor M 25M Integrated FP unit 1995 Pentium Pro 5.5M 200M PAE 1997 Pentium MMX 4.5M 200M MMX 1999 Pentium III 8.2M 500M SSE 2000 Pentium 4 42M 1.5G SSE Pentium 4E 125M 2.8G Intel 64 : first 64-bit processor, SSE Core 2 Duo 291M 2.3G First multi-core processor, SSSE Core 2 (Penryn) 820M 2.5G SSE Core i7 731M 2.9G Quad-core, SSE4.2 SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong (jinkyu@skku.edu) 10

11 2018 State of the Art Desktop: Core i7-8700k (Coffee Lake) 7th generation Intel Core processor with 14nm 6 cores ( GHz, 95W Max 64GB Memory, 12MB L3 Cache Integrated Graphics (UHD 630) 16 PCIe 3.0 lanes Server: Xeon Platinum 8180M (Skylake) 6th generation Intel Core processor with 14nm 28 cores ( GHz, 205W Max 1.5TB Memory, 38.5MB L3 Cache 48 PCIe 3.0 lanes SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong (jinkyu@skku.edu) 11

12 AMD: x86 Clones Historically AMD has followed just behind Intel A little bit slower, a lot cheaper Then Recruited top circuit designers from Digital Equipment Corp. and other downward trending companies Built Opteron: tough competitor to Pentium 4 Developed x86-64, their own extension to 64 bits Recent years Intel leads the world in semiconductor technology AMD has fallen behind SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong (jinkyu@skku.edu) 12

13 Intel s 64-bit History 2001: Intel attempts radical shift from IA32 to IA64 Totally different architecture (Itanium) Executes IA32 code only as legacy Performance disappointing 2003: AMD steps in with evolutionary solution x86-64 (now called AMD64 or Intel 64 ) 2004: Intel announces EM64T extension to IA32 Extended Memory 64-bit Technology Almost identical to x86-64! All but low-end x86 processors support x86-64 But, lots of code still runs in 32-bit mode SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong (jinkyu@skku.edu) 13

14 Turning C into Object Code gcc -Og p1.c p2.c -o p Use basic optimizations (-Og) Put resulting binary in file p text C program (p1.c p2.c) Compiler (gcc -Og -S) text binary binary Linker (gcc or ld) Asm program (p1.s p2.s) Object program (p1.o p2.o) Executable program (p) Assembler (gcc or as) Static libraries (.a) SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong (jinkyu@skku.edu) 14

15 Compiling into Machine Code Machine code (or binary code) The byte-level programs that a processor executes Assembly code A text representation of machine code gcc -Og -S sum.c sum.c long sum (long x, long y) { return x + y; } sum.s sum: leaq (%rdi,%rsi),%rax ret sum.o <sum>: 0x48 0x8d 0x04 0x37 0xc3 SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong (jinkyu@skku.edu) 15

16 Machine Code Example C code: add two signed integers Assembly Add two 8-byte integers quad words in x86-64 parlance Same instruction whether signed or unsigned Operands x: Register %rdi y: Register %rsi t: Register %rax Machine code 4-byte instruction Stored at address 0x4004d6 long t = x + y; leaq (%rdi,%rsi),%rax 0x4004d6: 48 8d SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong (jinkyu@skku.edu) 16

17 Object Program Assembler Translates.s into.o Binary encoding of each instruction Nearly-complete image of executable code Missing linkages between code in different files Linker Resolves references between files Combines with static run-time libraries e.g. code for malloc(), printf(), etc. Some libraries are dynamically linked Linking occurs when program begins execution 0x4004d6 <sum>: 0x48 0x8d 0x04 0x37 0xc3 Total of 5 bytes Each instruction 1 or 4 bytes Starts at address 0x4004d6 SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong (jinkyu@skku.edu) 17

18 Assembly Characteristics: Data Types integer data of 1, 2, 4, or 8 bytes Data values Addresses (untyped pointers) (cf.) In x86-64, a word means 16-bit data Floating point data of 4, 8, or 10 bytes No aggregated types such as arrays or structures Just contiguously allocated bytes in memory SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong (jinkyu@skku.edu) 18

19 Assembly Characteristics: Operations Perform an arithmetic or logical function on register or memory data Transfer data between memory and register Load data from memory into register Store register data into memory Transfer control Unconditional jump Conditional branch Procedure call and return SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong 19

20 Disassembling Disassembler: objdump -d sum.o Useful tool for examining object code Analyzes bit pattern of series of instructions Produces approximate rendition of assembly code Can be run on either a.out (complete executable) or.o (object code) file sum.o: file format elf64-x86-64 Disassembly of section.text: <sum>: 0: 48 8d lea (%rdi,%rsi,1),%rax 4: c3 retq SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong 20

21 Disassembling with gdb Disassemble procedure, sum $ gcc Og g sum.c main.c $ gdb a.out (gdb) disassemble sum Dump of assembler code for function sum: 0x d6 <+0>: lea (%rdi,%rsi,1),%rax 0x da <+4>: retq End of assembler dump. Examine 5 bytes starting at sum (gdb) x/5 sum 0x4004d6 <sum>: 0x48 0x8d 0x04 0x37 0xc3 SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong (jinkyu@skku.edu) 21

22 Whose Assembler? Intel/Microsoft differs from ATT/GAS (GNU Assembler) Operands listed in opposite order mov Dest, Src movq Src, Dest Constants not preceded by $, denote hex with h at end sub rsp,100h subq $0x100,%rsp Operand size indicated by operands rather than operator suffix cmp qword ptr [rbp-8],0 cmpq $0,-8(%rbp) Addressing format shows effective address computation mov rax,qword ptr [rax*4+100h] movq $0x100(,%rax,4),%rax (gdb) set disassemble-flavor intel (gdb) disassemble sum 0x d6 <+0>: lea rax,[rdi+rsi*1] 0x da <+4>: ret SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong (jinkyu@skku.edu) 22

23 x86-64 Reference Intel 64 and IA-32 Architectures Software Developer s Manuals Volume 1: Basic architecture Volume 2: Instruction set reference, A-Z Volume 3: System programming guide Available online: SSE2030: Introduction to Computer Systems, Spring 2018, Jinkyu Jeong (jinkyu@skku.edu) 23