Synchronous (burst) mode register setting for NOR Application Note
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1 Synchronous (burst) mode register setting for NOR Application Note Version 1.0, May-2009 Samsung Electronics Copyright c 2006 Samsung Electronics Co.,LTD.
2 Copyright 2004 Samsung Electronics Co, Ltd. All Rights Reserved. Though every care has been taken to ensure the accuracy of this document, Samsung Electronics Co, Ltd. cannot accept responsibility for any errors or omissions or for any loss occurred to any person, whether legal or natural, from acting, or refraining from action, as a result of the information contained herein. Information in this document is subject to change at any time without obligation to notify any person of such changes. Samsung Electronics Co, Ltd. may have patents or patent pending applications, trademarks copyrights or other intellectual property rights covering subject matter in this document. The furnishing of this document does not give the recipient or reader any license to these patents, trademarks copyrights or other intellectual property rights. No part of this document may be communicated, distributed, reproduced or transmitted in any form or by any means, electronic or mechanical or otherwise, for any purpose, without the prior written permission of Samsung Electronics Co, Ltd. The document is subject to revision without further notice. All brand names and product names mentioned in this document are trademarks or registered trademarks of their respective owners. Contact Information Mobile/ Flash Application Engineering Group Memory Division, Semiconductor Business Samsung Electronics Co., Ltd Address : San #16, Banwol-Ri, Taean-Eup, Hwasung-City, Gyeonggi-Do, Korea, Samsung Electronics Co; LTD 2
3 Purpose This application note will show how to set synchronous (burst) read mode during NOR operation. Both Burst mode register and extended register in NOR are related to synchronous read mode. You can change the sync mode and sync type using by put any value into these register. This is helpful for NOR software engineers. Definitions and Acronyms Definitions and Acronyms SLC MLC tiaa AVD CR Description Single Level Cell Multi Level Cell Initial Access Time Address Valid Input SIGNAL Configuration Register References NOR DATASHEET Samsung Electronics Co; LTD 3
4 Table of contents 1. What is synchronous (burst) read mode? 2. The latest NOR line up 2.1 NOR Line up is now available in 1Q, How to entry synchronous mode 3.1 Not using Extended Configuration Register Called no option 3.2 Using "Extended Configuration Register" Called Sync MRS Option 3.3 Product lists according to sync MRS option and no option 4. Burst Mode Configuration Register 4.1 Burst mode configuration register table for 256 / 512Mbit 4.2 Burst mode configuration register table for 32 / 64 / 128Mbit 4.3 Set Burst mode configuration register command sequence 5. Extended Configuration Register 5.1 Extended configuration register table for 256 / 512Mbit 5.2 Extended configuration register table for 16 / 32 / 128Mbit 5.3 Extended configuration register command sequence 6. The symptoms by improper value in sync mode Samsung Electronics Co; LTD 4
5 1. What is synchronous (burst) read mode? The device is capable of continuous or preset length linear burst read operation. Burst read allows system to be able to fetch mass word data faster than a word of single read. For the burst mode, the system should determine how many clock cycles are desired for the initial word (tiaa) of each burst access and what mode of burst operation is desired using "Burst Mode Configuration Register" command sequence. In addition to, "Extended Configuration Register" should be used to entry synchronous mode regarding some of devices. It described below in more detail. 2. The latest NOR line up 2.1 NOR Line up is now available in 1Q, 2009 Part Name Device Density Version SLC/ MLC K8S6415ET(B)C 32Mbit F die SLC K8S6415ET(B)C 64Mbit C die SLC K8S2815ET(B)C 128Mbit C die SLC K8F53(56)(57)15E(T/B/Z)A 256Mbit A die MLC K8F09(12)15E(T/B/Z)A 512Mbit A die MLC 3. How to enter sync (synchronous) mode There are two methods to enter the synchronous read mode. One type is only supported in each device and you could distinguish from the part name of device. 3.1 Not using Extended Configuration Register Called no option The synchronous (burst) mode will automatically start on the rising edge of the CLK Input when /AVD is low. If there are several CLKs in /AVD low, the last rising edge one is valid CLK. 3.2 Using "Extended Configuration Register" Called Sync MRS Option The synchronous (burst) mode will automatically start on the rising edge of the CLK input when /AVD is low after Extended Mode Register Setting to A13=0, A12=1 (Case of 256, 512Mbit) and A12 =1 (Case of 32, 64, 128Mbit). If there are several CLKs in AVD low, the last rising edge one is valid CLK. Samsung Electronics Co; LTD 5
6 3.3 Product lists according to sync MRS option and no option Options Part Name Density Sync MRS Option No option 32Mbit K8S3015ET(B)F K8S3115ET(B)F K8S3315ET(B)F K8S3215ET(B)F 64Mbit K8S6215ET(B)C K8S6315ET(B)C K8S6515ET(B)C K8S6415ET(B)C 128Mbit K8S2615ET(B)C K8S2715ET(B)C K8S2915ET(B)C K8S2815ET(B)C K8F5315ET(B)A K8F5415ET(B)A 256Mbit K8F5615ET(B)A K8F5515ET(B)A K8F5715ET(B)A K8F0915ET(B)A K8F1015ET(B)A 512Mbit K8F1215ET(B)A K8F1115ET(B)A K8F1315ET(B)A 4. Burst Mode Configuration Register 4.1 Burst mode configuration register table for 256 / 512Mbit Samsung Electronics Co; LTD 6
7 4.2 Burst mode configuration register table for 32 / 64 / 128Mbit 4.3 Set Burst mode configuration register command sequence No. of Cycle 1 ST Cycle 2 nd Cycle 3 rd Cycle Address 0x555H 0x2AAH CR + 0x555H 3 Data 0xAAH 0x55H 0xC0H CR = Configuration Register setting value Case of 256 / 512Mbit = A21 ~ A11 (Refer to 4.1). Case of 32 / 64 / 128Mbit = A20 ~ A12 (Refer to 4.2) Example code1 : typedef volatile unsigned short UINT16; /* Unlock command */ *( (UINT16 *) 0x555 ) = 0xAA; *( (UINT16 *) 0x2AA ) = 0x55; /* CR Value setting */ *( (UINT16 *)CR + 0x555 ) = 0xC0; CR Value Example Device - 512Mbit, Output Drive Control [A21 :19] 4, RDY Active [A18] 1, Burst read mode [A17 :15] 2, Programmable Wait State [A14 :11] 3. add A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10~A0 value x555 CR Value = 0x251B *( (UINT16 *)0x251B) = 0xC0; Samsung Electronics Co; LTD 7
8 5. Extended Configuration Register 5.1 Extended configuration register table for 256 / 512Mbit 5.2 Extended configuration register table for 16 / 32 / 128Mbit Note : 16,32 and 128Mbit have no option about RDY Polarity, The only is set to active low. 5.3 Extended configuration register command sequence No. of Cycle 1 ST Cycle 2 nd Cycle 3 rd Cycle Address 0x555H 0x2AAH CR + 0x555H 3 Data 0xAAH 0x55H 0xC5H CR = Configuration Register setting value Case of 256 / 512Mbit = A13 ~ A11 (Refer to 5.1). Case of 32 / 64 / 128Mbit = A12 (Refer to 5.2) Example code1 : typedef volatile unsigned short UINT16; /* Unlock command */ *( (UINT16 *) 0x555 ) = 0xAA; *( (UINT16 *) 0x2AA ) = 0x55; /* CR Value setting */ *( (UINT16 *)CR + 0x555 ) = 0xC5; CR Value Example Device - 512Mbit, Read mode [A13 : 12] 1, RDY Polarity [A11] 0. Add A13 A12 A11 A10~A0 value x555 CR Value = 0x15 *( (UINT16 *)0x15) = 0xC5; Samsung Electronics Co; LTD 8
9 6. The symptoms by improper value in sync mode 6.1 Asynchronous read operation is good, but synchronous only is problem. 6.2 The error is occurred after clock frequency is changing. 6.3 Some read data are misaligned when controller attempt to fetch read data. Samsung Electronics Co; LTD 9
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