EE457. Homework #7 (Virtual Memory)

Transcription

1 EE457 Homework #7 (Virtual Memory) Instructor: G. Puvvada Due: Please check on the BB Part Ia, Part Ib, and Part Ic are based on the textbook questions/figures. These are detailed in the first five pages. The rest of the parts are from the previous ee457 midterm/final exams. These questions are attached after the Part I questions. Part II Question 3 from Spring 1994 Final exam Part III Question 5 from Fall 1995 Final exam Part IV Question 5 from Spring 1999 Midterm exam Part Ia Exercises from the third edition of the textbook. Problems 7.39(7.32), 7.40(7.33) reproduced below for your convenience. Note: The exercise numbers in parentheses are the corresponding second edition exercise numbers Consider a virtual memory system with the following properties: - 40-bit virtual byte address - 16 KB pages - 36-bit physical byte address What is the total size of the page table for each process on this processor, assuming that the valid, protection, dirty, and use bits take a total of 4 bits and that all the virtual pages are in use? (Assume that disk addresses are not stored in the page table.). Note for EE457 students: Show your answer in this rectangle together with your calculations/explanation. If the page table entry is a little less than 32 bits, allocate 32-bit word for the entry as it would be difficult to deal with say 29-bit wide table. Also assume that it is a single level table. EE457 Homework #7 Page 1 / 12 C Copyright 2004 Gandhi Puvvada

2 7.40 Assume that the virtual memory system of Exercise 7.39 is implemented with a two-way set-associative TLB with a total of 256 TLB entries. Show the virtual-to-physical mapping with a figure like Figure 7.24 on page 525. Make sure to label the width of all fields and signals. Note to EE457 students: It is best to show an arrangement similar to the figure on page 7-55 of the classnotes. For this exercise 7.40(7.33), while you could use either the figure 7.25 on page 593 of the second edition or figure 7.24 on page 525 of the third edition (which are later reproduced in part Ic of this homework), we prefer that you refer to the figure on Intel i860 TLB arrangement 7-45 of the classnotes mainly because the TLB uses set associative mapping. Also look at page 7-12 of the classnotes to arrive at how many RAMs of what size are need to build the TLB. Show what portion of the virtual address is used to index these RAMs. Show comparators in a fashion similar to page 7-55 of the class notes. Answer in the rectangle below. Virtual Address VA[39:0] VA39 VA0 PA35 PA0 Physical address PA[35:0] EE457 Homework #7 Page 2 / 12 C Copyright 2004 Gandhi Puvvada

3 Part Ib - Relation between Cache, TLB and the Page Table Reproduced below is the Figure 7.26 on page 527 from the 3 rd edition of your textbook (figure 7.27 on page 595 of the 2 nd edition). PT Page Table Ib.1 Based on the bottom three rows of the above table, we can say that if the page is (present/ absent) in the main memory, then there (will be / can t be) a (hit / miss) in (TLB / Cache / either TLB or Cache / neither TLB nor Cache). Ib.2 By increasing the main memory, we can be sure to increase the HIT rate of (Cache / TLB / PT). Ib.3 Please refer to the first row of the above table. While a (hit / miss) in TLB guarantees a (hit / miss) in the Page Table, we note that a (hit / miss) in TLB (does / does not) necessarily imply (either a hit or a miss / neither a hit nor a miss) in the page table. Ib.4 Before a page in the main memory is removed (and perhaps copied back to the secondary storage), any blocks of the page in the (cache / TLB) are to be flushed to the main memory and the corresponding translation entry in TLB shall be _ (validated / invalidated). Ib.5 Replacement of an entry in TLB is (possible even though / impossible if) no pages are altered in the main memory (i.e. no new page is brought into the main memory or no existing page has been removed from the main memory). Replacement of a block in cache is (possible even though / impossible if) no pages are altered in the main memory (i.e. no new page is brought into the main memory or no existing page has been removed from the main memory). Ib.6 The block in cache that is being replaced or removed (is never written back to the main memory / is always written back to the main memory / written back to the main memory if write-back policy is used and the block is modified during its residency in the cache). EE457 Homework #7 Page 3 / 12 C Copyright 2004 Gandhi Puvvada

4 Part Ic: Let s take a closer look at Fig.7.25 from the 2 nd edition textbook and Fig.7.24 from the 3 rd edition textbook reproduced on the side and answer the following questions. TLB Valid Dirty Virtual address Virtual page number Page offset Tag Physical page number Ic.1 From these 2 figures we can tell that the TLB uses (fully associative mapping / set-associative mapping/ direct mapping) because Ic.2 From these 2 figures we can tell that the cache uses (fully associative mapping / set-associative mapping/ direct mapping) because Ic.3 The page size is (the same / different) in these two cases. The page size in the case of the fig of the 3rd edition is KB and it can be inferred from (which field). TLB hit Cache Cache hit Physical page number Page offset Physical address Physical address tag Cache index Valid Tag Data Fig 7.25 from the second edition of the textbook Fig from the third edition textbook Data 32 Byte offset 2 Ic.4 To search for an entry in the TLB we need (one comparator / two comparators / as many comparators as there are entries in the TLB) each of bits wide. Fig 7.24 from the third edition of the textbook 32 EE457 Homework #7 Page 4 / 12 C Copyright 2004 Gandhi Puvvada

5 Ic.5 In both cases (in both figures) you use (Physical address tag / Cache index / Block offset / Byte offset / a concatenations of...) to index the tag RAM in cache. In Fig.7.25 (from the 2 nd edition) you use (Physical address tag / Cache index / Block offset / Byte offset / a concatenations of...) to index the cache data RAM. In Fig.7.24 (from 3 rd edition) you use (Physical address tag / Cache index / Block offset / Byte offset / a concatenations of...) to index the cache data RAM. Ic.6 In Fig.7.25 (from the 2 nd edition) the shaded area in the cache data RAM is (an entire cache block / a part of a cache block). In Fig.7.24 (from 3 rd edition) the shaded area in the cache data RAM is (an entire cache block / a part of a cache block). Cache blocks in the two figures are (of the same size/different in sizes). The cache block size in the case of fig of the 3 rd edition is Bytes. This information is obtained from looking at the size of (state the name of the field(s)). Ic.7 In both figures we (have to / don t have to) wait until the translation from virtual address to physical address is done to access the cache. This architecture is called (physically indexed physically tagged (PIPT) / virtually indexed physically tagged (VIPT)) cache. To convert the current scheme to the other (PIPT to VIPT or VIPT to PIPT as the case may be), in the case of Fig.7.25 (from 2 nd edition), we can perhaps (i) consider _ (increasing / decreasing) the page size to KBytes from the current size of KBytes or (ii) consider (increasing / decreasing) the cache size to KBytes from the current size of KBytes. To convert the current scheme to the other (PIPT to VIPT or VIPT to PIPT as the case may be), in the case of Fig.7.24 (from 3 rd edition), we can perhaps (i) consider _ (increasing / decreasing) the page size to KBytes from the current size of KBytes or (ii) consider (increasing / decreasing) the cache size to KBytes from the current size of KBytes. Ic.8 Usually TAG RAM is different from Data RAM in cache. For example, on page 7-12 of the classnotes, we have two TAG RAMs each of 4x4 and two Data RAMs of 32x8. However, in some cases the TAG RAM and the Data RAM can be combined into one wide RAM if the (depth / width) is same for the TAG RAM and the Data RAM. Ic.9 Consider how the page 7-12 would look like if we change the block size from 8 words (= 8 bytes) to 1 word (= 1 byte). Then there will be 64 block-frames in the 64 location cache and 256 blocks in the main memory. The 64 block-frames in cache will be organized as 32 sets (since a set contains 2 blocks). Then the set filed is 5 bits, there is no word filed, and the TAG field is 3 bits as shown below. V TAG SET For this case, there will be (1 / 2 / 4 / 32 ) TAG RAMs each of size and there will be (1 / 2 / 4 / 32 ) Data RAMs each of size. Note that the number of TAG RAMs (similarly the number of Data RAMs) depends upon the degree of set associativity (= number of blocks per set (= 2 here)). EE457 Homework #7 Page 5 / 12 C Copyright 2004 Gandhi Puvvada

6

7

8

9

10

11

12