ELE 758 * DIGITAL SYSTEMS ENGINEERING * MIDTERM TEST * Circle the memory type based on electrically re-chargeable elements

Transcription

1 ELE 758 * DIGITAL SYSTEMS ENGINEERING * MIDTERM TEST * Student name: Date: Example 1 Section: Memory hierarchy (SRAM, DRAM) Question # 1.1 Circle the memory type based on electrically re-chargeable elements a) CPU-registers; b) Cache memory; c) Main memory (DRAM); d) Secondary memory devices (Disk). Correct answer: c). Comments: DRAM cell is based on capacitor, which is electrically re-chargeable element Question # 1.2 For 16 M x 32 bit SDRAM (64 Mbyte SIMM). a) Calculate number of SIMM pins used for address Number of address pins = Correct answer: Number of address pins = _12_ 24 Comments: Number of DRAM cells = 16 M = 2. Assuming that DRAM is square matrix 12 number of columns = number of rows = 2. Thus, number of Row address lines = 12 Column address lines = Log 2 = 12

2 b) Calculate an average word (32-bits) access time for above SDRAM if Bus clock frequency = 200 MHz, Bus width = 32 bits, block size to be transferred = 512 Bytes and the complete addressing period (RAS + CAS) = 20 c.c. (Clock cycles). Average Word access time = ns. Correct answer: Average Word access time = 5.78_ ns Comments: Latency (addressing period) + Block delivery time Average access word time (T av) = Number of words in block Block delivery time = 1 c.c. x (Number of words in block) Number of words in block = 512 Bytes / 4 Bytes = 128 words. Thus, 20 c.c. + 1 c.c. x 128 T av = = c.c. 128 Since Clock cycle period is = 1 / 200 MHz = 5 ns, T av. = x 5 ns = 5.78 ns 2 Section: Cache memory Question # 2.1 A computer system has memory subsystem with the Main memory (64 M x 8 bits) and Direct-mapped cache (256 K x 8bits) with cache block size = 128 x 8 bites. a) Calculate address word width in bits. W addr = bits Correct answer: W addr = 26 bits 26 Comments: Since each Byte (8 bits) has to be addressed in 64 MB memory = 2 Bytes 26 Address word should have Waddr = Log 2 = 26 bits

3 b) Divide the address word to: TAG; INDEX and BYTE OFFSET fields Number of TAG bits = Number of INDEX bits = Number of BYTE OFFSET bits = 0 Comments: 7 1. Number of bits in BYTE OFFSET = 7, since block length = 128 Bytes = 2 Bytes 2. Number of INDEX bits = Log (Number of Cache Entries). Number of cache entries = Cache volume / block size = 256 KB / 128 B = 2048 Thus, Number of INDEX bits = Log 2048 = 11 bits 3. Number of TAG bits = Address word width Index Byte offset = = 8 bit Question # 2.2 The content of a Direct-mapped Cache is shown on Fig The content of Main memory is shown on Fig.2.2 (See next page) Cache Index V TAG Registers Byte # 1 Byte # 0 Dirty bit 0 1 0x08 0x04 0x0A xA0 0xFF 0x0F x0F 0x05 0xFF x0A 0x00 0x x14 0x04 0x0A x17 0xFF 0x0F x12 0x05 0xFF x04 0x00 0x01 0 Fig. 2.1 Content of direct-mapped cache Address 0x0BE 0x0F4 0x12D 0x148 Fig. 2.2 Data 0x10 0xB5 0xA5 0x0A

4 Determine for the following references will it be hit or miss and what data CPU will get: a) If address word = 0x0F4, Result is Hit or Miss (circle)? What data (byte) CPU will read Initiate the write back procedure? Yes or No (circle)? Comments: Since Cache includes: 8 entries and 2 words in each block (See Fig. 2.1) then: INDEX should have 3 bits when OFFSET is only 1 bit. Thus Address= 0x0F = can be divided as Tag= , Index=010, Byte=0 Index 010 points to entry #2, where tag content 0F = tag of address word. V bit= 1 and thus, this is HIT Since Byte offset = 0 the Byte #0 = 0xFF will be delivered to CPU Write back procedure will not be initiated since HIT and there is no necessity for block replacement 3 Section: Virtual memory Question # 3.1 A 32-bits virtual address allows accessing to any byte in 128 MB main memory and 3.6 G Byte hard drive. Page size - S p was determined = 16 KB. Calculate the maximum number of Page table entries N pt and Page table size Vpt in K Bytes if a content of each page table entry includes the valid, dirty and reference bits + physical page number. a) Maximum number of Page table entries N pt max = Comments: Virtual address should address any byte in Address area = ( ) MB 32 = 2 Bytes. Thus Virtual Address word should be 32 bits long. However, since Page size 14 = 16 KB = 2, number of Virtual Pages = Max number of Page Table Entries = [32 bits (VA length) 14 bits (Page offset)] 18 = 2 = 2 = 256 K entries

5 b) Maximum Page table size V pt max = K Byte. Comments: Maximum Page table size = Number of Page table entries x Page Entry length (in Bytes) Page Entry length = 1 Valid bit + 1 Dirty bit + 1 Reference bit + Physical Page number Physical page number consists of = log 128 MB (Main memory size) - log 16 KB (Page offset length) = = 13 bits Thus, Page Entry length = = 16 bits = 2 Bytes And Maximum Page table size = 256 K x 2 B = 512 KB Question # 3.2 For above (Question 3.1) Virtual memory organization the content of the portion of the Page table for a task is shown on Fig. 3.1 Index Dirty Val Page table content x00B x00F x01F x00A x000F.... Fig. 3.1 For given Virtual address = 0x0000F2A0 do the following : a) Calculate the Virtual Page number (hex) = 0x b) Calculate Page offset (hex) = 0x

6 . Comments: Since Page offset contains 14 bits and the rest is Virtual page #, then if Virtual Address word = the Virtual Page # = 0x00003 and Page offset = 0x32A0 c) Calculate Physical address (hex) = 0x.. Comments: In Page Table Entry # 3 equal to Index = VA Page # 0x00003 Physical Page # = 0x00A1 and thus Physical address = = (PA#) & (Page Offset) = = (27 bit address for 128 MB memory) = = 0x 02872A0