Memory hierarchy and cache

Transcription

1 Memory hierarchy and cache QUIZ EASY 1). What is used to design Cache? a). SRAM b). DRAM c). Blend of both d). None. 2). What is the Hierarchy of memory? a). Processor, Registers, Cache, Tape, Main memory, Disk b). Processor, Registers, Cache, Main memory, Disk, Tape c). Processor, Registers, Cache, Tape, Disk, Main memory d). None. 3). Typically, a split cache divides both the L1 and L2 caches into an instruction-only cache and a data-only cache. a) True b) False c) None d) Both.

2 4) By having the cache act as a bridge between main memory and the CPU, the time it takes to retrieve a block of data from main memory is longer than it would be if the cache did not exist. a) True b) False c) None d) Both. 5) Which is the fastest cache mapping function? a.) Direct mapping b.) Set associative mapping c.) Fully associative mapping d.) None of these. 6) Cache memory refers to: a.) cheap memory that can be plugged into the mother board to expand main memory b.) fast memory present on the processor chip that is used to store recently accessed data c.) a reserved portion of main memory used to save important data d.) a special area of memory on the chip that is used to save frequently used constants.

3 7) is volatile, dynamic, very high speed computer memory a.) RAM b.) ROM c.) CMOS d.) Cache 8) How many bits do you need for a logical memory size of 1024K? A) 10 B) 20 C) D) ) Which cache mapping function does not require a replacement algorithm? a.) Direct mapping b.) Set associative mapping c.) Fully associative mapping d.) None of the options.

4 10) A memory management technique used to improve computer performance is: a.) selecting memory chips based on their cost b.) storing as much data as possible on disk c.) using the cache to store data that will most likely be needed soon d.) preventing data from being moved from the cache to primary memory. MEDIUM 1). Which is the fastest of all the memories? a). Main memory b). Tape c). Cache d). Disk. 2). Which of the following are CACHE mapping techniques? a). DIRECT MAPPING b). SET-ASSOCIATIVE Mapping c). FULLY ASSOCIATIVE Mapping d). All the above.

5 3). tend to represent a major bottleneck in system performance. a) CPUs b) Disks c) Programs d) I/O 4). CPU fetches the instruction from memory according to the value of: a) program counter b) status register c) instruction register d) program status word. Question 5-7 )) Design a 128KB direct-mapped data cache that uses a 32-bit address and 16 bytes per block. Calculate the following: 5) How many bits are used for the byte offset? a) 5 bits b) 7 bits c) 9 bits d) 10 bits. 6) How many bits are used for the set (index) field? a) 15 bits

6 b) 16 bits c) 17 bits d) 18 bits. 7) How many bits are used for the tag? a) 7 bits b) 8 bits c) 9 bits d) 10 bits. 8) A computer that is advertised as having a 96K byte DRAM memory and a 2.1 Gigabyte hard drive has a.) 96 K bytes of primary memory and 2.1 Gigabytes of secondary memory b.) 2.1 Gigabytes of primary memory and 96K bytes of secondary memory c.) 96 bytes of cache, 2.1 gigabytes of primary memory d.) 96K bytes of cache, 96 K bytes of primary memory, and 2.1 Gigabytes of secondary memory. 9) Which cache write mechanism allows an updated memory location in the cache to remain out of date in memory until the block containing the updated memory location is replaced in the cache? a.) Write through

7 b.) Write back c.) Both d.) Neither. a) True b) False c) None d) Both. 10) The number of lines contained in a set associative cache can be calculated from the number of bits in the memory address, the number of bits assigned to the tag, the number of bits assigned to the word id (identifying the number of words per block), and the number of bits assigned to the set id (identifying the number of sets.) HARD 1). Which type of CACHE WRITE technique is most suitable in the MULTIPROCESSOR systems? a). Write-Through b). Write -Back c). Both d). None.

8 2).Which one of the following is the address generated by CPU? a) Physical address b) Absolute address c) Logical address d) None of those mentioned above. 3).Run time mapping from virtual to physical address is done by: a) memory management unit b) CPU c) PCI d) none of those mentioned above. 4). If there are 32 segments, each of size 1Kb, then the logical address should have: a) 13 bits b) 14 bits c) 15 bits d) 16 bits. 5). Consider a computer with 8 Mbytes of main memory and a 128 K cache. The cache block size is 4 K. It uses a direct mapping scheme for cache management. How many different main memory blocks can map onto a given physical cache block?

9 a) 2048 b) 256 c) 64 d) 8. 6) Let's say a memory access to main memory on a cache "miss" takes 30 ns and a memory access to the cache on a cache "hit" takes 3 ns. If 80% of the processor's memory requests result in a cache "hit", what is the average memory access time? a.) 8.4 ns b.) 33 ns c.) 24.6 ns d.) 2.4 ns 7) An 8KB direct-mapped write-back cache is organized as multiple blocks, each of size 32-bytes. The processor generates 32-bit addresses. The cache controller maintains the tag information for each cache block comprising of the following. 1 Valid bit 1 Modified bit As many bits as the minimum needed to identify the memory block mapped in the cache. What is the total size of memory needed at the cache controller to store meta-data (tags) for the cache? (A) 4864 bits

10 (B) 6144 bits (C) 6656 bits (D) 5376 bits 8) A computer system has an L1 cache, an L2 cache, and a main memory unit connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times are 2 nanoseconds. 20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and main memory unit respectively. When there is a miss in L1 cache and a hit in L2 cache, a block is transferred from L2 cache to L1 cache. What is the time taken for this transfer? (A) 2 nanoseconds (B) 20 nanoseconds (C) 22 nanoseconds (D) 88 nanoseconds. 9) The memory access time is 1 nanosecond for a read operation with a hit in cache, 5 nanoseconds for a read operation with a miss in cache, 2 nanoseconds for a write operation with a hit in cache and 10 nanoseconds for a write operation with a miss in cache. Execution of a sequence of instructions involves 100 instruction fetch operations, 60 memory operand read operations and 40 memory operand write operations. The cache hit-

11 (A) 1.26 (B) 1.68 (C) 2.46 (D) 4.52 ratio is 0.9. The average memory access time (in nanoseconds) in executing the sequence of instructions is. A) 11 B) 14 C) 16 D) 27 10) A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The number of bits in the tag field of an address is. OLUTIONS EASY 1). A 2). B 3). B

12 4). A 5). A 6). B 7). D 8). B 9). A 10). C MEDIUM 1).C 2).D 3).B 4). A 5). B 6). A 7). D 8). A 9). B 10). B HARD 1). A 2). C

13 3). A 4). A 5). C 6). A 7). D {Explanation Cache size = 8 KB ; Block size = 32 bytes ; Number of cache lines = Cache size / Block size = ( bytes)/32 = 256 ; total bits required to store meta-data of 1 line = = 21 bits ; total memory required = = 5376 bits } 8) D {Explanation A block to access in L2 cache requires 20 nanoseconds, and 2 seconds to place in L1-cache. The block size in L1 cache is 4 words and there are total 16 words, so total time is 4*(20+2) = 88.} 9) B 10) C