Pentium 4 Processor Block Diagram
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1 FP FP Pentium 4 Processor Block Diagram FP move FP store FMul FAdd MMX SSE 3.2 GB/s 3.2 GB/s L D-Cache and D-TLB Store Load edulers Integer Integer & I-TLB ucode
2 Netburst TM Micro-architecture Pipeline vs P Fetch Fetch Decode Basic P6 Pipeline Decode Decode Intro at 733MHz.8µ ROB Rd Rdy/ Dispatch ec Basic Pentium 4 Processor Pipeline Intro at.4ghz.8µ Hyper pipelined Technology enables industry leading performance and clock rate Copyright 2000 Corporation.
3 : Trace cache next instruction pointer Pointer from the, indicating location of next instruction. Copyright 2000 Corporation. & I I-TLB edulers Integer FP L D D-Cache and D D-TLB
4 : Trace cache fetch Read the decoded instructions (uops) out of the ecution Copyright 2000 Corporation. & I I-TLB edulers Integer FP L D D-Cache and D D-TLB
5 Drive: Wire delay Drive the uops to the allocator Copyright 2000 Corporation. & I I-TLB edulers Integer FP L D D-Cache and D D-TLB
6 Alloc: Allocate Allocate resources required for execution. The resources include Load buffers, Store buffers, etc.. Copyright 2000 Corporation. & I I-TLB edulers Integer FP L D D-Cache and D D-TLB
7 : Register renaming the logical registers (EAX) to the physical register space (28 are implemented). Copyright 2000 Corporation. & I I-TLB edulers Integer FP L D D-Cache and D D-TLB
8 : Write into the uop ue uops are placed into the queues, where they are held until there is room in the schedulers Copyright 2000 Corporation. & I I-TLB edulers Integer FP L D D-Cache and D D-TLB
9 : edule Write into the schedulers and compute dependencies. Watch for dependency to resolve. Copyright 2000 Corporation. & I I-TLB edulers edulers Integer FP L D D-Cache and D D-TLB
10 Disp: Dispatch Send the uops to the appropriate execution unit. Copyright 2000 Corporation. & I I-TLB edulers Integer FP L D D-Cache and D D-TLB
11 : Register File Read the register file. These are the source(s) for the pending operation ( or other). Copyright 2000 Corporation. & I I-TLB edulers Integer FP FP L D D-Cache and D D-TLB
12 : ecute ecute the uops on the appropriate execution port. Copyright 2000 Corporation. & I I-TLB edulers Integer FP L D D-Cache and D D-TLB
13 Flgs: Flags Compute flags (zero, negative, etc..). These are typically the input to a branch instruction. Copyright 2000 Corporation. & I I-TLB edulers Integer FP L D D-Cache and D D-TLB
14 Br Ck: Branch Check The branch operation compares the result of the actual branch direction with the prediction. Copyright 2000 Corporation. & I I-TLB edulers Integer FP L D D-Cache and D D-TLB
15 Drive: Wire delay Drive the result of the branch check to the front end of the machine. Copyright 2000 Corporation. & I I-TLB edulers Integer FP L D D-Cache and D D-TLB
16 The ecution Copyright 2000 Corporation. FMul FAdd MMX SSE L D-Cache and D-TLB Store Load FP move FP store FP FP & I-TLB edulers 3.2 GB/s 3.2 GB/s Integer Integer ucode
17 ecution Advanced L instruction cache Caches decoded IA-32 instructions (uops) Removes decoder pipeline latency Capacity is ~2K uops Integrates branches into single line Follows predicted path of program execution ecution feeds fast engine Copyright 2000 Corporation.
18 ecution cmp 2 br -> > T..... (unused code) T: 3 sub 4 br -> > T (unused code) T2: 5 mov 6 sub 7 br -> > T (unused code) T3: 8 add 9 sub 0 mul cmp 2 br -> > T4 Delivery cmp 2 br T 3 T: sub 4 br T2 5 mov 6 sub 7 br T3 8 T3:add 9 sub 0 mul cmp 2 br T4 Copyright 2000 Corporation.
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