Lecture Topics. Announcements. Today: Data and Control Hazards (P&H ) Next: continued. Exam #1 returned. Milestone #5 (due 2/27)

Transcription

1 Lecture Topics Today: Data and Control Hazards (P&H ) Next: continued 1 Announcements Exam #1 returned Milestone #5 (due 2/27) Milestone #6 (due 3/13) 2 1

2 Review: Pipelined Implementations Pipelining improves performance by increasing instruction throughput Executes multiple instructions in parallel Each instruction has the same latency Instruction set design affects complexity of pipeline implementation Subject to hazards Structural, data, control 3 MIPS Pipelined Implementation Five stages in the pipeline Clock cycle long enough to handle work which must be completed in one stage Every instruction uses all 5 stages (but no work done in some stages for some instructions) Overlap execution: different instructions in each of the 5 stages simultaneously 4 2

3 MIPS Pipelined Implementation Classic five-stage model: IF: Fetch instruction from memory ID: Decode instruction and read registers EX: Execute operation or calculate address MEM: Access memory operand WB: Write result back to register 5 MIPS Pipelined Implementation Pipeline registers capture results at end of stages All instructions forced into same framework 6 3

4 Example Sequence of five MIPS instructions: 7 8 4

5 Pipeline Hazards Situations where there are conflicts between two instructions in the pipeline are called hazards Three categories: Structural hazards Data hazards Control hazards 9 Structural Hazards A structural hazard occurs when the datapathdoes not contain the necessary resources to perform two operations at the same time Solution: add resources to the datapath (perhaps by replicating existing resources) Examples: split I-cache and D-cache, multiple adder circuits 10 5

6 Data Hazards A data hazard occurs when the result of one instruction is an input to the next instruction Solution: freeze early stages of the pipeline (stall the pipeline) Solution in some cases: use data forwarding 11 Control Hazards Control transfer instructions create control hazards (branch hazards) in the pipeline The target address is not available until after at least one other instruction has entered the pipeline Handled by rearranging the pipeline and stalling the pipeline as needed 12 6

7 Overview: Data Hazards Ex: second instruction dependent on first: add $s0, $t0, $t1 sub $t2, $s0, $t3 Old value of $s0 13 Delay for two clock ticks: add $s0, $t0, $t1 nop nop sub $t2, $s0, $t3 14 7

8 Pipeline Bubbles Cause needed delays by inserting bubbles into the pipeline (cycles when no useful work is done in some stage) Several strategies for inserting bubbles Programmer required to insert no-ops Assembler inserts no-ops Hardware freezes early stages and converts "nullified" instructions into no-ops 15 Hardware inserts two bubbles: add $s0, $t0, $t1 sub $t2, $s0, $t3 16 8

9 Forwarding (Bypassing) Required value is sometimes available earlier in the pipeline Add pathways to forward the value 17 Load-Use Data Hazards Second instruction dependent on value loaded from memory by first instruction: lw $s0, 20 ($t1) sub $t2, $s0, $t3 Called a load-use data hazard 18 9

10 Required value is available after the MEM stage, so stall pipeline for one cycle and user forwarding (another new pathway) 19 Data Hazards in ALU Instructions Consider this sequence: sub $2, $1, $3 and $12, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2) Hazards can be resolved with forwarding Additional logic to detect when to forward 20 10

11 Dependencies & Forwarding 21 Detecting the Need to Forward Pass register numbers along pipeline: ID/EX.RegisterRs = Rsregister number in ID/EX pipeline register EX/MEM.RegisterRd = Rd register number in EX/MEM pipeline register ALU operand register numbers in EX stage: ID/EX.RegisterRs ID/EX.RegisterRt 22 11

12 Data hazard when: 1a. EX/MEM.RegisterRd = ID/EX.RegisterRs 1b. EX/MEM.RegisterRd = ID/EX.RegisterRt 2a. MEM/WB.RegisterRd = ID/EX.RegisterRs 2b. MEM/WB.RegisterRd = ID/EX.RegisterRt From the example: sub $2, $1, $3 and $12, $2, $5 or $13, $6, $2 23 Forward from EX/MEM pipeline register to resolve 1a and 1b Forward from MEM/WB pipeline register to resolve 2a and 2b But only if forwarding instruction will write to a register And only if destination register for that instruction is not $

13 Forwarding Paths 25 Forwarding Conditions EX hazard if (EX/MEM.RegWrite and (EX/MEM.RegisterRd 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) ForwardA = 10 if (EX/MEM.RegWrite and (EX/MEM.RegisterRd 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) ForwardB =

14 Forwarding Conditions MEM hazard if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = Double Data Hazard Consider the sequence: add $1, $1, $2 add $1, $1, $3 add $1, $1, $4 Both hazards occur: use the most recent value Revise MEM hazard condition: only forward if EX hazard condition is not true 28 14

15 MEM hazard if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0) and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = MEM hazard if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0) and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB =

16 Datapath with Forwarding 31 Load-Use Data Hazards Need to stall for one cycle 32 16

17 Load-Use Hazard Detection Check when instruction which uses the result is decoded in ID stage ALU operand register numbers in ID stage are IF/ID.RegisterRs, IF/ID.RegisterRt From the example: lw $2, 20($1) and $4, $2, $5 33 Load-Use Hazard Detection Load-use hazard when ID/EX.MemRead and ((ID/EX.RegisterRt = IF/ID.RegisterRs) or (ID/EX.RegisterRt = IF/ID.RegisterRt)) If detected, stall and insert bubble into the pipeline 34 17

18 Stalling the Pipeline Force control signals in ID/EX register to 0 instruction becomes no-op as instruction advances through pipeline, next 3 stages (EX, MEM and WB) will do nothing Prevent update of PC and IF/ID register Instruction with hazard is decoded again Following instruction is fetched again 35 Stall/Bubble in the Pipeline Stall inserted here 36 18

19 Stall/Bubble in the Pipeline Or, more accurately 37 Datapath with Hazard Detection 38 19

20 Stalls and Performance Stalls reduce performance, but are required to get correct results Compiler, assembler and/or programmer can arrange code to avoid hazards and stalls Re-arrange instructions without changing the meaning of the program Requires knowledge of the pipeline structure 39 Code Scheduling to Avoid Stalls Reorder code to avoid use of load result in the next instruction stall stall lw $t1, 0($t0) lw $t2, 4($t0) add $t3, $t1, $t2 sw $t3, 12($t0) lw $t4, 8($t0) add $t5, $t1, $t4 sw $t5, 16($t0) 13 cycles lw $t1, 0($t0) lw $t2, 4($t0) lw $t4, 8($t0) add $t3, $t1, $t2 sw $t3, 12($t0) add $t5, $t1, $t4 sw $t5, 16($t0) 11 cycles 40 20