ECE 313 Computer Organization FINAL EXAM December 14, This exam is open book and open notes. You have 2 hours.

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Anastasia Morton
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1 This exam is open book and open notes. You have 2 hours. Problems 1-5 refer to the following: We wish to add a new R-Format instruction to the MIPS Instruction Set Architecture called l_inc (load and increment). The assembly language form of l_inc and its register transfers are shown below: Assembly language: l_inc rt, offset(rs) Register Transfers Reg[rt] <- Mem[ Reg[rs] + sign_extend(offset)]; Reg[rs] <- Reg[rs] + 4; 1. Assembly Language 5 Points List two MIPS assembly language instructions which perform the same function as the l_inc instruction when executed together. 2. Instruction Set Design 5 Points Describe a scenario where the l_inc instruction would be useful. Page 1 of 8

2 3. Multicycle Processor Design 20 Points (a) Modify the multicycle processor design to efficiently implement the l_inc instruction. Mark changes on the state diagram below and the datapath diagram on the next page. (b) How much faster is the execution of the l_inc instruction in your modified design than the execution of the two instructions you listed in problem 1? Page 2 of 8

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4 4. Pipelined Processor Design 20 Points Assume that the register file is modified to add a second write port, with inputs WN2 (selects the register to be written), WD2 (write data), and RegWrite2 (write enable). Modify the pipelined processor datapath and control to implement the l_inc instruction. (a) Mark any changes to the datapath (including any additional hardware that you need) on the diagram on the next page. In addition, show all control outputs in the table below: Instr. l_inc Reg Dst ALU Op1 EX Stage Control Lines ALU Op0 ALU Src Branch MEM Stage Control Lines Mem Read Mem Write Reg Write WB Stage Control Lines Memto Reg (b) Suppose that an additional write port cannot be added to the register file. Briefly describe how the l_inc instruction could still be implemented with the pipelined design. What impact would this change have on performance? Page 4 of 8

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6 5. Data and Control Hazards 20 Points Assume that the following sequence of MIPS instructions (including the new l_inc instruction) is executing on the modified pipeline design from Problem 3, but that the design is altered to perform forwarding, stalls, and flushing as required to deal with data and control hazards. L: l_inc $2, 200($1) bne $1, $5, L add $7, $1, $4 sw $8, 0($7) sub $7, $8, $7 (a) Circle any data dependencies which exist between these instructions. (b) Mark any of the above instructions that will be stalled due to data hazards. (c) Assuming that the branch is taken, fill in the multicycle diagram shown below to show the execution of the instruction sequence during one iteration, including stalls, forwarding, and flushes (if any). Shade active stages. Page 6 of 8

7 6. Short Answers 10 Points Provide a short answer for each of the following questions: (a) List three features of the Intel IA-32 (x86) Instruction Set Architecture that make it difficult to implement. (b) List three different types of exceptions which can occur in a full implementation of the MIPS Instruction Set Architecture. (c) List two reasons why Virtual Memory is used in almost all modern computer systems. (d) How many levels of on-chip cache are common in current desktop computer systems? Page 7 of 8

8 7. Cache Memories 20 Points The diagram below shows a direct-mapped cache memory design which contains 16 blocks. Each block stores one 32-bit word plus tag and valid bit. (a) How many bits will there be in the Index field of the address? (b) How many bits will there be in the Tag field of each address? (c) How many bits of storage will be required for this cache memory? (d) Assume that the is initially empty (i.e. a cold cache). Fill in the chart below to show the hits and misses encountered for each 32-bit word reference. Also, write the cache contents in the diagram as the cache is updated. Hit Tag Data Reference (word offset) Hit/Miss Tag V Tag Index Byte Offset 32 Bits Data Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 Block 7 Block 8 Block 9 Block 10 Block 11 Block 12 Block 13 Block 14 Block = Page 8 of 8

ECE 313 Computer Organization FINAL EXAM December 13, 2000

ECE 313 Computer Organization FINAL EXAM December 13, 2000 This exam is open book and open notes. You have until 11:00AM. Credit for problems requiring calculation will be given only if you show your work. 1. Floating Point Representation / MIPS Assembly Language