TDT 4260 TDT ILP Chap 2, App. C

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1 TDT 4260 ILP Chap 2, App. C

2 Intro Ian Bratt ntnu no)

3 Instruction level parallelism (ILP) A program is sequence of instructions typically written to be executed one after the other Poor usage of CPU resources! (Why?) Better: Execute instructions in parallel 1: Pipeline Partial overlap of instruction execution 2: Multiple issue Total overlap of instruction execution Today: Pipelining and multi-issue issue (if time)

4 Pipelining i (1/3)

5 Pipelining (2/3) Multiple different stages executed in parallel Laundry in 4 different stages Fetch / Execute / Store Assumptions: Task can be split into stages Storage of temporary data Stages synchronized Next operation known before last finished?

6 Pipelining (3/3) Good Utilization: The whole CPU is always in use Fetch unit, decoder, ALU,... Great usage of CPU resources! Most common form of ILP, used everywhere CPU, GPU, digital circuits,... Ideal: time_stage = time_instruction / stages But stages are not perfectly balanced But transfer between stages takes time But pipeline may have to be emptied...

7 Example: MIPS64 (1/2) RISC Load/store Few instruction formats Fixed instruction length 64-bit DADD = 64 bits ADD LD = 64 bits L(oad) 32 registers (R0 = 0) EA = offset(ister) Pipeline IF: Instruction fetch ID: Instruction decode / register fetch EX: Execute / effective address (EA) MEM: Memory access WB: Write back (reg)

8 Example: MIPS64 (2/2) Time (clock cycles) I n s t r. Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Ifetch Ifetch ALU DMem ALU DMem O r d e r Ifetch Ifetch ALU DMem ALU DMem

9 Big Picture: What are some real world examples of pipelining? Why do we pipeline? p Does pipelining increase or decrease instruction throughput? Does pipelining increase or decrease instruction latency?

10 Big Picture (continued): Computer Architecture is the study of design tradeoffs!!!! There is no philosophy p of architecture and no perfect architecture. This is engineering, not science. What are the costs of pipelining? For what types of devices is pipelining not a good choice?

11 Improve speedup? Why not perfect speedup? Sequential programs One instruction dependent on another Not enough CPU resources What can be done? Forwarding (HW) Scheduling (SW / HW) Prediction (SW / HW) Both hardware (dynamic) and compiler (static) can help

12 Dependencies and hazards Dependencies Parallel instructions can be executed in parallel Dependent instructions are not parallel I1: DADD R1, R2, R3 I2: DSUB R4, R1, R5 Property of the instructions Hazards Situation where a dependency causes an instruction to give a wrong result Property of the pipeline Not all dependencies give hazards Dependencies must be close enough in the instruction stream to cause a hazard

13 Dependencies (True) data dependencies One instruction reads what an earlier has written Name dependencies Two instructions use the same register / mem loc But no flow of data between them Two types: Anti and output dependencies Control dependencies Instructions dependent on the result of a branch Again: Independent d of pipeline implementation ti

14 Hazards Data hazards Overlap will give different result from sequential RAW / WAW / WAR Control hazards Branches Ex: Started executing the wrong instruction Structural hazards Pipeline does not support this combination of instr. Ex: ister with one port, two stages want to read

15 Data dependency d Hazard? Figure A.6, Page A-16 IF ID/RF EX MEM WB I Ifetch add r1,r2,r3 n s t r. sub r4,r1,r3r1 r3 Ifetch ALU DMem ALU DMem O r d e r and r6,r1,r7 or r8,r1,r9 xor r10,r1,r11 Ifetch Ifetch ALU Ifetch DMem ALU DMem ALU DMem

16 Data Hazards (1/3) Read After Write (RAW) Instr J tries to read operand before Instr I writes it I: add r1,r2,r3, J: sub r4,r1,r3 Caused by a true data dependency This hazard results from an actual need for communication.

17 Data Hazards (2/3) Write After Read (WAR) Instr J writes operand before Instr I reads it I: sub r4,r1,r3 J: add r1,r2,r3 Caused by an anti dependency This results from reuse of the name r1 Can t happen in MIPS 5 stage pipeline because: All instructions take 5 stages, and Reads are always in stage 2, and Writes are always in stage 5

18 Data Hazards (3/3) Write After Write (WAW) Instr J writes operand before Instr I writes it. I: sub r1,r4,r3 J: add r1,r2,r3 Caused by an output dependency Can t happen in MIPS 5 stage pipeline because: All instructions take 5 stages, and Writes are always in stage 5 WAR and WAW can occur in more complicated pipes

19 Forwarding Figure A.7, Page A-18 IF ID/RF EX MEM WB I Ifetch add r1,r2,r3 n s t r. sub r4,r1,r3r1 r3 Ifetch ALU DMem ALU DMem O r d e r and r6,r1,r7 or r8,r1,r9 xor r10,r1,r11 Ifetch Ifetch ALU Ifetch DMem ALU DMem ALU DMem

20 Structural Hazards (Memory Port) Figure A.4, Page A-14 Time (clock cycles) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 I n s t r. O r d e r Load Ifetch Instr 1 Instr 2 Instr 3 Instr 4 Ifetch ALU Ifetch DMem ALU Ifetch DMem AL LU Ifetch DMem ALU DMem ALU DMem

21 Hazards, Bubbles (Similar il to Figure A.5, Page A-15) Time (clock cycles) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Ifetch I Load n s t r. Instr 1 ALU Ifetch Instr 2 Ifetch O r DMem ALU DMem ALU DMem d Stall Bubble Bubble Bubble Bubble Bubble e r Ifetch Instr 3 ALU DMem How do you bubble the pipe? How can we avoid this hazard?

22 Control hazards (1/2) Sequential execution is predictable, (conditional) branches are not May have fetched instructions that should not be executed Simple solution (figure): Stall the pipeline p (bubble) Performance loss depends on number of branches in the program and pipeline implementation Branch penalty Possibly wrong instruction Correct instruction

23 Control hazards (2/2) What can be done? Always stop (previous slide) Also called freeze or flushing of the pipeline Assume no branch (=assume sequential) Must not change state before branch instr. is complete Assume branch Only smart if the target address is ready early Delayed branch Execute a different instruction while branch is evaluated Static techniques (fixed rule or compiler)

24 Dynamic scheduling So far: Static scheduling Instructions executed in program order Any reordering is done by the compiler Dynamic scheduling CPU reorders to get a more optimal order Fewer hazards, fewer stalls,... Must preserve order of operations where reordering could change the result Covered by TDT 4255 Hardware design

25 25 Dataflow execution edu/6.823 October 19, 2011 Ins# use exec op p1 src1 p2 src2 ptr 2 next to deallocate t 1 t 2... prt 1 next available Reorder buffer t n Instruction slot is candidate for execution when: It holds a valid instruction ( use bit is set) It has not already started execution ( exec bit is clear) Both operands are available (p1 and p2 are set)

26 Renaming & Out-of-order Issue October 19, 2011 edu/6.823 An example Renaming table p data F1 F2 v1 t1 F3 F4 t2 t5 F5 F6 t3 F7 F8 v4 t4 Reorder buffer Ins# use exec op p1 src1 p2 src LD LD MUL 10 v2 t2 1 v SUB 1 v1 1 v DIV 1 v1 01 t4 v4 t 1 t 2 t 3 t 4 t data / t i 1 LD F2, 34(R2) 2 LD F4, 45(R3) When are names in sources 3 MULTD F6, F4, F2 replaced by data? 4 SUBD F8, F2, F2 Whenever an FU produces data 5 DIVD F4, F2, F8 When can a name be reused? 6 ADDD F10, F6, F4 Whenever an instruction completes

27 Compiler techniques for ILP For a given pipeline and superscalarity How can these be best utilized? As few stalls from hazards as possible Dynamic scheduling Tomasulo s algorithm etc. (TDT4255) Makes the CPU much more complicated What can be done by the compiler? Has ages to spend, but less knowledge Static ti scheduling, but what else?

28 Example Source code: for (i = 1000; i >0; i=i-1) x[i] = x[i] + s; Notice: Lots of dependencies No dependencies between iterations High loop overhead Loop unrolling MIPS: Loop: LD L.D F0,0(R1) ; F0 = x[i] ADD.D F4,F0,F2 ; F2 = s S.D F4,0(R1) ; Store x[i] + s DADDUI R1,R1,#-8 ; x[i] is 8 bytes BNE R1,R2,Loop ; R1 = R2?

29 Static scheduling Loop: L.D stopp ADD.D stopp stopp S.D DADDUI stopp BNE F0,0(R1) F4,F0,F2 F4,0(R1) R1,R1,#-8 R1,R2,Loop Loop: L.D DADDUI ADD.D stopp stopp S.D BNE F0,0(R1) R1,R1,#-8 F4,F0,F2 F4,8(R1) R1,R2,Loop Result: From 9 cycles per iteration to 7 (Delays from table in figure 2.2)

30 Loop unrolling Loop: LD L.D F0,0(R1) 0(R1) ADD.D F4,F0,F2 S.D F4,0(R1) Loop: L.D F0,0(R1) L.D F6,-8(R1) ADD.D F4,F0,F2 ADD.D F8,F6,F2 SD S.D F4,0(R1) S.D F8,-8(R1) DADDUI R1,R1,#-8 L.D F10,-16(R1) BNE R1,R2,Loop R2 ADD.D D F12,F10,F2 F10 F2 S.D F12,-16(R1) L.D F14,-24(R1) 4( Reduced d loop overhead ADD.D F16,F14,F2 Requires number of iterations S.D F16,-24(R1) divisible by n (here n=4) DADDUI R1,R1,#-32 ister renaming BNE R1,R2,Loop Offsets have changed Stalls not shown

31 Loop: LD L.D F0,0(R1) 0(R1) Loop: LD L.D F0,0(R1) 0(R1) ADD.D F4,F0,F2 L.D F6,-8(R1) S.D F4,0(R1) L.D F10,-16(R1) L.D F6,-8(R1) L.D F14,-24(R1) ADD.D F8,F6,F2 ADD.D F4,F0,F2 SD S.D F8,-8(R1) 8(R ADD.DD F8,F6,F2F6 F L.D F10,-16(R1) ADD.D F12,F10,F2 ADD.DD F12,F10,F2F10 F2 ADD.DD F16,F14,F2F14 F2 S.D F12,-16(R1) S.D F4,0(R1) L.D F14,-24(R1) S.D F8,-8(R1) ADD.D F16,F14,F2 DADDUI R1,R1,#-32 S.D F16,-24(R1) S.D F12,-16(R1) DADDUI R1,R1,#-32R SD S.D F6 F16,-24(R1) BNE R1,R2,Loop BNE R1,R2,Loop Avoids stall after: L.D(1), ADD.D(2), DADDUI(1)

32 Loop unrolling: Summary Original code Scheduling Loop unrolling Unrolled 4 iterationsti Combination Avoids stalls entirely 9 cycles per element 7 cycles per element 6,75 cycles per element 3,5 cycles per element Compiler reduced execution time by 61%

33 Loop unrolling in practice Do not usually know upper bound of loop Suppose it is n, and we would like to unroll the loop to make k copies of the body Instead of a single unrolled loop, we generate a pair of consecutive loops: 1st executes (nmod k) times and has a body that t is the original loop 2nd is the unrolled body surrounded by an outer loop that iterates (n/k) times For large values of n, most of the execution time will be spent in the unrolled loop

34 Getting CPI below 1 CPI 1 if issue only 1 instruction ti every clock cycle Multiple-issue processors come in 3 flavors: 1. Statically-scheduled l d superscalar processors In-order execution Varying number of instructions i issued (compiler) 2. Dynamically-scheduled superscalar processors Out-of-order execution Varying number of instructions issued (CPU) 3. VLIW (very long instruction i word) processors In-order execution Fixed number of instructions ti issued

35 VLIW: Very Large Instruction Word (1/2) Each VLIW has explicit coding for multiple operations Several instructions combined into packets Possibly with parallelism indicated Tradeoff instruction space for simple decoding Room for many operations Independent operations => execute in parallel E.g., 2 integer operations, 2 FP ops, 2 Memory refs, 1 branch

36 VLIW: Very Large Instruction Word (2/2) Assume 2 load/store, 2 fp, 1 int/branch VLIW with 0-5 operations. Why 0? Important to avoid empty instruction slots Loop unrolling Local scheduling Global scheduling Scheduling across branches Difficult to find all dependencies in advance Solution1: Block on memory accesses Solution2: CPU detects some dependencies

37 Recall: Unrolled Loop that minimizes stalls for Scalar Source code: for (i = 1000; i >0; i=i-1) x[i] = x[i] + s; Loop: LD L.D F0,0(R1) 0(R1) L.D F6,-8(R1) L.D F10,-16(R1) L.D F14,-24(R1) ADD.D F4,F0,F2 ADD.DD F8,F6,F2F6 F ADD.D F12,F10,F2 ADD.DD F16,F14,F2F14 F2 S.D F4,0(R1) S.D F8,-8(R1) DADDUI R1,R1,#-32 S.D F12,-16(R1) SD F6 (R ) BNE R1,R2,Loop ister mapping: S.D F16,-24(R1) s F2 i R1

38 Loop Unrolling in VLIW Memory Memory FP FP Int. op/ Clock reference 1 reference 2 operation 1 op. 2 branch L.D F0,0(R1) L.D F6,-8(R1) 1 L.D F10,-16(R1) L.D F14,-24(R1) 2 L.D F18,-32(R1) L.D F22,-40(R1) ADD.D F4,F0,F2 ADD.D F8,F6,F2 3 L.D F26,-48(R1) ADD.D F12,F10,F2 ADD.D F16,F14,F2 4 ADD.D F20,F18,F2 ADD.D F24,F22,F2 5 S.D 0(R1),F4 S.D -8(R1),F8 ADD.D F28,F26,F2 6 S.D -16(R1),F12 S.D -24(R1),F16 7 SD S.D -32(R1),F20 SD S.D -40(R1),F24 DSUBUI R1,R1,#48R 8 S.D -0(R1),F28 BNEZ R1,LOOP 9 Unrolled 7 iterations to avoid delays 7 results in 9 clocks, or 1.3 clocks per iteration (1.8X) Average: 2.5 ops per clock, 50% efficiency Note: Need more registers s in VLIW (15 vs. 6 in SS)

39 Problems with 1st Generation VLIW Increase in code size Loop unrolling Partially empty VLIW Operated in lock-step; no hazard detection HW A stall in any functional unit pipeline causes entire processor to stall, since all functional units must be kept synchronized Compiler might predict function units, but caches hard to predict Binary code compatibility Strict VLIW => different numbers of functional units and unit latencies require different versions of the code

40 IA-64 and EPIC 64 bit instruction set architecture Not a CPU, but an architecture Itanium and Itanium 2 are CPUs based on IA-64 Made by Intel and Hewlett-Packard Uses EPIC: Explicitly Parallel Instruction Computing Departure from the x86 architecture Details in Appendix G.6

41 Instruction bundle (VLIW)

42 Functional units and template Functional units: I (Integer), M (Integer + Memory), F (FP), B (Branch), L + X (64 bit operands + special inst.) Template field: Maps instruction to functional unit Indicates stops: Limitations to ILP

43 Code example (1/2)

44 Code example 2/2

45 Instruction fetching Want to issue >1 instruction every cycle This means fetching >1 instruction Eg E.g. 4-8 instructions fetched every cycle Several problems Bandwidth / Latency Determining which instructions Jumps Branches Integrated instruction fetch unit

46 Branch Target Buffer (BTB) Predicts next instruction address, sends it out before decoding instruction PC of branch sent to BTB When match is found, Predicted PC is returned If branch predicted taken, instruction fetch continues at Predicted PC

47 Return Address Predictor Small buffer of 70% return addresses acts 60% as a stack Caches most 50% recent return 40% addresses Call Push a 30% return address 20% on stack Return Pop an address off stack & predict as new PC Mispre ediction freque ency 10% 0% go m88ksim cc1 compress xlisp ijpeg perl vortex Return address buffer entries

48 Integrated Instruction Fetch Units Recent designs have implemented the fetch stage as a separate, autonomous unit Multiple-issue in one simple pipeline stage is too complex An integrated fetch unit provides: Branch prediction Instruction prefetch Instruction memory access and buffering

49 Limits to ILP Chapter 3 Advances in compiler technology + significantly new and different hardware techniques may be able to overcome limitations assumed in studies However, unlikely such advances when coupled with realistic hardware will overcome these limits in near future How much ILP is available using existing mechanisms with increasing HW budgets?

50 Ideal HW Model 1. ister renaming infinite virtual registers all register WAW & WAR hazards are avoided 2. Branch prediction perfect; no mispredictions 3. Jump prediction all jumps perfectly predicted 2 & 3 no control dependencies; perfect speculation & an unbounded d buffer of instructions ti available 4. Memory-address alias analysis addresses known & a load can be moved before a store provided addresses not equal 1&4 eliminates all but RAW 5. perfect caches; 1 cycle latency for all instructions; unlimited instructions issued/clock cycle

51 Upper Limit it to ILP: Ideal Machine (Figure 3.1) Instr ructio ons Per Cl lock Integer: FP: gcc espresso li fpppp doducd tomcatv Programs

52 Instruction window Ideal HW need to know entire code Obviously not practical ister dependencies scales quadratically Window: The set of instructions examined for simultaneous execution How does the size of the window affect IPC? Too small window => Can t see whole loops Too large window => Hard to implement

53 More Realistic HW: Window Impact Figure 3.2 FP: Clock IPC Instructi ions Per Integer: gcc espresso li f pppp doduc tomcatv Inf inite

54 Questions?

55 Thread Level Parallelism (TLP) ILP exploits implicit parallel operations within a loop or straight-line code segment TLP explicitly represented by the use of multiple threads of execution that are inherently parallel Use multiple instruction streams to improve: 1. Throughput of computers that run many programs 2. Execution time of a single application implemented as a multi-threaded t poga program (paa (parallel poga program)

56 Multi-threaded execution Multi-threading: multiple threads share the functional units of 1 processor via overlapping Must duplicate independent state of each thread e.g., a separate copy of register file, PC and page table Memory shared through virtual memory mechanisms HW for fast thread switch; much hfaster than full process switch 100s to 1000s of clocks When switch? Alternate instruction per thread (fine grain) When a thread is stalled, perhaps for a cache miss, another thread can be executed (coarse grain)

57 Fine-Grained Multithreading Switches between threads on each instruction Multiples threads interleaved Usually round-robin fashion, skipping stalled threads CPU must be able to switch threads every clock Hides both short and long stalls Other threads executed when one thread stalls But slows down execution of individual threads Thread ready to execute without stalls will be delayed by instructions from other threads Used on Sun s Niagara

58 Coarse-Grained Multithreading Switch threads only on costly stalls (L2 cache miss) Advantages No need for very fast thread-switching Doesn t slow down thread, since switches only when thread encounters a costly stall Disadvantage: hard to overcome throughput losses from shorter stalls, due to pipeline start-up costs Since CPU issues instructions from 1 thread, when a stall occurs, the pipeline must be emptied or frozen New thread must fill pipeline before instructions can complete => Better for reducing gpenalty of high cost stalls, where pipeline refill << stall time

59 Do both ILP and TLP? TLP and ILP exploit two different kinds of parallel structure in a program Can a high-ilp processor also exploit TLP? Functional units often idle because of stalls or dependences in the code Can TLP be a source of independent instructions that might reduce processor stalls? Can TLP be used to employ functional units that would otherwise lie idle with insufficient ILP? => Simultaneous Multi-threading (SMT) Intel: Hyper-Threading

60 Simultaneous Multi-threadingthreading Cycle One thread, 8 units M M FX FX FP FP BR CC Cycle Two threads, 8 units M M FX FX FP FP BR CC M = Load/Store, FX = Fixed Point, FP = Floating Point, BR = Branch, CC = Condition Codes

61 Simultaneous Multi-threading (SMT) A dynamically scheduled d processor already has many HW mechanisms to support multi-threading Large set of virtual registers Virtual = not all visible at ISA level ister renaming Dynamic scheduling Just add a per thread renaming table and keeping separate PCs Independent commitment can be supported by logically keeping a separate reorder buffer for each thread

62 Time (proc cessor cycle e) Multi-threaded th d categories Simultaneous Superscalar Fine-Grained Coarse-Grained Multiprocessing Multithreading Thread 1 Thread 3 Thread 5 Thread 2 Thread 4 Idle slot

63 Design Challenges in SMT SMT makes sense only with fine-grained implementation How to reduce the impact on single thread performance? Give priority to one or a few preferred threads Large register file needed to hold multiple contexts Not affecting clock cycle time, especially in Instruction issue - more candidate instructions need to be considered Instruction ti completion -choosing which h instructions ti to commit may be challenging Ensuring that cache and TLB conflicts generated by SMT do not degrade performance

TDT 4260 lecture 7 spring semester 2015

1 TDT 4260 lecture 7 spring semester 2015 Lasse Natvig, The CARD group Dept. of computer & information science NTNU 2 Lecture overview Repetition Superscalar processor (out-of-order) Dependencies/forwarding