Part 1 (70% of grade for homework 2): MIPS Programming: Simulating a simple computer

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1 CS Homework 2 Fall 2016 Profs. Daniel A. Menasce and Yutao Zhong Team Allowed: maximum of two per team. State clearly team member names and GMU IDs as comments in source code and each page of submitted report. Late submissions are not accepted. How to submit: A zip file answering all questions from Parts 1 and 2. The submission will be made via a blackboard link available to you. For team projects, only one member of the team should submit the zip file and the other should submit a one-page PDF file stating the names of both members of the team. Part 1 (70% of grade for homework 2): MIPS Programming: Simulating a simple computer Consider a simple computer SIMPCOMP with the following characteristics: Word size: 16 bits Sixteen 16-bit general registers numbered from 0 to 15. Register 0 contains the value zero and cannot be overwritten. All instructions are two bytes long. The most significant byte of an instruction (i.e., bits 15-8) are stored in the lower addressed byte of the instruction. For example, consider an instruction stored at bytes 0016 and Bits 15-8 are stored at address 0016 and bits 7-0 at address 0116 An 8-bit Program Counter (PC). The PC is incremented by 2 except in the case a branch is taken. An 8-bit Data Pointer (DP) register that contains the address of the first byte in memory used for data. An 8-bit End Data Pointer (EDP) that contains the address of the last word that contains data for a program. Programs in SIMPCOMP are always loaded at address 0016 Main memory has 256 bytes with addresses ranging from 0016 to FF16 Bytes of every instruction is the opcode determined by the table below = 016 Add 2 =116 Subtract = 216 Multiply 00112= 316 Divide = 416 Load word = 516 Store word = 616 Branch on equal = 716 Branch on not equal = 816 Unconditional jump = 916 Store immediate Page 1 of 5

2 10102 = A16 Print = B16 Halt Arithmetic instructions have the following additional fields: R1 (bits 11-8), R2 (bits 7-4), and R3 (bits 3-0). R1, R2 and R3 are register numbers. The registers whose numbers are in R2 and R3 contain the source operands and the register whose number is in R1 contains the destination register. For example, the add instruction adds the content of R2 to the content of R3 and stores the result in R1. The sub operation does R1 <- c[r2] c[r3] and the divide operation does R1 <- c[r2] / c[r3]. The contents of registers are considered signed numbers in 2 s complement. The load/store word instructions have the following additional fields: R1 (bits 11-8) and Memory Address (bits 7-0). The jump instruction has a Memory Address field (bits 7-0) that points to the address of an instruction (i.e., to the most significant byte of the instruction) The branch on equal and branch on not equal instructions have the following additional fields R1 (bits 11-8), R2 (bits 7-4), and Offset (bits 3-0). Offset is an unsigned number and is added to the address of the branch instruction in case the branch occurs to determine the address of the next instruction to be executed. The store immediate instruction has the following additional fields: Constant (bits 11-8) and Memory Address field (bits 7-0). This instruction stores the 1-byte Constant into memory at the word starting at Memory Address. But, before storing, the sign of the constant is extended so that the 4-bit constant becomes a full word (i.e., 16 bits). This is done by replicating bit 11 of the instruction into bits 15-4 of the sign extended constant. The print instruction has the following additional field: R1 (bits 11-8). This instruction prints the content of the register whose number is in R1. The Halt instruction stops the execution of the program. You need to write a procedure called SIMPCOMP that receives as arguments the contents of the Data Pointer register and of the End Data Pointer Register and returns a Result according to the table below. The program execution should be stopped for return codes > 0. Return Code Description 0 Normal program execution 1 Jump or Branch to an illegal address (i.e., either in the data area, outside of the memory bounds, or not aligned with a word boundary) 2 Illegal address for a load or store (including store immediate) instruction (these instructions can only load/store from/into the data area) 3 Illegal opcode 4 Overflow or underflow in an arithmetic operation Page 2 of 5

3 You need to write a MIPS program that (1) reads the input program, (2) prints the memory content after the program with the data is initially loaded into memory (one line per memory word in the format <address in hexadecimal> <word content>), and (3) invokes the SIMPCOMP procedure to execute the program and print the return code. Your program will read the program in hexadecimal, one instruction per line, and store it in main memory starting at address After the program instructions, you will find a line with the word. This indicates that data words in hexadecimal follow, one per line. These data words have to be stored in memory immediately following the program. The end of data words is indicated in the input by the word. See the following example input. 450A 480C 0258 A A The five instructions of the program above would be stored into addresses 0016 to 0816 and the values 1010 and 510 into addresses 0A16 to 0C16. The values of the Data Pointer and End Data Pointer registers are 0A16 and 0C16, respectively. The program displays 15 when executed. Execute the following SIMPCOMP programs for the following input and display the result: Program 1 Program 2 Program 3 Program 4 Program A 0006 C224 Page 3 of 5

4 What is the general function of program 1 above? Clearly indicate in comments at the top of the procedure SIMPCOMP where SIMPCOMP s memory, general registers, Program Counter, and Data Pointer are simulated. Part 2 (30% of grade for homework 2): Exercises related to chapter (10 pts) The instructions below are not included in the MIPS real instruction set: 1) inci rs, imm # imm is an immediate operand, rs = rs + imm 2) orn rd, rs, rt # rd = bitwise OR of rs and (not rt) 3) bgt rs, rt, L1 # branch to label L1 if rs>rt; # otherwise advance to the next instruction Provide the shortest sequences of MIPS instructions that implement these instructions. You are NOT allowed to use pseudo-instructions in your answer. Do not change any register other than the destination register. You can use $at to hold temporary values. 2. (10 pts) Consider the following MIPS code: Loop: slt $t2, $0, $t1 beq $t2, $0, DONE addi $t1, $t1, -1 addi $s2, $s2, 3 j Loop Done: 1) Write an equivalent C code for the given MIPS code, assuming registers $t1 and $s2 are integers i and A respectively. 2) If register $t1 is initialized as value N, $s2 is initialized as zero, how many MIPS instructions are executed? What will be the final value of $t1 and $s2? 3. (5 pts) Translate function f into MIPS assembly language following the calling conventions discussed in the textbook. Assume the function declaration of func is int func(int a, int b);. The code for function f is as follows: int f (int a, int b, int c){ return func(func(b,c), func(b,a)) } 4. (5 pts) If the current value of the PC is 0x while the target address is 0x ) Can you use a single MIPS branch instruction to get to the target instruction from current PC? 2) Can you use a single MIPS jump instruction to get to the target instruction from current PC? Show your calculations to justify your answer. Deliverables for homework 2: Page 4 of 5

5 A zip file containing: o For part 1: Your source code file: SIMPCOMP_ZZZ.asm where ZZZ is your "last names combined". Do not submit PDF of the MIPS programs, just an.asm file! As in all programming assignments, your code must be very well commented. o For part 1: The output as a PDF file for the inputs indicated above. File name: SIMPCOMP_output_ZZZ.pdf. o For part 2: A pdf file with your answers. File name: Part2_ ZZZ.pdf Page 5 of 5