EEM870 Embedded System and Experiment Lecture 4: ARM Instruction Sets

Transcription

1 EEM870 Embedded System and Experiment Lecture 4 ARM Instruction Sets Wen-Yen Lin, Ph.D. Department of Electrical Engineering Chang Gung University wylin@mail.cgu.edu.tw March 2014

2 Introduction Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 2

3 Operations of the Computer Hardware ~ Arithmetic Add and subtract, have 3 operands Two sources and one destination Operand order is fixed (destination first) Example C code a = b + c ARM code ADD a, b, c (MIPS also has the similar form, we ll talk about registers in a bit) All arithmetic operations have this form The natural number of operands for an operation like addition is three requiring every instruction to have exactly three operands, no more and no less, conforms to the philosophy of keeping the hardware simple Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 3

4 Operations of the Computer Hardware ~ Arithmetic Design Principle 1 simplicity favors regularity. Regularity makes implementation simpler Simplicity enables higher performance at lower cost Of course this complicates some things... C code a = b + c + d; ARM code ADD a, b, c ADD a, a, d Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 4

5 Example - C Assignment Statement into ARM C Language a = b + c; d = a e; f = (g + h) (i + j); Compiler ARM Assembly Language ADD a, b, c SUB d, a, e ADD t0, g, h //temp variable t0=g+h ADD t1, i, j //temp variable t1=i+j SUB f, t0, t1 //f=t0-t1=(g+h)-(i+j) Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 5

6 Operands of the Computer Hardware Arithmetic instructions use register operands Registers Limited number of special locations built directly in hardware ARM has a 16 x 32-bit register file Use for frequently accessed data Registers numbered 0 to 15 (r0 to r15) Words 32-bit data called a word MIPS architecture has 32 x 32-bit register file Programming language can have far more amount of variables The natural unit of access in a computer, usually a group of 32 bits Corresponds to the size of a register in many architectures, like ARM, MIPS, etc. Design Principle 2 Smaller is faster. Why? Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 6

7 Example Compiling a C Assignment Using Registers C Language f = (g + h) (i + j); Compiled ARM Instructions ADD r5, r0, r1 ;temp reg. r5 contains g+h ADD r6, r2, r3 SUB r4, r5, r6 Compiler f, g, h, i, and j are variables used in C language ;temp reg. r6 contains i+j ;reg. r4 gets(g+h)-(i+j) It is the compiler s job to associate program variables with registers f,.., j in registers r0,,r4 r5 and r6 are used as temporary registers The MIPS convention is to use two-character names following a dollar sign to represent registers, such as $s0, $s1,.., $t0, $t1,.. Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 7

8 Registers vs. Memory Arithmetic instructions operands must be registers only 16 registers provided in ARM Only 32 registers provided in MIPS architecture Compiler associates variables with registers What about programs with lots of variables and more complex data structures arrays and structures Registers reside in the processor Control Memory Input Datapath Output Processor I/O Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 8

9 Registers vs. Memory Complex data structures are kept in memory while arithmetic operations occur only on registers in MIPS instructions Data transfer instructions To transfer data between memory and registers To access a word in memory, the instruction must supply the memory address Load Copies data from memory to register Load word instruction LDR r5, [r3,#32] // MIPS lw $t0, 32($s3) Store Copies data from register to memory Store word instruction STR r5, [r3,#48] // MIPS sw $t0, 48($s3) Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 9

10 Memory Operands Main memory used for composite data Arrays, structures, dynamic data To apply arithmetic operations Load values from memory into registers Store result from register to memory Memory is byte addressed Each address identifies an 8-bit byte Words are aligned in memory Address must be a multiple of 4 ARM is Little Endian Least-significant byte at least address c.f. Big Endian Most-significant byte at least address of a word Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 10

11 Memory Operand Example 1 base register Compiling an assignment when an operand is in memory g = h + A[8]; where g in r1, h in r2, base address of A in r3 r5 is temporary register Compiled ARM code LDR r5,[r3,#8] ADD r1, r2, r5 offset ; reg. r5 gets A[8] ; g = h + A[8] This is just an explanation of concept, we will discuss the actual code later. Compiled MIPS instructions look like lw $t0,8($s3) //temp reg. $t0 gets A[8] add $s1, $s2, $t0 //g = h + A[8] Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 11

12 Memory Organization Viewed as a large, single-dimension array, with an address. A memory address is an index into the array "Byte addressing" means that the index points to a byte of memory bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 12

13 Memory Organization Bytes are nice, but most data items use larger "words" For ARM & MIPS, a word is 32 bits or 4 bytes bits of data 32 bits of data 32 bits of data 32 bits of data Registers hold 32 bits of data 2 32 bytes with byte addresses from 0 to words with byte addresses 0, 4, 8, Words are aligned i.e., what are the least 2 significant bits of a word address? Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 13

14 Memory Organization Word Addressing v.s. Byte addressing Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 14

15 Memory Operand Example 2 Load and store instructions Example (ARM & MIPS use Byte addressing) C code A[12] = h + A[8]; ARM code MIPS code LDR r5,[r3,#32] ADD r5, r2, r5 STR r5,[r3,#48] ;Stores h+a[8] into A[12] lw $t0, 32($s3) add $t0, $s2, $t0 sw $t0, 48($s3) Store word has destination last Index 8 requires offset of 32, index 12 requires offset of 48 Remember in MIPS, arithmetic operands are registers, no memory allowed! Can t write add 48($s3), $s2, 32($s3) Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 15

16 Registers vs. Memory Registers are faster to access than memory Operating on memory data requires loads and stores More instructions to be executed Compiler must use registers for variables as much as possible Only spill to memory for less frequently used variables The process of putting less commonly used variables (or those needed later) into memory is called spilling registers Register optimization is important! Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 16

17 So far we ve learned ARM & MIPS loading words but addressing bytes arithmetic on registers only ARM Instruction Meaning MIPS Instruction ADD r1, r2, r3 r1=r2+r3 add $s1, $s2, $s3 SUB r1, r2, r3 r1=r2 r3 sub $s1, $s2, $s3 LDR r1, [r2,#100] r1=memory[r2+100] lw $s1, 100($s2) STR r1, [r2,#100] Memory[r2+100]=r1 sw $s1, 100($s2) Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 17

18 Constant or Immediate Operands In SPEC2006, more than 50% of ARM arithmetic instructions have a constant as an operand What is a constant? A designated value which will not be changed and also not allowed to change during program execution Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 18

19 Constant or Immediate Operands If we want to add a constant 4 to register r3 By using the instructions we have seen so far LDR r5, [r1,#addrconstant4] //r5 = 4 ADD r3, r3, r5 //r3 = r3 + r5 // The constant 4 is pre-stored in memory and r1 + AddrConstant4 is the memory address ARM Use immediate operand ADD r3, r3, #4 ; r3 = r3 + 4 MIPS offers add immediate instruction addi $s3, $s3, 4 //$s3 = $s3 + 4 (MIPS does not offer sub immediate, subi. Why??) Design Principle 3 Make the common case fast Small constants are common Immediate operand avoids a load instruction Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 19

20 Numbers Bits are just bits (no inherent meaning) conventions define relationship between bits and numbers Binary numbers (base 2) decimal n bit numbers most significant bit (32-bit wide) least significant bit Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 20

21 Unsigned Binary Integers Given an n-bit number x x n 1 n n 12 xn 22 x12 x02 Range 0 to +2 n 1 Example = = = Using 32 bits 0 to +4,294,967,295 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 21

22 Numbers Of course it gets more complicated numbers are finite (overflow) Proper results after operations can not be represented by these rightmost hardware bits, overflow occurred. fractions and real numbers negative numbers e.g., no MIPS subi instruction; addi can add a negative number How do we represent negative numbers? i.e., which bit patterns will represent which numbers? Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 22

23 2s-Complement Signed Integers Bit 31 is sign bit 1 for negative numbers 0 for non-negative numbers ( 2 n 1 ) can t be represented Non-negative numbers have the same unsigned and 2s-complement representation Some specific numbers Most-negative Most-positive Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 23

24 32-bit Signed Numbers 32 bit signed numbers two = 0 ten two = + 1 ten two = + 2 ten two = + 2,147,483,645 ten two = + 2,147,483,646 ten two = + 2,147,483,647 ten two = 2,147,483,648 ten two = 2,147,483,647 ten two = 2,147,483,646 ten two = 3 ten two = 2 ten two = 1 ten Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 24

25 2s-Complement Signed Integers Given and n-bit number x x n 1 n n 12 xn 22 x12 x02 Range 2 n 1 to +2 n 1 1 Example = = 2,147,483, ,147,483,644 = 4 10 Using 32 bits - 2,147,483,648 to +2,147,483,647 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 25

26 Signed Negation Complement and add 1 Complement means inverting all bits 1 0, 0 1 x x x 1 x Example negate = = = Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 26

27 Sign Extension Representing a number using more bits Preserve the numeric value In ARM instruction set LDRSB,LDRSH extend loaded signed byte/halfword (vs. LDRB,LDRH) In MIPS lb vs. lbu, lh vs. lhu Replicate the sign bit to the left c.f. unsigned values extend with 0s Examples 8-bit to 16-bit => => Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 27

28 Representing Instructions Instructions are encoded in binary Called machine code ARM instructions Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register numbers, Regularity! Register numbers r0 to r15 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 28

29 ARM Data Processing (DP) Instructions Cond F I Opcode S Rn 4 bits 2 bits 1 bits 4 bits 1 bits 4 bits Rd Operand2 4 bits 12 bits Instruction fields Cond Condition F Instruction Format IImmediate. If I is 0, the second source operand is a register, else the second source is a 12-bit immediate. Opcode Basic operation of the instruction S Set Condition Code Rn The first register source operand Rd The destination register operand Operand2 The second source operand Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 29

30 DP Instruction Example Cond F I Opcode S Rn 4 bits 2 bits 1 bits 4 bits 1 bits 4 bits Rd Operand2 4 bits 12 bits ADD r5,r1,r2 ; r5 = r1 + r bits 2 bits 1 bits 4 bits 1 bits 4 bits bits 12 bits Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 30

31 ARM Data Transfer (DT) Instruction Cond F Opcode Rn 4 bits 2 bits 6 bits 4 bits Rd Offset12 4 bits 12 bits LDR r5, [r3, #32] ; Temporary reg r5 gets A[8] bits 2 bits 6 bits 4 bits bits 12 bits Design Principle 4 Good design demands good compromises Different formats complicate decoding, but allow 32-bit instructions uniformly Keep formats as similar as possible Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 31

32 ARM Instruction Encoding Revealed so Far Name Format Example Comments ADD DP 14 ten ten 0 2 ten 1 3 ten ADD r1, r2, r3 SUB DP 14 ten ten 0 2 ten 1 3 ten SUB r1, r2, r3 LDR DT 14 ten 1 24 ten 2 ten ten LDR r1,[r2,#100] STR DT 14 ten 1 25 ten 2 ten ten STR r1,[r2,#100] Field Size 4 bits 2 bits 1 bit 4 bits 1 bit 4 bits 4 bits 12 bits DP format DP Cond F I Opcode S Rn Rd Operand2 DT format DT Cond F Opcode Rn Rd Offset12 All ARM instruction are 32 bits long Arithmetic instruction format Data transfer format Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 32

33 Logical Operations Instructions for bitwise manipulation Operation C Java ARM Bitwise AND & & AND Bitwise OR ORR Bitwise NOT ~ ~ MVN Shift left << << LSL Shift right >> >>> LSR Useful for extracting and inserting groups of bits in a word The needs to operate on fields of bits within a word or even on individual bits Examining characters which are stored as bytes within words Packing and unpacking of bits into words Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 33

34 Bitwise Operations AND Bitwise AND operations Basic AND operation in bit x & 1 = x x & 0 = 0 Useful to mask bits in a word A bit pattern in conjunction with AND is called a mask To retrieve some fields of the word and leave others as 0s Example <= r2 & = <= r => r5 ARM Instructions AND r5, r1, r2 ; r5 = r1 & r2 MIPS has and & andi (for immediate operand) E.g. andi $t0, $t1, 100 // $t0 = $t1 & 100 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 34

35 Bitwise Operations OR Bitwise OR operations Basic OR operation in bit x 1 = 1 x 0 = x Useful to include bits in a word set 1s in some bits of the word and leave others un-touched Example = <= r <= r => r5 ARM Instructions ORR r5, r1, r2 ; r5 = r1 r2 MIPS has or and ori (for immediate operand) E.g. ori $t0, $t1, 100 // $t0 = $t1 100 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 35

36 Bitwise Operations NOT Bitwise NOT operation Useful to invert bits in a word Change 0 to 1, and 1 to 0 ARM has Move Not (MVN), also has MOV which copy word directly. MVN r5, r1 ; reg. r5 = ~ reg. r1 Example MVN <= r1 = => r5 MIPS has bitwise NOR operation which can achieve NOT operations Basic NOR operation in bit ~(x 1) = 0 ~(x 0) = ~x To invert bit patterns is to NOR them with 0s i.e. A NOR 0 = NOT(A OR 0) = NOT(A) Support only operate with two register operands E.g. nor $t0, $t1, $t3 //$t0 = ~($t1 $t3) Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 36

37 Logical SHIFT Operations SHIFT operations Move all the bits in a word to the left or right Filling emptied bits with 0s Bonus benefits Shifting left by i bits give the same results as multiplying by 2 i. Shifting right (logically) by i bits give the same results as dividing by 2 i for unsigned number only. Why?!! Examples Shift 9 left (logically) by = 9 ten = 144 ten Shift 9 right (logically) by = 9 ten = 2 ten Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 37

38 Logical SHIFT Operations Examples Shift left -1,073,741,815 (logically) by = -1,073,741,815 ten = -2,147,483,630 ten Shift left -1,073,741,815 (logically) by = -1,073,741,815 ten = 36 ten (Overflow) Shift right -1,073,741,815 (logically) by = -1,073,741,815 ten = 1,610,612,740 ten (Error) How to do it correctly for right shift on signed numbers? Do sign-extension (Arithmetic Shifting) Shift right -1,073,741,815 (arithmetically) by = -1,073,741,815 ten = -536,870,908 ten (Correct) Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 38

39 Logical SHIFT Operations Most architectures offer separate instructions for shifting operations, but not ARM MIPS instructions sll, srl Example sll $t2, $s0, 4 //$t2 = $s0 << 4 bits ARM offers the ability to shift the second operand as part of any data processing instruction (LSL, LSR) Examples ADD r5, r1, r2, LSL #2 ; r5 = r1 + (r2 << 2) MOV r6, r5, LSR #4 ; r6 = r5 >> 4 ARM allows shifting by the value found in a register MOV r6, r5, LSR r3 ; r6 = r5 >> 3 How can ARM support these features in instruction encoding? Hint why Operand2 in DP format needs 12 bits? Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 39

40 ARM - Encoding of SHIFT operations shift_imm how many positions to shift, i.e. shift amount (5 bits immediate number) Shift 0 LSL, 1 LSR Rs shift amount by register value (4 bits register number) Rm Register number for 2 nd register operand or source operand for MOV, MVN instructions Examples ADD r5, r1, r2, LSL #2 ; r5 = r1 + (r2 << 2) MOV r6, r5, LSR #4 ; r6 = r5 >> 4 MOV r6, r5, LSR r3 ; r6 = r5 >> 3 Cond F I Opcode S Rn Operand2 (12 bits) Shift_imm Shift 0 Rm Rs 0 Shift 1 Rm Rd Shift_imm Shift Rm Rs 0 Shift Rm Error in the text book! Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 40

41 Conditional Operations Decision making instructions alter the control flow, i.e., change the "next" instruction to be executed like if statement with a goto Branch to a labeled instruction if a condition is true Otherwise, continue sequentially CMP reg1,reg2 BEQ L1 if (reg1 == reg2) branch to instruction labeled L1; CMP reg1,reg2 BNE L1 if (reg1!= reg2) branch to instruction labeled L1; B exit ; go to exit unconditional jump to instruction labeled exit Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 41

42 Compiling If Statements C code if (i==j) f = g+h; else f = g-h; f, g, in r0, r1,..r4 Compiled ARM code CMP r3,r4 BNE Else ; go to Else if i!= j ADD r0,r1,r2 ; f = g + h (skipped if i!= j) B Exit Else SUB r0,r1,r2 ; f = g - h (skipped if i = j) Exit Assembler calculates addresses Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 42

43 Compiling Loop Statements Can we build a while loop block with instructions that we have learn so far? Example C code while (save[i] == k) i += 1; i in r3, k in r5, base address of save in r6 Compiled ARM code Loop ADD r12,r6, r3, LSL # 2 ; r12 = address of save[i] LDR r0,[r12,#0] ; Temp reg r0 = save[i] CMP r0,r5 BNE Exit ; go to Exit if save[i] k ADD r3,r3,#1 ; i = i + 1 B Loop ; go to Loop Exit Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 43

44 Basic Blocks A basic block is a sequence of instructions with No embedded branches (except at end) No branch targets (except at beginning) A compiler identifies basic blocks for optimization An advanced processor can accelerate execution of basic blocks Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 44

45 Signed vs. Unsigned Comparison Signed comparison BGE,BLT,BGT,BLE Unsigned comparison BHS,BLO,BHI,BLS Example r0 = r1 = CMP r0,r1 BLO L1 ; unsigned branch Branch not taken since 4,294,967,295 ten > 1 ten BLT L2 ; signed branch Branch taken to L2 since -1 ten < 1 ten. How about compiling Case/Switch Statements? Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 45

46 Encoding Branch Instructions in ARM Remember that we have 4 bits Cond field in the instruction encoding format Conditional Execution is specified in the field. Value Meaning Value Meaning 0 EQ (Equal) 8 HI (unsigned Higher) 1 NE (Not Equal) 9 LS (unsigned Lower or Same) 2 HS (unsigned Higher or Same) 10 GE (signed Greater than or Equal 3 LO (unsigned Lower) 11 LT (signed Less Than) 4 MI (Minus, <0) 12 GT (signed Greater Than) 5 PL (Plus, >= 0) 13 LE (signed Less Than or Equal) 6 VS (overflow Set, overflow) 14 AL (Always) 7 VC (overflow Clear, no overflow) 15 NV (reserved) Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 46

47 ARM BRANCH Instruction The maximum field length in DP & DT instruction formats is just 12 bits Limit the programs to just 2 12 or 4096 bytes Design Principle 4 Good design demands good compromises. Keep all instructions the same length Great another instruction Type BR Now we have 24 bits for the branch address. Is it good enough?? Maybe and Maybe NOT!! Most conditional branches are local (if else, Loops, etc.) How about unconditional branches?? Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 47

48 ARM BRANCH Instruction Working around on the 24 bits field ARM address space is 32 bits (byte addressing) Each instruction is 32 bits (4 bytes) long and instructions are stored in memory also. Have the 24 bits fields representing numbers of word (i.e. number of instructions) For conditional branch, it is easier to refer the branch target from the current instruction. PC-relative addressing branching address = PC + Branch address offset In fact, the ARM branch address is actually relative to the next two instruction from branch instruction. We will be more clear later. i.e. New PC = PC (24-bit branch offset)*4 (MIPS is relative to the next one instruction, i.e. New PC = PC (branch offset)*4) Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 48

49 Conditional Execution All instruction formats has the Cond field Most instructions can be conditionally executed, not just branch instructions. C Code if (i==j) f = g+h; else f = g-h; Compiled ARM code => f, g, in r0, r1,..r4 CMP r3,r4 BNE Else ; go to Else if i!= j ADD r0,r1,r2 ; f = g + h (skipped if i!= j) B Exit Else SUB r0,r1,r2 ; f = g - h (skipped if i = j) Exit Alternatively, CMP r3,r4 ADDEQ r0,r1,r2 ; f = g + h (skipped if i!= j) SUBNE r0,r1,r2 ; f = g - h (skipped if i = j) Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 49

50 Procedure Support What is a procedure (or function)? Procedure is a group of codes which can be repeated called from main program without duplicating the codes inside main program. Every time when a procedure is called, the caller can pass different parameters to the procedure for process. Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 50

51 Procedure Calling Steps in execution a procedure 1. Place parameters in registers 2. Transfer control to procedure 3. Acquire storage for procedure 4. Perform procedure s operations 5. Place result in register for caller 6. Return to place of call Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 51

52 ARM Register Conventions Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 52

53 Procedure Call Instructions Procedure call Branch and link BL ProcedureAddress Address of following instruction put in lr Jumps to target address Procedure return MOV pc,lr Copies lr to program counter Can also be used for computed jumps e.g., for case/switch statements Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 53

54 Issues What if the procedure needs more than 4 parameters (arguments) and/or 2 return value registers? What if the procedure calls another procedure? (Nested Procedures) Solution Spilling Registers Use stack in main memory for storing Parameters (if procedure has more than 4) Any registers that needs to be preserved across procedure calls, i.e. any registers needed by the caller must be restored to the values that they contained before the procedure was called. Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 54

55 Using More Registers Stack Ideal data structure for spilling registers to memory Last-in-first-out queue Stack pointer (sp, for ARM Reg. #13 is reserved for it) A pointer to the most recently added data in the stack, i.e. top of stack Adjusted by one word for each register that is saved or restored. Push Placing data onto the stack Stack pointer has to be subtracted by 4 (a word = 4 bytes) every time when word is placed onto the stack Pop Removing data from the stack Stack pointer has to be added by 4 every time when a word is retrieved from the stack => Stack implementation in most architectures (ARM & MIPS also) growing from higher memory addresses to lower addresses Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 55

56 Leaf Procedure Example Procedure that doesn t call another procedure => Leaf Procedure C code int leaf_example (int g, h, i, j) { int f; f = (g + h) - (i + j); return f; } Arguments g,, j in r0,, r3 f in r4 (hence, need to save r4 on stack) Result in r0 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 56

57 Leaf Procedure Example (Cont d) ARM code leaf_example SUB sp, sp, #12 STR r6,[sp,#8] STR r5,[sp,#4] STR r4,[sp,#0] ADD r5,r0,r1 ADD r6,r2,r3 SUB r4,r5,r6 MOV r0,r4 LDR r4, [sp,#0] LDR r5, [sp,#4] LDR r6, [sp,#8] ADD sp,sp,#12 MOV pc,lr Make room for 3 items Save r4,r5,r6 on stack r5 = (g+h), r6= (i+j) Result in r4 Result moved to return value register r0. Restore r4,r5,r6 Return Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 57

58 Stack between Procedure Calling r6 r5 r4 Before During After Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 58

59 Nested Procedure (Non-Leaf Procedure) A procedures that call other procedures, or call itself (recursive) For nested call, caller needs to save on the stack Its return address Any arguments and temporaries needed after the call Restore from the stack after the call Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 59

60 Non-Leaf Procedure Example C code int fact (int n) { if (n < 1) return f; else return n * fact(n - 1); } Argument n in register r0 Result in register r0 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 60

61 Non-Leaf Procedure Example (Cont d) ARM code fact SUB sp,sp,#8 ; Adjust stack for 2 items STR lr,[sp,#8] ; Save return address STR r0,[sp,#0] ; Save argument n CMP r0,#1 ; compare n to 1 BGE L1 MOV r0,#1 ; if so, result is 1 ADD sp,sp,#8 ; Pop 2 items from stack MOV pc,lr ; Return to caller L1 SUB r0,r0,#1 ; else decrement n BL fact ; Recursive call MOV r12,r0 ; Restore original n LDR r0,[sp,#0] ; and return address LDR lr,[sp,#0] ; pop 2 items from stack ADD sp,sp #8 ; MUL r0,r0,r12 ; Multiply to get result MOV pc,lr ; and return Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 61

62 What is Preserved Across a Procedure Call? To avoid restoring/saving registers values who are never used Caller pushes any argument registers (r0-r3) or scrach registers (r12) that are needed after the call. Callee pushes the link register (return address) lr and any variable registers (r4 r11) before nested procedure calls. Preserved Variable registers r4 r11 Stack pointer register sp Link register lr Stack above the stack pointer Not Preserved Argument registers r0 r3 Intra-procedure-call scratch register r12 Stack below the stack pointer The stack is preserved by making sure the callee does not write above sp sp is preserved by the callee adding exactly the same amount that was subtracted from it The other registers are preserved by saving them on the stack and storing them from there. Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 62

63 Allocating More Space for New Data C storage classes automatic and static Automatic variables are local to a procedure and are discarded when the procedure exits Static variables exist across exits from and entries to procedures which are always valid and can be seen in every procedure C variable declared outside all procedures are considered static, as are any variable declared using the keyword static. The rest are automatic MIPS reserve another register, called global pointer ($gp) for accessing static data. Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 63

64 Local Data on the Stack Local data allocated by callee e.g., C automatic variables Procedure frame (activation record) Used by some compilers to manage stack storage Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 64

65 Allocating Space for New Data on the Heap Text program code Static data global variables e.g., static variables in C, constant arrays and strings Dynamic data heap E.g., linked list data structures, malloc in C, new in Java Stack automatic storage Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 65

66 Communicating with People Computers use 8-bit bytes to represent characters, with American Standard Code for Information Interchange (ASCII) Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 66

67 Character Data Byte-encoded character sets ASCII 128 characters 95 graphic, 33 control Latin characters ASCII, +96 more graphic characters Unicode 32-bit character set Used in Java, C++ wide characters, Most of the world s alphabets, plus symbols UTF-8, UTF-16 variable-length encodings Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 67

68 Byte/Halfword Operations Could use bitwise operations ARM byte load/store String processing is a common case LDRB r0, [sp,#0] ; Read byte from source STRB r0, [r10,#0] ; Write byte to destination Sign extend to 32 bits LDRSB ; Sign extends to fill leftmost 24 bits ARM halfword load/store LDRH r0, [sp,#0] ; Read halfword (16 bits) from source STRH r0,[r12,#0] ; Write halfword (16 bits) to dest. Sign extend to 32 bits LDRSH ; Sign extends to fill leftmost 16 bits Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 68

69 String Copy Example C code (naïve) Null-terminated string void strcpy (char x[], char y[]) { int i; i = 0; while ((x[i]=y[i])!='\0') i += 1; } Addresses of x, y in registers r0, r1 i in register r4 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 69

70 String Copy Example (Cont d) ARM code strcpy SUB sp,sp, #4 ; adjust stack for 1 item STR r4,[sp,#0] ; save r4 MOV r4,#0 ; i = L1 ADD r2,r4,r1 ; addr of y[i] in r2 LDRB r3, [r2, #0] ; r3 = y[i] ADD r12,r4,r0 ; ; Addr of x[i] in r12 STRB r3 [r12, #0] ; x[i] = y[i] BEQ L2 ; exit loop if y[i] == 0 ADD r4,r4,#1 ; i = i + 1 B L1 ; next iteration of loop L2 LDR r4, [sp,#0] ; restore saved r4 ADD sp,sp, #4 ; pop 1 item from stack MOV pc,lr ; return Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 70

71 32-bit Immediates Most constants are small 16-bit immediate is sufficient For the occasional 32-bit constant Load 32 bit constant to r The 8 non-zerobits ( , 217 ten ) of the constant is rotated by 16 bits and MOV instruction (opcode -13) loads the 32 bit value The rotate-imm value is actually doubled for the actual number of bits of rotation Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 71

72 ARM Addressing Modes 1-3 of 12 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 72

73 ARM Addressing Modes (Cont d) 4-6 of 12 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 73

74 ARM Addressing Modes (Cont d) 7-8 of 12 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 74

75 ARM Addressing Modes (Cont d) 9-10 of 12 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 75

76 ARM Addressing Modes (Cont d) Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 76

77 Pseudoinstructions Most assembler instructions represent machine instructions one-to-one Pseudoinstructions figments of the assembler s imagination LDR r0, #constant The assembler determines which instructions to use to create the constant in the most efficient way. Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 77

78 Arrays vs. Pointers Array indexing involves Multiplying index by element size Adding to array base address Pointers correspond directly to memory addresses Can avoid indexing complexity Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 78

79 Example Clearing an Array clear1(int array[], int size) { int i; for (i = 0; i < size; i += 1) array[i] = 0; } clear2(int *array, int size) { int *p; for (p = &array[0]; p < &array[size]; p = p + 1) *p = 0; } Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 79

80 Comparison of Array vs. Ptr Multiply strength reduced to shift Array version requires shift to be inside loop Part of index calculation for incremented i c.f. incrementing pointer Compiler can achieve same effect as manual use of pointers Induction variable elimination Better to make program clearer and safer Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 80

81 Fallacies Powerful instruction higher performance Fewer instructions required But complex instructions are hard to implement May slow down all instructions, including simple ones Compilers are good at making fast code from simple instructions Use assembly code for high performance But modern compilers are better at dealing with modern processors More lines of code more errors and less productivity Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 81

82 Pitfalls Sequential words are not at sequential addresses Increment by 4, not by 1! Keeping a pointer to an automatic variable after procedure returns e.g., passing pointer back via an argument Pointer becomes invalid when stack popped Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 82

83 Concluding Remarks Instruction complexity is only one variable Lower instruction count vs. higher CPI / lower clock rate Design principles 1. Simplicity favors regularity 2. Smaller is faster 3. Make the common case fast 4. Good design demands good compromises Layers of software/hardware Compiler, assembler, hardware ARM typical of RISC ISAs c.f. x86 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 83

84 Concluding Remarks Measure ARM instruction executions in benchmark programs Consider making the common case fast Consider compromises Instruction class ARM examples SPEC2006 Int SPEC2006 FP Arithmetic ADD,SUB,MOV 16% 48% Data transfer LDR,STR,LDRB,LDRSB,LDR H,LDRSH,STRB,STRH 35% 36% Logical AND,ORR,MNV,LSL,LSR 12% 4% Conditional Branch B_,CMP 34% 8% Jump B,BL 2% 0% Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 84

85 More Detailed on Non-Leaf Procedure Example C code void main( ) { int I; I = fact(3); } I in register r4 Argument n in register r0 Result in register r0 int fact (int n) { if (n < 1) return 1; else return n * fact(n - 1); } Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 85

86 More Detailed on Non-Leaf Procedure Example pc Addr Instructions Comments 0x MOV r0, #3 ;Put argument into r0 0x BL fact ;call fact 0x C MOV r4, r0 ;store results to "I" 0x fact 0x SUB sp, sp, #8 ;adjust stack for pushing 2 items 0x STR lr, [sp, #4] ;save return address 0x STR r0, [sp, #0] ;save argument "n" 0x C CMP r0, #1 ;compare n to 1 0x BGE L1 ;if n >= 1 branch to L1 0x MOV r0, #1 ;else i.e. n < 1, result is 1 0x ADD sp, sp, #8 ;adjust stack for poping 2 items 0x C MOV pc, lr ;return to caller L1 0x SUB r0, r0, #1 ;decrement n 0x BL fact ;recursive call 0x MOV r12, r0 ;store returned result to r12 0x C LDR r0, [sp, #0] ;restore original n 0x LDR lr, [sp, #4] ;and return address 0x ADD sp, sp, #8 ;adjust stack after poping 2 items 0x MUL r0, r0, r12 ;multiply to get result 0x C MOV pc, lr ;and return sp Reg. Value r0 r4 r12 sp 0x7FFF FFF0 lr pc 0x Addr Value 0x7FFF FFF0 0x7FFF FFEC 0x7FFF FFE8 0x7FFF FFE4 0x7FFF FFE0 0x7FFF FFDC 0x7FFF FFD8 0x7FFF FFD4 0x7FFF FFD0 0x7FFF FFCC 0x7FFF FFC8 0x7FFF FFC4 0x7FFF FFC0 0x7FFF FFBC 0x7FFF FFB8 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 86

87 More Detailed on Non-Leaf Procedure Example pc Addr Instructions Comments 0x MOV r0, #3 ;Put argument into r0 0x BL fact ;call fact 0x C MOV r4, r0 ;store results to "I" 0x fact 0x SUB sp, sp, #8 ;adjust stack for pushing 2 items 0x STR lr, [sp, #4] ;save return address 0x STR r0, [sp, #0] ;save argument "n" 0x C CMP r0, #1 ;compare n to 1 0x BGE L1 ;if n >= 1 branch to L1 0x MOV r0, #1 ;else i.e. n < 1, result is 1 0x ADD sp, sp, #8 ;adjust stack for poping 2 items 0x C MOV pc, lr ;return to caller L1 0x SUB r0, r0, #1 ;decrement n 0x BL fact ;recursive call 0x MOV r12, r0 ;store returned result to r12 0x C LDR r0, [sp, #0] ;restore original n 0x LDR lr, [sp, #4] ;and return address 0x ADD sp, sp, #8 ;adjust stack after poping 2 items 0x MUL r0, r0, r12 ;multiply to get result 0x C MOV pc, lr ;and return sp Reg. Value r0 3 r4 r12 sp 0x7FFF FFF0 lr pc 0x Addr Value 0x7FFF FFF0 0x7FFF FFEC 0x7FFF FFE8 0x7FFF FFE4 0x7FFF FFE0 0x7FFF FFDC 0x7FFF FFD8 0x7FFF FFD4 0x7FFF FFD0 0x7FFF FFCC 0x7FFF FFC8 0x7FFF FFC4 0x7FFF FFC0 0x7FFF FFBC 0x7FFF FFB8 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 87

88 More Detailed on Non-Leaf Procedure Example pc Addr Instructions Comments 0x MOV r0, #3 ;Put argument into r0 0x BL fact ;call fact 0x C MOV r4, r0 ;store results to "I" 0x fact 0x SUB sp, sp, #8 ;adjust stack for pushing 2 items 0x STR lr, [sp, #4] ;save return address 0x STR r0, [sp, #0] ;save argument "n" 0x C CMP r0, #1 ;compare n to 1 0x BGE L1 ;if n >= 1 branch to L1 0x MOV r0, #1 ;else i.e. n < 1, result is 1 0x ADD sp, sp, #8 ;adjust stack for poping 2 items 0x C MOV pc, lr ;return to caller L1 0x SUB r0, r0, #1 ;decrement n 0x BL fact ;recursive call 0x MOV r12, r0 ;store returned result to r12 0x C LDR r0, [sp, #0] ;restore original n 0x LDR lr, [sp, #4] ;and return address 0x ADD sp, sp, #8 ;adjust stack after poping 2 items 0x MUL r0, r0, r12 ;multiply to get result 0x C MOV pc, lr ;and return sp Reg. Value r0 3 r4 r12 sp 0x7FFF FFF0 lr 0x C pc 0x Addr Value 0x7FFF FFF0 0x7FFF FFEC 0x7FFF FFE8 0x7FFF FFE4 0x7FFF FFE0 0x7FFF FFDC 0x7FFF FFD8 0x7FFF FFD4 0x7FFF FFD0 0x7FFF FFCC 0x7FFF FFC8 0x7FFF FFC4 0x7FFF FFC0 0x7FFF FFBC 0x7FFF FFB8 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 88

89 More Detailed on Non-Leaf Procedure Example pc Addr Instructions Comments 0x MOV r0, #3 ;Put argument into r0 0x BL fact ;call fact 0x C MOV r4, r0 ;store results to "I" 0x fact 0x SUB sp, sp, #8 ;adjust stack for pushing 2 items 0x STR lr, [sp, #4] ;save return address 0x STR r0, [sp, #0] ;save argument "n" 0x C CMP r0, #1 ;compare n to 1 0x BGE L1 ;if n >= 1 branch to L1 0x MOV r0, #1 ;else i.e. n < 1, result is 1 0x ADD sp, sp, #8 ;adjust stack for poping 2 items 0x C MOV pc, lr ;return to caller L1 0x SUB r0, r0, #1 ;decrement n 0x BL fact ;recursive call 0x MOV r12, r0 ;store returned result to r12 0x C LDR r0, [sp, #0] ;restore original n 0x LDR lr, [sp, #4] ;and return address 0x ADD sp, sp, #8 ;adjust stack after poping 2 items 0x MUL r0, r0, r12 ;multiply to get result 0x C MOV pc, lr ;and return sp Reg. Value r0 3 r4 r12 sp 0x7FFF FFE8 lr 0x C pc 0x Addr Value 0x7FFF FFF0 0x7FFF FFEC 0x7FFF FFE8 0x7FFF FFE4 0x7FFF FFE0 0x7FFF FFDC 0x7FFF FFD8 0x7FFF FFD4 0x7FFF FFD0 0x7FFF FFCC 0x7FFF FFC8 0x7FFF FFC4 0x7FFF FFC0 0x7FFF FFBC 0x7FFF FFB8 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 89

90 More Detailed on Non-Leaf Procedure Example pc Addr Instructions Comments 0x MOV r0, #3 ;Put argument into r0 0x BL fact ;call fact 0x C MOV r4, r0 ;store results to "I" 0x fact 0x SUB sp, sp, #8 ;adjust stack for pushing 2 items 0x STR lr, [sp, #4] ;save return address 0x STR r0, [sp, #0] ;save argument "n" 0x C CMP r0, #1 ;compare n to 1 0x BGE L1 ;if n >= 1 branch to L1 0x MOV r0, #1 ;else i.e. n < 1, result is 1 0x ADD sp, sp, #8 ;adjust stack for poping 2 items 0x C MOV pc, lr ;return to caller L1 0x SUB r0, r0, #1 ;decrement n 0x BL fact ;recursive call 0x MOV r12, r0 ;store returned result to r12 0x C LDR r0, [sp, #0] ;restore original n 0x LDR lr, [sp, #4] ;and return address 0x ADD sp, sp, #8 ;adjust stack after poping 2 items 0x MUL r0, r0, r12 ;multiply to get result 0x C MOV pc, lr ;and return sp Reg. Value r0 3 r4 r12 sp 0x7FFF FFE8 lr 0x C pc 0x Addr Value 0x7FFF FFF0 0x7FFF FFEC 0x C 0x7FFF FFE8 0x7FFF FFE4 0x7FFF FFE0 0x7FFF FFDC 0x7FFF FFD8 0x7FFF FFD4 0x7FFF FFD0 0x7FFF FFCC 0x7FFF FFC8 0x7FFF FFC4 0x7FFF FFC0 0x7FFF FFBC 0x7FFF FFB8 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 90

91 More Detailed on Non-Leaf Procedure Example pc Addr Instructions Comments 0x MOV r0, #3 ;Put argument into r0 0x BL fact ;call fact 0x C MOV r4, r0 ;store results to "I" 0x fact 0x SUB sp, sp, #8 ;adjust stack for pushing 2 items 0x STR lr, [sp, #4] ;save return address 0x STR r0, [sp, #0] ;save argument "n" 0x C CMP r0, #1 ;compare n to 1 0x BGE L1 ;if n >= 1 branch to L1 0x MOV r0, #1 ;else i.e. n < 1, result is 1 0x ADD sp, sp, #8 ;adjust stack for poping 2 items 0x C MOV pc, lr ;return to caller L1 0x SUB r0, r0, #1 ;decrement n 0x BL fact ;recursive call 0x MOV r12, r0 ;store returned result to r12 0x C LDR r0, [sp, #0] ;restore original n 0x LDR lr, [sp, #4] ;and return address 0x ADD sp, sp, #8 ;adjust stack after poping 2 items 0x MUL r0, r0, r12 ;multiply to get result 0x C MOV pc, lr ;and return sp Reg. Value r0 3 r4 r12 sp 0x7FFF FFE8 lr 0x C pc 0x C Addr Value 0x7FFF FFF0 0x7FFF FFEC 0x C 0x7FFF FFE8 3 0x7FFF FFE4 0x7FFF FFE0 0x7FFF FFDC 0x7FFF FFD8 0x7FFF FFD4 0x7FFF FFD0 0x7FFF FFCC 0x7FFF FFC8 0x7FFF FFC4 0x7FFF FFC0 0x7FFF FFBC 0x7FFF FFB8 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 91

92 More Detailed on Non-Leaf Procedure Example pc Addr Instructions Comments 0x MOV r0, #3 ;Put argument into r0 0x BL fact ;call fact 0x C MOV r4, r0 ;store results to "I" 0x fact 0x SUB sp, sp, #8 ;adjust stack for pushing 2 items 0x STR lr, [sp, #4] ;save return address 0x STR r0, [sp, #0] ;save argument "n" 0x C CMP r0, #1 ;compare n to 1 0x BGE L1 ;if n >= 1 branch to L1 0x MOV r0, #1 ;else i.e. n < 1, result is 1 0x ADD sp, sp, #8 ;adjust stack for poping 2 items 0x C MOV pc, lr ;return to caller L1 0x SUB r0, r0, #1 ;decrement n 0x BL fact ;recursive call 0x MOV r12, r0 ;store returned result to r12 0x C LDR r0, [sp, #0] ;restore original n 0x LDR lr, [sp, #4] ;and return address 0x ADD sp, sp, #8 ;adjust stack after poping 2 items 0x MUL r0, r0, r12 ;multiply to get result 0x C MOV pc, lr ;and return sp Reg. Value r0 3 r4 r12 sp 0x7FFF FFE8 lr 0x C pc 0x Addr Value 0x7FFF FFF0 0x7FFF FFEC 0x C 0x7FFF FFE8 3 0x7FFF FFE4 0x7FFF FFE0 0x7FFF FFDC 0x7FFF FFD8 0x7FFF FFD4 0x7FFF FFD0 0x7FFF FFCC 0x7FFF FFC8 0x7FFF FFC4 0x7FFF FFC0 0x7FFF FFBC 0x7FFF FFB8 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 92

93 More Detailed on Non-Leaf Procedure Example pc Addr Instructions Comments 0x MOV r0, #3 ;Put argument into r0 0x BL fact ;call fact 0x C MOV r4, r0 ;store results to "I" 0x fact 0x SUB sp, sp, #8 ;adjust stack for pushing 2 items 0x STR lr, [sp, #4] ;save return address 0x STR r0, [sp, #0] ;save argument "n" 0x C CMP r0, #1 ;compare n to 1 0x BGE L1 ;if n >= 1 branch to L1 0x MOV r0, #1 ;else i.e. n < 1, result is 1 0x ADD sp, sp, #8 ;adjust stack for poping 2 items 0x C MOV pc, lr ;return to caller L1 0x SUB r0, r0, #1 ;decrement n 0x BL fact ;recursive call 0x MOV r12, r0 ;store returned result to r12 0x C LDR r0, [sp, #0] ;restore original n 0x LDR lr, [sp, #4] ;and return address 0x ADD sp, sp, #8 ;adjust stack after poping 2 items 0x MUL r0, r0, r12 ;multiply to get result 0x C MOV pc, lr ;and return sp Reg. Value r0 3 r4 r12 sp 0x7FFF FFE8 lr 0x C pc 0x Addr Value 0x7FFF FFF0 0x7FFF FFEC 0x C 0x7FFF FFE8 3 0x7FFF FFE4 0x7FFF FFE0 0x7FFF FFDC 0x7FFF FFD8 0x7FFF FFD4 0x7FFF FFD0 0x7FFF FFCC 0x7FFF FFC8 0x7FFF FFC4 0x7FFF FFC0 0x7FFF FFBC 0x7FFF FFB8 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 93

94 More Detailed on Non-Leaf Procedure Example pc Addr Instructions Comments 0x MOV r0, #3 ;Put argument into r0 0x BL fact ;call fact 0x C MOV r4, r0 ;store results to "I" 0x fact 0x SUB sp, sp, #8 ;adjust stack for pushing 2 items 0x STR lr, [sp, #4] ;save return address 0x STR r0, [sp, #0] ;save argument "n" 0x C CMP r0, #1 ;compare n to 1 0x BGE L1 ;if n >= 1 branch to L1 0x MOV r0, #1 ;else i.e. n < 1, result is 1 0x ADD sp, sp, #8 ;adjust stack for poping 2 items 0x C MOV pc, lr ;return to caller L1 0x SUB r0, r0, #1 ;decrement n 0x BL fact ;recursive call 0x MOV r12, r0 ;store returned result to r12 0x C LDR r0, [sp, #0] ;restore original n 0x LDR lr, [sp, #4] ;and return address 0x ADD sp, sp, #8 ;adjust stack after poping 2 items 0x MUL r0, r0, r12 ;multiply to get result 0x C MOV pc, lr ;and return sp Reg. Value r0 2 r4 r12 sp 0x7FFF FFE8 lr 0x C pc 0x Addr Value 0x7FFF FFF0 0x7FFF FFEC 0x C 0x7FFF FFE8 3 0x7FFF FFE4 0x7FFF FFE0 0x7FFF FFDC 0x7FFF FFD8 0x7FFF FFD4 0x7FFF FFD0 0x7FFF FFCC 0x7FFF FFC8 0x7FFF FFC4 0x7FFF FFC0 0x7FFF FFBC 0x7FFF FFB8 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 94

95 More Detailed on Non-Leaf Procedure Example pc Addr Instructions Comments 0x MOV r0, #3 ;Put argument into r0 0x BL fact ;call fact 0x C MOV r4, r0 ;store results to "I" 0x fact 0x SUB sp, sp, #8 ;adjust stack for pushing 2 items 0x STR lr, [sp, #4] ;save return address 0x STR r0, [sp, #0] ;save argument "n" 0x C CMP r0, #1 ;compare n to 1 0x BGE L1 ;if n >= 1 branch to L1 0x MOV r0, #1 ;else i.e. n < 1, result is 1 0x ADD sp, sp, #8 ;adjust stack for poping 2 items 0x C MOV pc, lr ;return to caller L1 0x SUB r0, r0, #1 ;decrement n 0x BL fact ;recursive call 0x MOV r12, r0 ;store returned result to r12 0x C LDR r0, [sp, #0] ;restore original n 0x LDR lr, [sp, #4] ;and return address 0x ADD sp, sp, #8 ;adjust stack after poping 2 items 0x MUL r0, r0, r12 ;multiply to get result 0x C MOV pc, lr ;and return sp Reg. Value r0 2 r4 r12 sp 0x7FFF FFE8 lr 0x pc 0x Addr Value 0x7FFF FFF0 0x7FFF FFEC 0x C 0x7FFF FFE8 3 0x7FFF FFE4 0x7FFF FFE0 0x7FFF FFDC 0x7FFF FFD8 0x7FFF FFD4 0x7FFF FFD0 0x7FFF FFCC 0x7FFF FFC8 0x7FFF FFC4 0x7FFF FFC0 0x7FFF FFBC 0x7FFF FFB8 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 95

96 More Detailed on Non-Leaf Procedure Example pc Addr Instructions Comments 0x MOV r0, #3 ;Put argument into r0 0x BL fact ;call fact 0x C MOV r4, r0 ;store results to "I" 0x fact 0x SUB sp, sp, #8 ;adjust stack for pushing 2 items 0x STR lr, [sp, #4] ;save return address 0x STR r0, [sp, #0] ;save argument "n" 0x C CMP r0, #1 ;compare n to 1 0x BGE L1 ;if n >= 1 branch to L1 0x MOV r0, #1 ;else i.e. n < 1, result is 1 0x ADD sp, sp, #8 ;adjust stack for poping 2 items 0x C MOV pc, lr ;return to caller L1 0x SUB r0, r0, #1 ;decrement n 0x BL fact ;recursive call 0x MOV r12, r0 ;store returned result to r12 0x C LDR r0, [sp, #0] ;restore original n 0x LDR lr, [sp, #4] ;and return address 0x ADD sp, sp, #8 ;adjust stack after poping 2 items 0x MUL r0, r0, r12 ;multiply to get result 0x C MOV pc, lr ;and return sp Reg. Value r0 2 r4 r12 sp 0x7FFF FFE0 lr 0x pc 0x Addr Value 0x7FFF FFF0 0x7FFF FFEC 0x C 0x7FFF FFE8 3 0x7FFF FFE4 0x7FFF FFE0 0x7FFF FFDC 0x7FFF FFD8 0x7FFF FFD4 0x7FFF FFD0 0x7FFF FFCC 0x7FFF FFC8 0x7FFF FFC4 0x7FFF FFC0 0x7FFF FFBC 0x7FFF FFB8 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 96

97 More Detailed on Non-Leaf Procedure Example pc Addr Instructions Comments 0x MOV r0, #3 ;Put argument into r0 0x BL fact ;call fact 0x C MOV r4, r0 ;store results to "I" 0x fact 0x SUB sp, sp, #8 ;adjust stack for pushing 2 items 0x STR lr, [sp, #4] ;save return address 0x STR r0, [sp, #0] ;save argument "n" 0x C CMP r0, #1 ;compare n to 1 0x BGE L1 ;if n >= 1 branch to L1 0x MOV r0, #1 ;else i.e. n < 1, result is 1 0x ADD sp, sp, #8 ;adjust stack for poping 2 items 0x C MOV pc, lr ;return to caller L1 0x SUB r0, r0, #1 ;decrement n 0x BL fact ;recursive call 0x MOV r12, r0 ;store returned result to r12 0x C LDR r0, [sp, #0] ;restore original n 0x LDR lr, [sp, #4] ;and return address 0x ADD sp, sp, #8 ;adjust stack after poping 2 items 0x MUL r0, r0, r12 ;multiply to get result 0x C MOV pc, lr ;and return sp Reg. Value r0 2 r4 r12 sp 0x7FFF FFE0 lr 0x pc 0x Addr Value 0x7FFF FFF0 0x7FFF FFEC 0x C 0x7FFF FFE8 3 0x7FFF FFE4 0x x7FFF FFE0 0x7FFF FFDC 0x7FFF FFD8 0x7FFF FFD4 0x7FFF FFD0 0x7FFF FFCC 0x7FFF FFC8 0x7FFF FFC4 0x7FFF FFC0 0x7FFF FFBC 0x7FFF FFB8 Embedded System and Experiment, 102/2, EE/CGU, W.Y. Lin 97