Sheet For the following C code: a = b + c; b = a + c; d = a b; Write an equivalent assembly MIPS program. Solution:

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1 Sheet 2 1- For the following C code: a = b + c; b = a + c; d = a b; Write an equivalent assembly MIPS program. add a, b, c add b, a, c sub d, a, b # b + c a # a + c b # a - b d 2- What is the corresponding MIPS assembly code for each of the following C statements? How many MIPS instructions are needed in each case? Assume that the variables f, g, h, i, and j are available 32-bit integers a. f=f+g+h+i+j+2 b. f=g-(f+5 ) a- add f, f, g add f, f, h add f, f, i add f, f, j addi f, f, 2 5 instructions b- addi f, f, 5 sub f, g, f 2 instructions

2 3. Why doesn t MIPS have a subtract immediate instruction? Since MIPS includes add immediate and since immediates can be positive or negative, subtract immediate would be redundant. 4. What is the corresponding MIPS assembly code for each of the following C statements? How many MIPS instructions and how many registers are needed in each case? Assume that the variables f, g, and h are assigned to registers $s0, $s1, and $s2 respectively and that the base address of arrays A and B are in registers $s6 and $s7. a. f= -g + h + B[1] ; b. f= A[B[g] + 1] ; a. lw $s0, 4($s7) sub $s0, $s0, $s1 add $s0, $s0, $s2 b. add $t0, $s7, $s1 lw $t0, 0($t0) add $t0, $t0, $s6 lw $s0, 4($t0)

3 5. Some computers have explicit instructions to extract an arbitrary field from a 32-bit register and to place it in the least significant bits of a register. The figure below shows the desired operation: Find the shortest sequence of MIPS instructions that extracts a field for the constant values i = 5 and j = 22 from register $t3 and places it in register $t0. (Hint: It can be done in two instructions.) sll $t0, $t3,9 # shift $t3 left by 9, store in $t0 srl $t0,$t0, 15 # shift $t0 right by The following logical instructions are not included in the MIPS instruction set. If the Value of $t2=0x00ffa5a5 and the value of $t3=0xffff003c, what is the result of $t1 in each case? Implement these logical instructions using the minimal set of MIPS instructions and show the bit-level representation of these instructions. a. andn $t1,$t2,$t3 #bitwise AND of $t2,!$t3 b. XNOR $t1,$t2,$t3 #bitwise exclusive NOR

4 a. 0x0000a581 b. 0x00ff5a66 a. nor $t1, $t3, $0 and $t1, $t1, $t2 b. A.B + A.B xor $t1,$t2,$t3 nor $t1,$t1,$zero

5 7. For the following MIPS machine code listed in hexadecimal, using the MIPS reference data sheet: a. Disassemble the machine code to a MIPS assembly code segment. b. Decompile the obtained MIPS code segment to a C code segment. List assumed register placement in a table. 8E AD First we will divide this for 32 bit segments representing the bit size of each MIPS instruction line: Line1: 0x 8E Convert to binary From the bits 31 to 26 =0b = 35 =0x23 This represents the op code of the LW instruction so it is an I-type instruction and it can be divided as follows: bits No. of bits I-format op rs rt 16- bit immediate Value bin Value decimal 35 (0x23) Translation LW $s3 $t0 32 immediate Instruction lw $t0, 32($s3)

6 Line2: 0x Convert to binary From the OP code bits 31 to 26 =0b From the Funct. bits 5 to 0 =0b = 32=0x 20 This represents the instruction add instruction which is R-type instruction bits No. of bits R-format op rs rt rd shamt funct Value bin Value decimal (0x 20) Translation R-type $s2 $t0 $t0 0 add Instruction add $t0, $s2, $t0 Line3: 0x Convert to binary From the OP code bits 31 to 26 =0b From the Funct. bits 5 to 0 =0b = 0 This represents the instruction SLL instruction which is R-type instruction

7 bits No. of bits R-format op rs rt rd shamt funct Value bin Value decimal Translation R-type X $s4 $t1 2 SLL Instruction sll $t1,$s4,2 Line4: 0x Convert to binary From the OP code bits 31 to 26 =0b From the Funct. bits 5 to 0 =0b = 32=0x 20 This represents the instruction add which is R-type instruction bits No. of bits R-format op rs rt rd shamt funct Value bin Value decimal (0x 20) Translation R-type $t1 $s3 $t1 0 add Instruction add $t1, $t1, $s3

8 Line 5: 0x AD Convert to binary From the OP code bits 31 to 26 =0b101011= 43 = 0x 2B This represents the op code of the SW instruction so it is an I-type instruction and it can be divided as follows: bits No. of bits I-format op rs rt 16- bit immediate Value bin Value decimal 43 (0x2B) Translation SW $t1 $t0 0 immediate Instruction sw $t0, 0($t1)

9 8. Assume that the variables f, g, h, and i are assigned to registers $s0, $s1, $s2, and $s3, respectively. Assume that the base address of array A is in register $s6. a. add $s0,$s0,$s1 add $s0,$s3,$s2 add $s0,$s0,$s3 b.addi $s6,$s6,-20 add $s6,$s6,$s1 lw $s0,8($s6) 1- from assembly to C: a. f = f + g; f = I + h; f= f + I; can be reduced to f=2i + h; b. A[g-3] 2- The value of $s0 at the end of each code:

10 a. $s0=2*40+30=110 b. $s0=m[ ]=m[264]= Showing the required fields: a. Type Op code rs rt rd add $s0, $s0, $s1 add add $s0, $s3, $s2 add add $s0, $s0, $s3 add b. Type Op code rs rt rd immediate addi $s6,$s6,-20 add 0x add $s6,$s6,$s1 add 0x lw $s0,8($s6) add 0x