ECE 4510/5530 Microcontroller Applications Week 6

Transcription

1 ECE 4510/5530 Microcontroller Applications Week 6 Dr. Bradley J. Bazuin Associate Professor Department of Electrical and Computer Engineering College of Engineering and Applied Sciences

2 Lab 5 Element Hardware Development Enhanced Capture Timer (ECT) (Chap. 8) Input Capture (external event timing) Pulse Width Modulator (PWM) (Chap. 8) Serial Communication Interface (SCI) (Chap. 9) RS-232 Transceiver Software Development Smoothing (filtering) measured data ECE

3 PWM COMPUTATION SPREAD SHEET ECE 4510/5530 3

4 PWM SA/SB Clock Rates E-Clock prescale vs. PWMSCLA/B E-Clock / / / / / / / Using values that are numerical factors of the clock rate 2 n, 3 n, 5 n and combinations This rate is further reduced by the PWMCNTx to form the PWM periodic rate. for 0-100% duty cycle in steps of 1, PWMCNTx=100 and rate is SA/B_rate/100 ECE 4510/5530 4

5 PWM Spread Sheet See the PWM Design MS Excel file ECE 4510/5530 5

6 STATES AND MODES IN LAB 4 ECE 4510/5530 6

7 Lab Task Write code for a home appliance off timer. To initialize and start the code, press the A of the keypad. When B is pressed, the following decimal digits (0-9) will define how long (in seconds) the relay is to remain energized. When the number has been entered, press C. To turn on the coil and begin the time, press D. If F is pressed at any time, the coil should be turned off and the system should return to a mode where it is ready for programming. ECE 4510/5530 7

8 States A: Initialization B: time in seconds data entry C: accept time, idle until turned on D: turn on and start counting down the time E: undefined F: emergency stop User proofing" requires additional state transitions ECE 4510/5530 8

9 Sunseeker Driver Controller State Update Code (1 of 2) // Update the DC Mode switch(dcmode){ case POWERUP: if(switches_new & SW_IGN_ON){ enable = FALSE; switches_new &= ~(SW_IGN_ON); } else { dcmode = PRECHARGE; } break; case PRECHARGE: if(switches_new & SW_IGN_ON){ enable = FALSE; switches_new &= ~(SW_IGN_ON); switches_out_new = 0xFF00; if(bps_precharge_done) dcmode = DISABLE;} break; case DISABLE: if(enable){ if(reverse) dcmode = REV_RDY; else dcmode = FWD_RDY; } switches_new &= ~(SW_REGEN); break; case FWD_RDY: if(!enable){ dcmode = DISABLE; } else { if(reverse){ dcmode = REV_RDY; } else if(adcvalue1 > ADC_MIN moving){ dcmode = FWD_DRV; } } switches_new &= ~(SW_REGEN); break; enum MODE { POWERUP, PRECHARGE, DISABLE, FWD_RDY, FWD_DRV, REV_RDY, REV_DRV, REGENEN, CRCNTRL } dcmode; dcmode should be named dcstate for the operating state the car is in ECE 4510/5530 9

10 Sunseeker Driver Controller State Update Code (2 of 2) enum MODE { ECE 4510/5530 POWERUP, PRECHARGE, DISABLE, FWD_RDY, FWD_DRV, REV_RDY, REV_DRV, REGENEN, CRCNTRL } dcmode; case FWD_DRV: if(!enable){ dcmode = DISABLE; } else if(!moving && brake){ dcmode = FWD_RDY; } else if(cruise){ dcmode = CRCNTRL; switches_new &= ~(SW_REGEN); cruise_velocity = actual_velocity; cruise_current = avg_set_current; ruise_steps = 0; } else if(regen){ dcmode = REGENEN; } break; case REV_RDY: if(!enable){ dcmode = DISABLE; } else { if(!reverse){ dcmode = FWD_RDY; } else if(adcvalue1 > ADC_MIN moving){ dcmode = REV_DRV; } } switches_new &= ~(SW_REGEN); break; case REV_DRV: if(!enable){ dcmode = DISABLE; } else if(!moving && brake){ dcmode = REV_RDY; } switches_new &= ~(SW_REGEN); break; case REGENEN: if(!enable){ dcmode = DISABLE; } else if(!regen){ dcmode = FWD_DRV; } switches_new &= ~(SW_REVERSE); break; case CRCNTRL: if(!enable){ dcmode = DISABLE; } else if(!cruise brake){ dcmode = FWD_DRV; } switches_new &= ~(SW_REVERSE SW_REGEN); 10 break; } // Mode update completed

11 Using the previous example You need one switch-case statement to update the current state to the next state (or not change) A second switch-case block may be needed to perform operations based on the state. The two switch-case blocks could be merged into one to minimize code, but it may not be as clear to the person reading/debugging the code as to what is going on. two processes: (1) what to do in a state and (2) what is the next state ECE 4510/

12 Alternate State Method 1 asm( sei ); // disable interrupts // initialize everything here state = A ; asm( cli ); // enable interrupts while(1) { while(state == A ) { } while(state == B ) { } while(state == C ) { } etc Exist in a state until a condition changes the state variable. locked in a state primary while loop does not repeat regularly must have a means to modify state either in the state or by an interrupt with state as a global variable } ECE 4510/

13 Alternate State Method 2 asm( sei ); // disable interrupts // initialize everything here state = A ; asm( cli ); // enable interrupts while(1) { if(state == A ) { } else if(state == B ) { } else { Chained if else if else primary while loop repeats regularly not locked in a state state update or modification can be performed seperately } etc } ECE 4510/

14 SERIAL PERIPHERAL INTERFACE (SPI) ECE 4510/

15 What is Serial Peripheral Interface (SPI)? SPI is a synchronous serial protocol initial defined by Motorola to be used as standard for interfacing peripheral chips to a microcontroller. Devices are classified into the master or slaves. The SPI protocol uses four wires to carry out the task of data communication: MOSI: master out slave in MISO: master in slave out SCK: serial clock SS: slave select An SPI data transfer is initiated by the master device. A master is responsible for generating the SCK signal to synchronize the data transfer. ECE

16 Serial Peripheral Interface (SPI) Extended serial string transmission Synchronous (faster - devices work on clock edges) More than 8-bits at a time Multiple devices can communicate using the same serial lines (daisy chained or output wired-or) Chip Select line allows low power operations when a device is not selected Applications: ADC, DAC, temperature measurement, CAN controllers, SD card interface, etc. ECE

17 Data Transfer Example Chip Select: enable target device for transfer Serial Clock: fast clock from master for synchronous data transfers MOSI: master output, slave input (simultaneous transfer with MISO) MISO: slave output, master input (simultaneous transfer with MOSI) Typically, the first 8-bits are an address and/or command from master to slave and subsequent 8-bit transfers are data. ECE

18 Memory Addresses ECE

19 The HCS12 SPI Modules The MC9S12DP256 has three SPI modules: SPI0, SPI1, and SPI2. By default, the SPI0 share the use of the upper 4 Port S pins: PS7 SS0 (can be rerouted to PM3) PS6 SCK0 (can be rerouted to PM5) PS5 MOSI0 (can be rerouted to PM4) PS4 MISO0 (can be rerouted to PM2) By default, the SPI1 shares the use of the lower 4 Port P pins: PP3 SS1 (can be rerouted to PH3) PP2 SCK1 (can be rerouted to PH2) PP1 MOSI1 (can be rerouted to PH1) PP0 MISO1 (can be rerouted to PH0) By default, the SPI2 shares the use of the upper 4 Port P pins: PP6 SS2 (can be rerouted to PH7) PP7 SCK2 (can be rerouted to PH6) PP5 MOSI2 (can be rerouted to PH5) PP4 MISO2 (can be rerouted to PH4) It is important to make sure that there is no conflict in the use of signal pins when making rerouting decision. ECE

20 Module Routing Register The MODRR configures the re-routing of CAN0, CAN4, SPI0, SPI1, and SPI2 on defined port pins. ECE 4510/

21 SPI0 Pin Selection MODRR[4] Default Alternate ECE 4510/

22 SPI1 and SPI2 Pin Selection MODRR[5:6] Default Alternate ECE 4510/

23 Adapt9S12DP512 I/O Pins ECE Primary Pins Alternate Pins

24 Motorola/Freescale DOCUMENT NUMBER S12SPIV3/D ECE 4510/

25 SPI Related Registers (1 of 6) The operating parameters of each SPI module are controlled via two control registers: SPIxCR1: (x = 0, 1, or 2) SPIxCR2 The baud rate of SPI transfer is controlled by the SPIxBR register. The operation status of the SPI operation is recorded in the SPIxSR register. The SS pin may be disconnected from SPI by clearing the SSOE bit in the SPIxCR1 register. After that, it can be used as a general I/O pin. If the SSOE bit in the SPIxCR1 register is set to 1, then the SS signal will be asserted to enable the slave device whenever a new SPI transfer is started. The equation for setting the SPI baud rate is given in Figure ECE

26 SPI Related Registers (2 of 6) SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE reset: SPIE: SPI interrupt enable bit 0 = SPI interrupts are disabled 1 = SPI interrupts are enabled SPE: SPI system enable bit 0 = SPI disabled 1 = SPI enabled and pins PS4-PS7 are dedicated to SPI function SPTIE: SPI transmit interrupt enable 0 = SPTEF interrupt disabled 1 = SPTEF interrupt enabled MSTR: SPI master/slave mode select bit 0 = slave mode 1 = master mode CPOL: SPI clock polarity bit 0 = active high clocks selected; SCK idle low 1 = active low clocks selected, SCK idle high CPHA: SPI clock phase bit 0 = The first SCK edge is issued one-half cycle into the 8-cycle transfer operation. 1 = The SCK edge is issued at the beginning of the 8-cycle transfer operation. SSOE: slave select output enable bit The SS output feature is enabled only in master mode by asserting the SSOE bit and the MODFEN bit of the SPIxCR2 register. LSBF: SPI least-significant-bit first enable bit 0 = data is transferred most-significant bit first 1 = data is transferred least-significant bit first Important Control Clock Mode Interrupt Enable SPI Enable Master/Slave ECE 2510 Figure 10.1 SPI control register 1 (SPIxCR1, x = 0, 1, or 2) 26

27 SPI Related Registers (3 of 6) MODFEN BIDIROE 0 SPSWAI SPC0 reset: MODFEN: Mode fault enable bit 0 = Disable the MODF error 1 = Enable settinig the MODF error BIDIROE: Output enable in the bidirectional mode of operation 0 = Output buffer disabled 1 = Output buffer enabled SPSWAI: SPI stop in wait mode 0 = SPI clock operates normally in stop mode 1 = Stop SPI clock generation in Wait mode SPC0: Serial pin control bit 0 With the MSTR bit in the SPIxCR1 register, this bit enables bidirectional pin configuration as shown in Table Figure 10.2 SPI control register 2 (SPIxCR2, x = 0, 1, or 2) ECE

28 SPI Related Registers (4 of 6) Table 10.1 SS input/output selection MODFEN SSOE Master Mode Slave mode SS not used by SPI SS not used by SPI SS input with MODF feature SS output SS input SS input SS input SS input Dr. Bazuin s Typical Use (i.e. all Sunseeker code): I do not let the SCI peripheral control the SSn bit. I always make it a general purpose I/O pin: for masters, it is an output, for slaves, it is an input. The pin then is pre-transfer asserted (goes low) chip selected which is deasserted (goes high) post-transfer. Please do it this way! ECE

29 SPI Related Registers (5 of 6) SPPR2 SPPR1 SPPR0 0 SPR2 SPR1 SPR0 reset: SPPR2~SPPR0: SPI baud rate preselection bits SPR2~SPR0: SPI baud rate selection bits BaudRateDivisor = (SPPR + 1) 2 (SPR + 1) Baud Rate = Bus Clock BaudRateDivisor Figure 10.3 SPI baud rate register (SPIxBR, x = 0, 1, or 2) SPIF 0 SPTEF MODF reset: SPIF: SPI interrupt request bit SPIF is set after the eight SCK cycles in a data transfer, and it is cleared by reading the SP0SR register (with SPIF set) followed by a read access to the SPI data register. 0 = transfer not yet complete 1 = new data copied to SPIxDR SPTEF: SPI data register empty interrupt flag 0 = SPI data register not empty 1 = SPI data register empty MODF: mode error interrupt status flag 0 = mode fault has not occurred ECE = mode fault has occurred 29 Figure 10.4 SPI status register (SPIxSR)

30 SPI Related Registers (6 of 6) Example 10.2 What is the highest possible baud rate for the SPI with 24 MHz bus clock? Solution: The highest SPI baud rate occurs when both the SPPR2-SPPR0 and SPR2-SPR0 are 000. In this case the baud rate is 24 MH 2 = 12 MHz. Example 10.1 Give a value to be loaded to the SPIxBR register to set the baud rate to 2 MHz for a 24 MHz bus clock. Solution: 24 MHz 2 MHz = 12 = 3 x 4. One possibility is to set SPPR2-SPPR0 and SPR2-SPR0 to 010 and 001, respectively. The value to be loaded into the SPIxBR register is $21. BaudRate E Clock BaudRateDivisor BaudRateDivisor SPR 2 SPRR 1 2 ECE

31 SPI Transmission Format (1 of 3) The data bits can be shifted on the rising or the falling edge of the SCK clock. Since the SCK can be idle high or idle low, there are four possible combinations as shown in Figure 10.5 and To shift data bits on the rising edge, set CPOL-CPHA to 00 or 11. To shift data bits on the falling edge, set CPOL-CPHA to 01 or 10. Data byte can be shifted in and out most significant bit first or least significant bit first. ECE

32 SPI Transmission Format (2 of 3) performed manually Transfer SS (O) master only Begin End SS (I) SCK (CPOL = 0) SCK (CPOL = 1) Sample I MOSI/MISO Change O MOSI Pin Change O MISO Pin MSB first (LSBF = 0) LSB first (LSBF = 1) t L MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB t T t I t L Minimum 1/2 SCK for t T, t I, t L Figure 10.5 SPI Clock format 0 (CPHA = 0) ECE

33 SPI Transmission Format (3 of 3) performed manually Transfer SS (O) master only Begin End SS (I) SCK (CPOL = 0) SCK (CPOL = 1) Sample I MOSI/MISO Change O MOSI Pin Change O MISO Pin MSB first (LSBF = 0) LSB first (LSBF = 1) t L MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB t T t I t L Minimum 1/2 SCK for t T, t I, t L Figure 10.6 SPI Clock format 1 (CPHA = 1) ECE

34 Normal and Bidirectional Mode When SPE = 1 Master mode MSTR = 1 Slave Mode MSTR = 0 Typical Normal Mode SPC0 = 0 Serial Out SPI Serial In MOSI MISO Serial In SPI Serial Out MOSI MISO SWOM enables open-drain output SWOM enables open-drain output Bi-directional mode SPC0 = 1 Serial Out SPI Serial In BIDIROE MOMI Serial In SPI Serial Out BIDIROE SISO Figure 10.7 Normal mode and bidirectional mode ECE

35 Bidirectional Mode (MOMI or SISO) A mode that uses only one data pin to shift data in and out. This mode is provided to deal with peripheral devices with only one data pin. Either the MOSI pin or the MISO pin can be used as the bidirectional pin. When the SPI is configured to the master mode (MSTR bit = 1), the MOSI pin is used in data transmission and becomes the MOMI pin. When the SPI is configured to the slave mode (MSTR bit = 0), the MISO pin is used in data transmission and becomes the SISO pin. The direction of each serial pin depends on the BIDIROE bit of the SPIxCR2 register. The pin configuration for MOSI and MISO are illustrated in Figure To read data from the peripheral device, clear the BIDIROE bit to 0. To output data to the peripheral device, set the BIDIROE bit to 1. ECE

36 SPI Circuit Connection In an SPI system, one device is configured as a master (up). Other devices are configured as slaves (peripherals). The circuit connection for a single-slave system is shown in Figure A multi-slave system may have two different connection methods as illustrated in Figure 10.9 and In Figure 10.9, the master can exchange data with each individual slave without affecting other slaves. In Figure 10.10, all the slaves are configured into a larger ring. A data transmission with certain slaves will go through other slaves. ECE

37 Single IC Interconnection Master SPI Shift register MISO MISO Slave SPI MOSI SCK MOSI SCK Shift register Baud Rate Generator SS V DD Figure 10.8 Master/slave transfer block diagram SS Please use a manual chip enable with a parallel output pin. This system uses SS as a chip-enable Typical Sunseeker connection. ECE

38 SS Multiple IC Interconnection +5V Slave 0 Slave 1 Slave k SPI Master (HCS12) SS Shift register MOSI SCK MISO SS Shift register MOSI SCK MISO SS... Shift register MOSI SCK MISO SS SCKx MOSIx MISOx PP0 PP PPk Figure 10.9 Single-master and multiple-slave device connection (method 1) This system uses SS as a chip-enable Sunseeker BPS ADC 1, 2, and 3 connection. ECE

39 Daisy Chained Multiple IC Interconnection Slave 0 Slave 1 Slave k SPI Master (HCS12) +5V Shift register MOSI SCK MISO SS Shift register MOSI SCK MISO SS... Shift register MOSI SCK MISO SS SS SCKx... MOSIx MISOx Figure Single-master and multiple-slave device connection (method 2) It saves pins, but complicates the serial transfers. Therefore, I have not used this method ECE

40 Example 10.3 Example 10.3 Configure the SPI0 to operate with the following setting assuming that Eclock is 24 MHz: 6 MHz baud rate Enable SPI0 to master mode SCK0 pin idle low with data shifted on the rising edge of SCK Transfer data most significant bit first and disable interrupt Disable SS0 function Stop SPI in Wait mode Normal SPI operation (not bidirectional mode) ECE

41 Example 10.3 Solution: f E / baud rate = 24 MHz/6 MHz = 4. We need to set SPPR2-SPPR0 and SPR2-SPR0 to 001 and 000, respectively. Write the value $10 into the SPI0BR register. The following instruction sequence will configure the SPI0 as desired: movb #$10, SPI0BR ; set baud rate to 6 MHz movb #$50, SPI0CR1 ; disable interrupt, enable SPI, SCK idle low, data ; latched on rising edge, data transferred msb first movb #$02, SPI0CR2 ; disable bidirectional mode, stop SPI in wait mode movb #0, WOMS ; enable Port S pull-up SPI0BR = 0x10; SPI0CR1 = 0x50; SPI0CR2 = 0x02; WOMS = 0x0; // set baud rate to 6 MHz // disable interrupt, enable SPI, SCK idle low, data // latched on rising edge, data transferred msb first // disable bidirectional mode, stop SPI in wait mode // enable Port S pull-up ECE

42 SPI Desirable Utility Functions The following operations are common in many applications and should be made into library functions to be called by many SPI applications: Send a character to SPI putcspix (x = 0, 1, or 2) Send a string to SPI putsspix (x = 0, 1, or 2) Read a character from SPI getcspix (x = 0, 1, or 2) Read a string from SPI getsspix (x = 0, 1, or 2) ECE

43 Function putcspi0 putcspi0: brclr SPI0SR,SPTEF, putcspi0 ; wait until write operation is permissible staa SPI0DR ; output the character to SPI0 pcsp0_lp: brclr SPI0SR,SPIF, pcsp0_lp ; wait until the byte is shifted out ldaa SPI0DR ; clear the SPIF flag rts void putcspi0 (char cx) { char temp; while(!(spi0sr & SPTEF)); /* wait until write is permissible */ SPI0DR = cx; /* output the byte to the SPI */ while(!(spi0sr & SPIF)); /* wait until write operation is complete */ temp = SPI0DR; /* clear the SPIF flag */ } ECE

44 Function putsspi0 ; the string to be output is pointed to by X putsspi0: ldaa 1,x+ ; get one byte to be output to SPI port beq doneps0 ; reach the end of the string? jsr putcspi0 ; call subroutine to output the byte bra putsspi0 ; continue to output doneps0: rts void putsspi0(char *ptr) { while(*ptr) { /* continue until all characters have been output */ putcspi0(*ptr); ptr++; } } ECE

45 Function getcspi0 ; This function reads a character from SPI0 and returns it in accumulator A getcspi0: brclr SPI0SR,SPTEF, getcspi0 ; wait until write operation is permissible staa SPI0DR ; trigger eight clock pulses for SPI transfer gcsp0_lp: brclr SPI0SR,SPIF, gcsp0_lp ; wait until a byte has been shifted in ldaa SPI0DR ; return the byte in A and clear the SPIF flag rts char getcspi0(void) { while(!(spi0sr & SPTEF)); /* wait until write is permissible */ SPI0DR = 0x00; /* trigger 8 SCK pulses to shift in data */ while(!(spi0sr & SPIF)); /* wait until a byte has been shifted in */ return SPI0DR; /* return the character */ } ECE

46 Function getsspi0 ; This function reads a string from the SPI and store it in a buffer pointed to by X ; The number of bytes to be read in passed in accumulator B getsspi0: tstb ; check the byte count beq donegs0 ; return when byte count is zero jsr getcspi0 ; call subroutine to read a byte staa 1,x+ ; save the returned byte in the buffer decb ; decrement the byte count bra getsspi0 donegs0: clr 0,x ; terminate the string with a NULL character rts void getsspi0(char *ptr, char count) { while(count) { /* continue while byte count is nonzero */ *ptr++ = getcspi0(); /* get a byte and save it in buffer */ count--; } *ptr = 0; /* terminate the string with a NULL */ } ECE