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1 Serial :. PT_EE-EC_A_Microprocessor_968 Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph: CLASS TEST 28-9 Subject : Microprocessors Date of test : 2/6/28 Answer Key. (d) 7. (c) 3. (a) 9. (d) 25. (a) 2. (c) 8. (b) 4. (d) 2. (a) 26. (b) 3. (a) 9. (c) 5. (c) 2. (c) 27. (d) 4. (c). (d) 6. (b) 22. (b) 28. (c) 5. (c). (a) 7. (a) 23. (b) 29. (a) 6. (b) 2. (d) 8. (d) 24. (b) 3. (c)

2 CT-28 Microprocessors 7 Detailed Explanations. (d) Contents of PC = FF H = address of next instruction and SP = 2 H. When CALL H is executed, PC is loaded with H and address of next instruction is pushed onto stack. Hence SP is decremented by 2. SP = FFE H and PC = H 2. (c) Memory size = 6 k 4 = = Address lines = 4 Data lines = 4 size = = 8 k Bytes 3. (a) PUSH instruction needs 3 machine cycles and 2 T-states (OPcode fetch 6T, memory write 3T, memory write 3T) POP instruction needs 3 machine cycles and T-states (OPcode fetch 4T, memory read 3T, memory read 3T) 4. (c) SHLD 6-bit address instruction stores the content of HL pair at 6-bit address specified. It consists of cycles as F + R + R + W + W. Hence, RD = 3; WR = 2; ALE = 5 5. (c) 4 kb memory can be represented as kb memory can be represented as Hence, address lines are 2 and 3 respectively. 6. (b) 7. (c) A = XRI H A = and = ; AC = and Z = After RAL 8. (b) A = = H = and Z = ( Z is not affected by RAL) DAD HContents of HL pair are added to HL pair XCHGExchanges the content of DE and HL pair

3 8 EE EC 9. (c) CMA does not affect any flag.. (d) IN instruction reads the data present at port address 84 H into accumulator.. (a) MVI B, H ; Moves H to register B. So, B = H MVI A, C H ; Moves C H to register A So, A = C H DCR B ; Decrements the contents of B by one B = FF H DAA ; Decimal adjust accumulator A = 22 H STA TEMP ; Stores the contents of accumulator at memory location TEMP HLT ; Halts the execution of program Thus, contents of TEMP are 22 H. 2. (d) 3. (a) LXI H, 98 H MOV A, L ADD H Mnemonics M-cycle T-states XRA A 4 MOV L, A 4 MOV H, L 4 INX X 6 DAD H 3 H = 9 : L = 8 H A = 8 H A + H = 9 H + 8 H = H = AC = DAA As = Hence DAA adds to the higher order bits to adjust binary result to BCD Hence A = A = 7 H MOV H, A H = 7 H PCHL H L 7 8 After execution of PCHL, the program counter has 78 H. So, the address of next instruction to be fetched will be 78 H.

4 CT-28 Microprocessors 9 4. (d) MVI A, 8 H LXI B, 24 H ADI 4 H PUSH PSW XTHL PUSH B JMP H HLT No effect on SP SP = SP 2 = 232 H Exchange the content of top of stack with HL pair. SP remains same. SP = 232 H SP = SP 2 = 23 H Unconditional Jump SP is not affected Halts the execution. 5. (c) Machine cycles F R W MVI M, 8F requires both memory read and memory write machine cycles, microprocessor first reads the data 8F from memory and then write the same at memory location whose address is stored in HL pair. 6. (b) Trap is also called as RST 4.5 Vector address = (4.5 8) = (36) = (24) H = (24) H INTR is a level triggered interrupt. 7. (a) 25 : MVI A, 3H A = (3) H 252 : LXI H, 25H HL = (25) H 255 : ADD M Content at memory location pointed by content of HL pair i.e. (25) H is added to A and data at (25) H is 3H. So after addition, content of A will become double. 8. (d) In CALL SP decremented by 2 In POP SP incremented by 2 So, from the given program, SP will not be affected after final execution and content of HL pair is same as that of initial content of SP. SP = 27FF H and HL = 6 H 9. (d) LDA 75 H ; Load the contents in location 75 H to accumulator. CMA ; Complement accumulator is performed. INR A ; Increment A by one (A A + H) i.e. 2 s compliment. STA 75 H ; Store contents of accumulator to memory location 75 H. HLT ; Halt the program Contents in location 75 H are two s complemented. 2. (a) LXI SP, 9 H ; SP 9 LXI H, 5D H ; HL 5D PUSH H ; SP = SP 2 = 8FFE H POP PSW ; Pop the contents 5D onto PSW register.

5 EE EC In pop PSW SP SP + 2 i.e. 2 B on top of stack is accessed into A and F PSW = A F = 5D Flag register = S Z AC P 2. (c) RM is conditional return instruction. When sign flag is set, RM is executed with three machine cycles (opcode fetch, memory read, memory read) and 2 T states. 22. (b) When XRA instruction is executed sign, zero, parity flags are modified to reflect the result operation with carry and auxiliary flags being reset. 23. (b) PSW register is; PSW = Accumulator + S Z X AC X P X Flag register MVI A, F H ; move data FH immediately to accumulator MVI B, F H ; move data F H immediately to register B. ADD B ; add content of A and register B and then store in accumulator A. A = F = B = F = Flag register = X is a don t care bit, Then from given options the answer is, PSW = 24. (b) Stack over flow occurs while execution of a program is interrupted due to logical faults. So it is a program dependent, hence internal interrupt is activated. 25. (a) MOV H, B ; Move the content of register B to H. MOV L, C ; Move the content of register C to L. XCHG ; exchange HL and DE register pairs contents. MOV B, H ; move the content of register H to B. MOV C, L ; move the content of register L to C. 26. (b) Accumulator is initially loaded with C4 H. Instruction ORA A resets the carry flag.

6 CT-28 Microprocessors RRC RAL RRC Finally accumulator content is A = 62 H 27. (d) As IO/M = Logic high input/output operation RD = Logic low read operation (input) Address = 4242 H port address is 42 H instruction is IN 42 H 28. (c) A 5 A 4 = ( E = enable if E = ) A 3 A 2 A = ( E 2 = enable if E 2 = ) A A 9 A 8 = (To select Y 4 ) Address range is = 34 H = 34FF H 29. (a) MVI, B, H ; load content into register B. MVI C, 8 H ; load content 8 into register C. MOV A, D ; move the contents of register D to A. BACK : RAR ; Rotate accumulator contents right with carry JNC SKIP ; If = ; jump to SKIP INR B ; Increment counter B. SKIP: DCR C ; Decrement content of C by one. JNZ BACK ; If Z =, jump sequence to BACK else halt. HLT ; Halt Here clearly we can notice contents of register D are taken to A to number of ones. The number of s are stored is count register B. 3. (c) The loop is executed four times adding the contents of accumulator with decremented contents of register B. A = A = (6) A = () H

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:

Serial : 01. ND_EE_NW_Microprocessors_150718 Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: E-mail: info@madeeasy.in Ph: 011-45124612 CLASS TEST 2018-19 ELECTRICAL